UNIT-I

Intel 8086 Microprocessor

Features of 8086 Microprocessor:

• 1978 - Intel released its first 16-bit microprocessor - 8086.
• Executes the instructions at 2.5 MIPS (i.e. 2.5 million Instruction per second).
• Execution time of one instruction - 400ns (=1/MIPS=1/(2.5x106)).
• Width of the address bus is 20 bits.
• Width of the data bus is 16 bits.
• 8086 can also address one megabytes (1MB=220 bytes) of memory.
• Another feature in 8086 - presence of a small 6-byte instruction queue - so instructions fetched from
memory are placed in it before they are executed.
• Higher execution speed - larger memory size.
• Supports segmented memory.
• Supports pipelining technique.
Architecture of 8086:
It is subdivided into two units –
- The execution unit (EU) and
- The bus interface unit (BIU)
The execution unit (EU):
The EU tells the BIU where to fetch instruction or data from, decodes and executes the instructions using
the 16-bit ALU. It consists of a ALU, eight 16-bit general purpose registers (AX, BX, CX, DX, SP, BP,
SI and DI), a 16 bit flag register.
The bus interface unit (BIU):
The BIU computes 20 bit address and sends out addresses. It fetches instructions from the memory, reads
and writes data from ports and memory, writes data to output ports. It consists of an adder for address
calculations, four 16-bit segment registers (CS, DS, SS and ES), a 16 bit instruction pointer (IP), a 6 byte
instruction queue and bus control logic.
.

Fig: Architecture of 8086

EXECUTION UNIT:

Arithmetic & Logic Unit: A 16-bit ALU to perform arithmetic & logic operations. It fetches the operands
from the registers or memory locations and performs the operation according to the instruction given by
the user. The result can be stored either in the registers, memory locations can be sent to the output device.

General purpose registers:

The general data registers can be used as 8 bit registers (AH/AL, BH/BL, CH/CL, DH/DL or as 16 bit
registers (AX, BX, CX, DX).
AX/AL (Accumulator): It is used as accumulator. It is used to store data and for multiply, divide,
input/output (I/O) and some of the decimal and ASCII adjustment instructions.
BX (Base register): It holds the offset address of a location in memory also used to refer the data in
memory using lookup table technique with the help of XLAT instruction.
CX (Count register): It is used to hold the count while executing repeated string instructions
(REP/REPE/REPNE) and LOOP instruction also used to hold the count while executing the shift and
rotate instructions. Count value indicates the number of times the same instructions has to be executed.
DX (Data register): It is used to hold a part of the result during multiplication and part of the dividend
before a division also used to hold the I/O device address while executing IN and OUT instructions
SP (stack pointer): It holds the offset address of the data stored at the top of stack segment used along
with SS register to decide the address at which data is pushed or popped during the execution of PUSH
and POP instructions.
BP (Base Pointer): It used to hold the offset address of the data to be read from or write into the stack
segment.
SI (Source Index register): It holds the offset address of source data in data segment while executing
string instructions.
DI (Destination Index register): It holds the offset address of destination data in extra segment while
executing String instructions.
Flag Register: The 8086 flag register contents indicate the results of computation in the ALU. It also
contains some flag bits to control the CPU operations.

Bus Interface Unit (BIU):

• Code segment register (CS): It consists of starting address or segment address of the code segment
which is used for addressing memory location in the code segment of the memory, where the
executable program is stored.
• Data segment register (DS): It consists of starting address or segment address of the data segment
which points to the data segment of the memory where the data is stored.
• Extra Segment Register (ES) : It consists of starting address or segment address of the extra segment
which refers to a data in the extra segment in the memory.
• Stack Segment Register (SS): It consists of starting address or segment address of the stack segment
which is used for addressing stack segment which is used to store stack data.
• Instruction pointer register (IP) : It holds an offset address of the instruction to be executed. That is
it holds an offset address of the code segment.
• Instruction Byte Queue:
The BIU fetches up to 6 instruction bytes for the following instructions. The BIU stores these
prefetched bytes in first-in-first-out (FIFO) register set called a queue. When the EU is ready for
its next instruction it simply reads the instruction byte(s) for the instruction from the queue in the BIU.
• Adder: It computes 20 bit physical address. The complete physical address which is 20-bits long is
generated using segment and offset registers, each 16-bits long.
 Flag register of 8086:

A flag is a flip-flop which indicates some condition produced by the execution of an instruction, or controls
certain operations of the EU. The flags classified into
1. Status flags and
2. Control flags

Status flags: These are CF, PF, AF, ZF, SF and OF. They indicate the status of the result that is obtained
after the execution of arithmetic or logic instruction.

Control flags: These are DF, IF and TF. They can control the operation of CPU.

Fig: Flag Register/PSW

 CF (Carry Flag) - This flag is set, when there is a carry out of MSB in case of addition or a borrow in
case of subtraction otherwise reset.
 PF (Parity Flag) - This flag is set to 1, if the lower byte of the result contains even number of 1’s
otherwise reset.
 AF (Auxiliary Carry Flag) - This is set, if there is a carry from the lowest nibble, during addition, or
borrow for the lowest nibble during subtraction.
• ZF (Zero Flag) - This flag is set when the result of an arithmetic or logic operation is zero otherwise
reset.
• SF (Sign flag) - This flag is set, when the result of any computation is negative otherwise reset. Sign
flag equal to the MSB of the result. SF=1 indicates Negative and SF=0 indicates Positive.
• TF (Trap Flag) –If this flag is set, the processor enters the single step execution mode. In other words,
a trap flag is generated after execution of each instruction.
• DF (Direction Flag) – It selects either the increment or decrement mode for the DI and/or SI register
during the execution of string instructions. If D=0 the registers are automatically incremented. If D=1
the registers are automatically decremented.
• IF (Interrupt Flag) – It controls the operation of the ‘INTR’ interrupt pin of 8086 - If I=0 - INTR pin
is disabled - If this flag is set, the maskable interrupt are recognized by the CPU, otherwise they are
ignored.
• OF (Overflow flag) - This flag is set, if an overflow occurs, i.e, if the result of a signed operation is
large enough to accommodate in a destination register. The result is of more than 7-bits in size in
case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, then the
overflow will be set.