Data Converter Fundamentals

A/D & D/A

Dr. Menka Yadav
Deptt of ECE
MNIT Jaipur
INDIA
 Nyquist Rate vs Oversampling
• Nyquist-rate converters- => 1.5 to 10 time of
Nyquist rate
• Oversampling converters increase SNR by
operating much faster than the input signal’s
Nyquist rate (10 to 512 time of 2fm) and
filtering out quantization noise outside of the
signal bandwidth

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 IDEAL D/A CONVERTER

Ideal D/A Converter Input & Output transfer curve for D/A

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 IDEAL A/D CONVERTER

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 QUANTIZATION NOISE

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 Deterministic approach

Vin is sawtooth wave

Vin is Sine wave

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 PERFORMANCE LIMITATIONS
• Resolution-N-bit resolution means N bit digital input
or output or
• Offset and Gain Error-

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 Offset & Gain error

INL & DNL Errors

•Linearity & Accuracy

• Absolute accuracy - includes the offset, gain, and linearity errors. &
• Relative accuracy (Max. INL)– after removing the offset & gain errors
• INL- deviation from straight line
•DNL- variation in step size away from 1 LSB
•INL & DNL are measured at low frequencies so these are static
nonlinearities.

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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• Monotonicity (D/A converter )- maximum DNL 1 LSB or INL
0.5 LSB guarantees monotonicity (No slope change)
• Missing Codes (A/D converter)- maximum DNL 1 LSB or INL
0.5 LSB guarantees no missing codes
• A/D Conversion Time -acquisition + input signal time
• Sampling Rate-inverse of conversion time (differs for pipelined
converters)
• D/A Settling Time- Outputs settle within 0.5 LSB; Sampling
Rate –typically inverse of settling time
• Sampling-Time Uncertainty- Aperture jitter
• Dynamic Range- signal-to-noise and distortion ratio (SNDR ).
Max/Min amplitude

Effective number of bits are always <N, is a good measure of dynamic range.

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

2/7/2024 9
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 A/D converters

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 Integrating or Dual Slope ADC

•Phase 1- Constant time (T1 = 2^N.Tclk)- to charge

• Phase 2 – Constant Slope

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 Integrating or Dual Slope ADC

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 SUCCESSIVE-APPROXIMATION CONVERTERS

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 D/A converter based SAR ADC

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 Charge-Redistribution SAR A/D
• 1. Sample mode: all the capacitors are charged to while the comparator is
being reset to its threshold voltage through S2 , In this step, note that the
capacitor array is performing the sample-andhold operation.
• 2. Hold mode: Next, the comparator is taken out of reset by opening S2 ,
and then all the capacitors are switched to ground. This causes Vx, which
was originally zero, to change to -Vin, thereby holding the input signal, Vin
, on the capacitor array. Finally, S1 is switched to Vref so that can be
applied to the capacitor array during bit cycling.
• 3. Bit cycling: Next, the largest capacitor (i.e., the capacitor in this
example) is switched to Vref. Vx now goes to (-Vin+Vref/2). If Vx is
negative, the MSB capacitor is left connected to Vref & b1 is considered to
be a 1. Otherwise, the MSB capacitor is reconnected to ground and is
taken to be 0.
• This process is repeated times, with a smaller capacitor being switched
each time, until the conversion is finished for N+1 cylces

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
2/7/2024 16
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 RC Delay calculation
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Resistor Capacitor hybrid SAR ADC

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 Multibit SAR ADc

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 Pipelined Converters
•Uses SAR or Algorithmic converters *Performs iterative search for a digital code
•Speed- First sample after N+1 cycle and continous samples after that in every cycle

Signal flow for Pipelined ADC

One bit per stage pipelined converter stage & input vs output characteristics

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

MDAC-
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 One bit per stage pipelined converter stage & input vs output
characteristics

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 1.5 bit per stage pipeline converter

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 1.5 bit per stage pipelined converter stage

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 a) 1.5 gain & b) two times gain implementation for MDAC

K-bit per stage pipelined ADC

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 Pipeline ADC points to remember
• Introducing redundancy between successive stages in a
pipelined converter permits simple digital correction of any
offset in the comparators of each stage.
• Pipelined A/D converter performance is limited by
nonlinearities and noise in the MDAC, and inaccuracy in the
interstage gain, none of which are cancelled by simple digital
correction.
• Multiple bits (k-bit per stage) can be resolved in each stage,
with digital correction, in order to reduce the number of
opamps in a pipelined converter and decrease the number of
clock cycles required for each conversion.

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

2/7/2024 25
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 FLASH ADC
• Flash converters are generally capable of the
fastest conversion speeds of any A/D
architecture. However, their power
consumption grows dramatically with the
required resolution so they are usually
reserved for converters where high speed and
low or modest resolution is sought.

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

2/7/2024 26
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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 FLASH ADC
• Highest speed
• Number of comparators increases with resolution
• Moderate or low accuracy

A clocked CMOS
Dr. Menka Yadav, Comparator
ECE Deptt, MNIT Jaipur,
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 Flash ADC Designing Isuues
• Input capacitive loading
• Resistor string bowing
• Comparator latch to track delay
• Signal and/or clock delay
• Substrate and power supply noise
• Bubble error removal
• Flashback

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 Interpolating ADC
• Input amplifiers
• Linear amplifiers
• Saturate once difference input is moderately
greater than threshold
• Lesser number of input amplifier
• Used with folding ADC but also used
separately
• Logic 0-5, threshold 2.5, gain -10
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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 Folding ADC
• Lesser number of comparator
• Like two step converter
• MSB- LSB separately

Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,

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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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 Folding +Interpolating

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 Dr. Menka Yadav, ECE Deptt, MNIT Jaipur,
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