A

Micro-project report on

“Generate PN sequence For Given Maximum Length”

Submitted by

Roll No. Name of students

EJ-220 Ruturaj Swami

EJ-247 Vedant Madhekar

EJ-249 Gulshan Kumar

EJ-252 Ritesh Shinde

EJ-267 Om Gaikwad

UNDER THE GUIDANCE OF

(Mr. Bagban S. R.)

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION

ENGINEERING

Shanti Education Society’s

A.G. Patil Polytechnic Institute, Solapur.

NBA Accredited Programs

ACADEMIC YEAR (2023-2024)

 Shanti Education Society’s

A.G. Patil Polytechnic Institute, Solapur.

CERTIFICATE

This is to certify that the micro-project report on “Generate P-N Sequence For Given
Max Length” has been submitted by EJ-(220,247,249,252,267,) of S.Y. (Electronics and
Telecommunication Engineering) has completed predefined micro project satisfactorily in
course Digital Communication Systems (22428) for the academic year 2023-2024 as prescribed
in the curriculum of M.S.B.T.E.

Course Co-ordinator Program Head

(Mr. Bagban S. R.) (Mr. Bagban S. R.)

PRINCIPAL

Dr. Chougule M. A.

(A.G.P.P.I. SOLAPUR)
 Title: - “Generate PN Sequence For Given Maximum Lenght "

1. INTRODUCTION: -
Pseudo-Noise (PN) Sequences are binary sequences that have the length of n = 2m-1. Pseudo-
Noise Sequences are also called pseudo-random sequences, maximal-length shift-register
sequences, or m-sequences [1]. PN Sequence is a periodic signal which can be locally
generated in both transmitter and receiver. Therefore, PN sequences can be utilized as wide
bandwidth signal for radar ranging and remote synchronization with high accuracy [2]. PN
Sequence is a deterministic signal which has a finite length. This length might vary; however,
for a specific condition, it has a maximum length (n = 2m-1). Each bit in the pseudo-noise
sequence is called chip [3]. PN Sequences can simply and stably be generated by digital circuits
using Linear Feedback Shift Registers (LFSR). These digital circuits are combination of clock
generation network, D type flip-flops, and exclusive-or gate. A feedback mechanism is formed
with the help of flip-flops and exclusive-or gate, which generates PN sequence. PN sequences
can be implemented on FPGA by using VHDL [4], [5], [6]. However, in this paper hardware
implementation with integrated circuits (ICs) which can be found on the market is proposed to
lower the cost and design a PN sequence generator block that can be used for many systems.

2. Working of Circuit: -
Peudo-Noise sequences or (PN) are randomized spreading sequences , that resembles noise
signals , used in many wireless communications standards [ such as : CDMA-2000 and UMTS]
, to spread the transmitted data sequences over longer sequences of 0s and 1s , which makes it
more powerful against fading and noise effect

Circuit Diagram: -
 ➢ IC 7474

IC 7474 or mostly known as IC 74LS74 is a dual D Flip Flop positive edge-triggered IC. It has two
indep and a Q output. The data in the D input may be changed during the high or low clock but it does
not affect the output and the delay times also do not affect it. The IC 7474 can be operated up to 7V
voltage and 0 to +70 degrees centigrade temperature. The main features of the IC 74LS74 are, that it
provides very fast switching, low propagation delay, large operating mode, etc.

➢ Pin Configuration of IC7474

➢ Truth table of IC7474

➢ Features of IC 7474:-

• Two D-Type Flip-Flops.

• Outputs Directly Interface to CMOS, NMOS and TTL.
• Large Operating Voltage Range.
• Wide Operating Conditions.

➢ Specifications of IC7474: -
• Supply voltage: 7V.
• Input voltage: 7V.
• Free-air temperature range: 0°C to +70°C.
• Storage temperature range: –65°C to +150°C.
 ➢ IC 7486

7486 is Quad 2-Input EXOR Gate 14 Pin IC. It is an advanced high-speed CMOS 2−input
Exclusive−OR gate fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power
dissipation. Internal circuit is composed of three stages, including a buffer output which
provides high noise immunity and stable output. Inputs tolerate voltages up to 7V, allowing
interface of 5V systems to 3V systems. Used for Building Arithmetic Logic Circuits,
Computational Logic Comparators and Error Detection Circuits and True/Complement
Element.

➢ Pin Configuration of IC7486

 ➢ Truth table of IC 7486

➢ Features of IC7486: -
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 6V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families

➢ Specifications of IC7486: -
• Type: Quad
• Material: Plastic
• Number of Pins: 14 Pins
• Mounting: Through Hole
➢ Components Required: -

Sr No. Particulars Specification Quantity

1. Resistor 230 ohms 4

2. Battery 9V 1
3. Connecting Wire -------- --------
4. Bread Board 5.5cm x 17cm 1
5. LED 1.8V to 2.2V 1 Each

6. Battery -------- 1
Connector
7. IC 7486 TTL Family 1
8 IC 7474 TTL Family 2

➢ Applications: -

• Interdevice signaling.
• Shift-register.
• Memory-address identification.
• Position measurement in machinery control.

➢ Advantages :-

• Increased capacity.
• Improved voice quality.
• Reduced average transmitted power.

➢ Disadvantages: -

• Wide bandwidth per user required.

• Precision code synchronization needed
➢ Aim of Micro Project: -

Develop a PN Sequence generator and test for various input sequence.

➢ CO’s Covered: -

CO5: - Maintain spread spectrum based systems.

➢ Action Plan:-

Serial Planned Planned Name of Responsible

Details of Activity
No. Start Date Finish Date Team Members

Group formation & topic 10/01/2024 12/01/2024 All Group Members

1.
selection discussion.

Discussion of group with 16/01/2024 19/01/2024 All Group Members

2.
project guide.

20/01/2024 25/01/2024
3. Finalization of topic. All Group Members

02/02/2024 07/02/2024 Vedant Mahadekar &

Data collection & Arrangement
4. Om Gaikwad
of data.

5. Preparation of model. 08/02/2024 25/02/2024 Gulshan Kumar

6. Data correction. 27/02/2024 05/03/2024 Gulshan Kumar

07/03/2024 10/03/2024
7. Preparation of proposal.
Ruturaj Swami
07/03/2024 13/03/2024
8. Presentation of proposal.

9. Data collection through internet. 13/03/2024 20/03/2024 Ritesh Shinde

10. Submission of model 21/03/2024 24/03/2024 All Group Members

11. Preparation of report. 25/03/2024 02/04/2024

Ruturaj Swami
03/04/2024 06/04/2024
12. Presentation of report.
09/04/2024
Final submission of the
13. All Group Members.
Microproject
➢ Resources Required: -
Sr. Name Of Resources/ Specification. Qty Remarks
No. Material. .

www.google.com
Designing a Hamming
Coder/Decoder Using
QCAs (scialert.net)
74HC86 - Bing images
Google Image Result
1. Internet https://www.factoryforwa 4 Search engine
rd.com/product/7486-xorgate-
ic-dip-
14package/#:~:text=7486%
20is%20Quad%202%2DI
nput,maintaining%20CM
OS%20low%20power%2
0 dissipation.
Computer
2. Microsoft World 1 Documentation
Facility
IC 8
Resistors 4
Components LED 4
3. Components
used in Project
General purpose PCB 1
Battery 1
Battery Switch 1
Electronic Communication
Systems.
Reference (Tomasi, Wayne)
4. 2 Books
Books Digital Communication
(Sklar, Bernald)
➢ Output of Microproject: -
Skills developed/ Learning out of this Microproject: -
a. Component identifications skills.

b. Handle components & equipment carefully.

c. Other skills such as critical thinking, collaboration, and creativity.

d. Communication between group members.