Professional Documents
Culture Documents
glossary
glossary
July 2001
Altera Corporation 1
Glossary
ARM A hard embedded RISC processor core Block Design File (.bdf) A schematic design file
licensed from ARM® Limited used to created with the Quartus II Block Editor. BDFs
implement processing functionality in may contain block diagrams, symbols, and
ExcaliburTM devices. Altera embeds the ARM schematics that represent logic in a design. You
processors into Excalibur devices to provide can read and edit BDFs in the Block Editor.
customers with a processor and programmable
logic on a single device. ByteBlasterMV cable (The ByteBlasterTM cable is
obsolete and has been replaced by the
array clock A clock signal that passes through ByteBlasterMVTM cable). A parallel download
the logic array of a device before arriving at the cable that allows PC users to program and
clock input of a register. configure devices in-system. The ByteBlaster
parallel port download cable provides
Assignment & Configuration File (.acf) An ASCII programming support for MAX® 9000,
file for the MAX+PLUS II software that stores MAX 7000S, MAX 7000A, MAX 7000B, and
information about probe, resource, and device MAX 3000A devices, and configuration
assignments for a hierarchy tree, as well as the support for MercuryTM, APEX, ACEXTM, and
configuration information for the Compiler, FLEX® devices. APEX, Mercury, and ACEX
Simulator, Timing Analyzer, and Programmer. devices can be configured together in a chain.
All information that can affect output files FLEX 8000 devices cannot be configured with
containing design information for the current other devices.
hierarchy tree is controlled by the ACF.
C
B
carry chain A dedicated architectural feature
ball-grid array (BGA) A high-performance of the Mercury, APEX II, APEX 20K,
device package offered by Altera that allows for FLEX® 10K , FLEX 8000, FLEX 6000, and
higher pin counts in significantly less board ACEX 1K device families that provides a high-
area than quad flat pack (QFP) packages and performance carry-forward function between
has better thermal characteristics than most logic elements (LEs). The carry-in signal from a
QFP packages. BGA packages are rapidly lower-order bit moves forward into the higher-
becoming the preferred packages for high- order bit via the carry chain, and feeds into both
density PLDs. See the Altera Device Package the look-up table (LUT) and the next portion of
Information Data Sheet and Ordering Information the carry chain. The carry-forward function is
for more information. ideal for adders, counters, and comparators.
2 Altera Corporation
Glossary
ACEX 1K families that allows implementation ClockLock An Altera high-density PLD feature
of high-performance, wide fan-in functions. available in Mercury, APEX II, ACEX 1K
Adjacent LUTs can be used to compute devices, and selected FLEX 10K devices that
portions of a function in parallel; the cascade uses phase-locked loops (PLLs) to eliminate
chain serially connects the intermediate values. clock skew inside the PLD, improving system
performance. Combining the ClockBoost and
ceramic dual in-line package (CerDIP) A device ClockLock features provides significant
package offered by Altera. See the Altera Device advantages in system performance and
Package Information Data Sheet and Ordering bandwidth.
Information for more information.
clock-data recovery (CDR) A type of high-
Ceramic J-lead chip carrier (JLCC) A device speed serial interface in which the clock is
package offered by Altera. Both JLCC and encoded into the data stream rather than sent as
plastic J-lead chip carrier (PLCC) packages are a separate signal. A device uses CDR to recover
available. See the Altera Device Package the clock from the data stream and make both
Information Data Sheet for more information. signals available to logic within the device.
Since no separate clock signal is required, there
ceramic quad flat pack (CQFP) A device is no clock-to-channel skew requirement. CDR
package offered by Altera. See the Altera Device offers high-speed data transfer while easing
Package Information Data Sheet and Ordering board design requirements.
Information for more information.
Compiler Settings File (.csf) The Compiler
Certified Design Center (CDC) Altera has partnered Settings File (.csf) is an ASCII file that stores the
with design services leaders to create the CDC. CDC chip definitions for a Quartus II project, the
members provide SOPC design services, including default device options, the compilation focus,
IP integration and Excalibur-based designs, for the type of compilation to perform, the device
Altera customers. family and device to use, and other options.
Classic An Altera device family based on configuration device Altera’s family of serial
Altera’s original EPROM-based EPLD devices that are designed to configure Mercury,
architecture. The Classic™ device family APEX, Excalibur, FLEX, and ACEX devices. See
includes the EP600I, EP610I, EP900I, EP910I, the Configuration Devices for ACEX, APEX, FLEX
EP1800I, and EP1810 devices. & Mercury Devices Data Sheet for more
information.
ClockBoost An Altera high-density PLD
feature available in Mercury, APEX, ACEX 1K, configuration scheme The method used to load
and selected FLEX 10K devices that uses phase- data into Mercury, APEX II, APEX, FLEX, and
locked loops (PLLs) to multiply or divide the ACEX devices.
clock, improving system performance.
Combining the ClockBoostTM and ClockLockTM Five configuration schemes are available for
features provides significant advantages in Mercury, APEX II, APEX, FLEX 10K, and
system performance and bandwidth. ACEX devices: configuration device, passive
serial (PS), passive parallel asynchronous
(PPA), passive parallel synchronous (PPS), and
IEEE Std. 1149.1 Joint Test Action Group
(JTAG). For complete information on
configuration schemes, see AN 116: Configuring
Altera Corporation 3
Glossary
APEX 20K, FLEX 10K, and FLEX 6000 Devices. programmable logic devices with the same
fundamental architecture. Altera device
Six configuration schemes are available for families include the Mercury, APEX 20K,
FLEX 8000 devices: active serial (AS), active APEX II, FLEX 10K, FLEX 8000, FLEX 6000,
parallel up (APU), active parallel down (APD), MAX 9000, MAX 7000, MAX 3000A,
PPA, PPS, and PS. For complete information on MAX 5000, ACEX 1K, and Classic device
FLEX 8000 configuration schemes, see AN 33: families. Altera also offers a configuration
Configuring FLEX 8000 Devices and device family that includes devices used for
AN 38:Configuring Multiple FLEX 8000 Devices. configuring Mercury, APEX II, APEX 20K,
FLEX 10K, FLEX 8000, FLEX 6000, and
Three configuration schemes are available for ACEX 1K devices.
FLEX 6000 devices: configuration device,
passive serial (PS), and passive serial double data rate (DDR) A RAM interface
asynchronous (PSA). For complete information standard.
on FLEX 6000 configuration schemes, see AN
116: Configuring SRAM-based LUT Devices. dual in-line package (DIP) A device package
offered by Altera. See the Altera Device Package
content-addressable memory (CAM) A memory Information Data Sheet for more information.
technology that searches for data by content Ceramic (CerDIP) and plastic (PDIP) versions
rather than by address. are available.
continuity checking A test for open circuits dual-port RAM The Mercury, APEX II, and
between device pins and programming adapter APEX 20K embedded system block (ESB) and
sockets. This test verifies that a device is the FLEX 10KE embedded array block (EAB)
properly seated in the socket of the adapter. support dual-port RAM with independent
read/write ports, synchronous or
asynchronous access, and 150+ MHz first-in
first-out (FIFO) buffer performance. This
D system-level memory integration efficiently
supports the various RAM requirements of a
dedicated input pin A pin that can only be used system-level design, such as cache RAM, dual-
as an input to the device. port FIFO buffers, or ROM.
4 Altera Corporation
Glossary
EDIF Input File (.edf) An EDIF version 200 or embedded array A series of embedded array
300 netlist file generated by any industry- blocks (EABs) in FLEX 10K devices used to
standard EDIF netlist writer. EDIF Input files implement a variety of memory functions or
can be compiled by the Quartus II and complex logic functions, such as digital signal
MAX+PLUS II software. The Quartus II and processing (DSP), microcontrollers, wide
MAX+PLUS II software supports EDIF Input datapath manipulation, and data
Files that contain functions from the library of transformation functions.
parameterized modules (LPM).
embedded array block (EAB) The building block
EDIF Output File (.edo) An EDIF version 200 or of embedded arrays in FLEX 10K devices. Each
300 netlist file generated by the EDIF Netlist EAB provides 2,048 or 4,096 bits of configurable
Writer module of the Quartus II and RAM, ROM, first-in first-out (FIFO), or dual-
MAX+PLUS II software. This file can be port RAM. When implementing logic, each EAB
exported to an industry-standard UNIX can contribute 100 to 300 gates towards complex
workstation or PC environment for simulation logic functions.
in third-part simulation software.
embedded system block (ESB) The embedded
electrically erasable programmable read-only system block is part of the APEX II and
memory (EEPROM) A form of reprogrammable APEX 20K devices. Each ESB contains 2,048
semiconductor memory in which the contents programmable bits that can be configured as
can be erased by subjecting the device to quad-port RAM, bidirectional dual port RAM,
appropriate electrical signals. See the Operating dual-port RAM, look-up table-based logic,
Requirements for Altera Devices Data Sheet for ROM, or content-addressable memory (CAM).
more information.
EP Family signature on a part number that
Electronic Design Interchange Format (EDIF) An refers to the APEX 20K, APEX II, and Classic
industry-standard format for the transmission device families.
of design data. You can generate an EDIF 200 or
300 netlist file from a schematic design or from EP1K Family signature on a part number that
a VHDL design that has been processed with an refers to the ACEX 1K device family.
appropriate industry-standard synthesis tool.
You can then import the file into the Quartus II EP1M Family signature on a part number that
and MAX+PLUS II software as an EDIF Input refers to the Mercury device family.
File (.edf). The Quartus II and the
MAX+PLUS II software supports EDIF Input EP2A Family signature on a part number that
Files that contain functions from the library of refers to the APEX II device family.
parameterized modules (LPM). The Quartus II
and MAX+PLUS II compilers can also generate EPC Family signature on a part number that
one or more EDIF Output Files (.edo) in either refers to configuration devices.
EDIF 200 or 300 format that contain functional
and timing information for simulation with a EPF Family signature on a part number that
standard EDIF simulator. refers to the FLEX device family.
Altera Corporation 5
Glossary
refers to the ARM-based Excalibur embedded packages. See the QFP Carrier & Development
processor solutions. Socket Data Sheet for more information.
6 Altera Corporation
bypassing local interconnect. FastLUTTM unit that stores a single bit of data. A low-to-
interconnect is implemented in Mercury high transition on the clock signal changes the
devices. output of the flipflop based on the value of the
data input(s). This value is maintained until the
Fitter The Compiler module in the Quartus II next low-to-high transition of the clock, or until
and MAX+PLUS II software that fits a project the flipflop is preset or cleared. Depending on
into one or more devices. The Fitter selects the architecture of the device family, a register
appropriate interconnection paths as well as the can be programmed as a level-sensitive flow-
pin and logic cell assignments. through latch or as an edge-triggered D, T, JK,
or SR flipflop.
Flexible-LVDS Dedicated LVDS input and
output buffers built into general-purpose I/O
pins. Also supports LVPECL and other
differential standards, depending on the device G
family. The Flexible-LVDSTM feature also
supports data transfer rates up to 624 Mbps, global clear A signal from a dedicated input
resulting in up to 110 Gbps of additional pin or logic element (LE) that does not pass
differential bandwidth. through the logic array before arriving at the
clear input of a register. In FLEX 8000 devices,
FLEX 10K An Altera device family based on the global clear can come from any of the dedicated
Flexible Logic Element MatriX (FLEX) inputs. In Mercury, APEX 20K, APEX II,
architecture. This SRAM-based family offers FLEX 10K, FLEX 6000, and ACEX 1K devices, a
high-performance, register-intensive, high- global clear can come from any dedicated input
gate-count devices with embedded arrays. The or from an LE. MAX 9000, MAX 7000, and
embedded arrays are used to implement MAX 3000A devices have input pins that can be
memory or complex logic functions efficiently. used either as a global clear sources or as
See the FLEX 10K Embedded Programmable Logic dedicated inputs to the device.
Family Data Sheet and FLEX 10KE Embedded
Programmable Logic Family Data Sheet for more global clock A signal from a dedicated input
information. pin or LE that does not pass through the logic
array before arriving at the clock input of a
FLEX 6000 An Altera device family based on register. In FLEX 8000 devices, a global clock
the OptiFLEX® architecture. This SRAM-based can come from any of the four dedicated input
family offers high-performance, register- pins. Mercury, APEX II, APEX 20K, FLEX 10K,
intensive, high-gate-count devices. See the FLEX 8000, FLEX 6000, MAX 9000, MAX 7000,
FLEX 6000 Programmable Logic Device Family MAX 3000A, MAX 5000, and ACEX 1K devices
Data Sheet for more information. have input pins that can be used as either global
clock sources or dedicated inputs to the device.
FLEX 8000 An Altera device family based on EP910 and EP610 devices have dedicated clock
the Flexible Logic Element MatriX (FLEX) input pins. In Mercury, APEX II, APEX 20K,
architecture. This SRAM-based family offers FLEX 10K, and FLEX 6000 devices, an LE can
high-performance, register-intensive, high- also generate a global clock signal.
gate-count devices. See the FLEX 8000
Programmable Logic Device Family Data Sheet for Graphic Design File (.gdf) A schematic design
more information. file created with the MAX+PLUS II software.
The Quartus II software can read GDF files but
flipflop An edge-triggered, clocked storage does not produce them.
Altera Corporation 7
I/O cell Also known as an I/O element; a
register that exists on the periphery of a
H Mercury, APEX II, APEX 20K, FLEX 10K,
FLEX 8000, MAX 9000, or ACEX 1K device, in
Hexadecimal (Intel-Format) File (.hex) A an I/O band of a Mercury device or a fast input-
hexadecimal file in the Intel Hex format. The type logic cell that is associated with an I/O pin
Quartus II and MAX+PLUS II Compilers and in MAX 7000E, MAX 7000S, MAX 7000A, and
Simulators can use HEX files as inputs to specify MAX 7000B devices. I/O cells give short set-up
the initial memory contents. After compilation, and clock-to-out times.
you can also create HEX files that support
configuration schemes for Mercury, APEX,
FLEX, and ACEX 1K devices.
J
high-speed differential interface (HSDI) Supports
clock-data recovery (CDR) in Mercury devices. Jam Language An open-standard language for
In a Mercury HSDI I/O band, half of the programming in-system programmability
dedicated banks support LVDS, PCML or (ISP)-capable devices. The JamTM language is
LVPECL, and receiver inputs, while the other supported by all versions of the Quartus II and
half support LVDS, PCML, or LVPECL, and MAX+PLUS II software. The Jam language is an
transmitter outputs. interpreted language that is optimized for
programming devices via the Joint Test Action
Group (JTAG) interface. The Jam language is
platform-independent, supports both new and
I existing ISP-capable devices, and has a small
interpreter code and file size.
in-system programmability (ISP) The capability
of EEPROM- or flash memory-based devices to Jam File (.jam) An ASCII Jam standard test
be programmed after they have been mounted and programming language (STAPL) file that
on a printed circuit board. Altera MAX 9000, stores programming data for programming,
MAX 7000S, MAX 7000A, MAX 7000B, verifying, and blank-checking one or more in-
MAX 7000AE, MAX 3000A, EPC4, and EPC16 system programmability (ISP)-capable devices
devices support ISP. in a JTAG chain. Jam files are used in embedded
processor or in-circuit (ICT) equipment
internal timing parameters Worst-case delays programming environments. Altera Mercury,
based on external timing parameters. Internal APEX II, MAX 9000, MAX 7000S, MAX 7000A,
timing parameters cannot be measured MAX 7000B, MAX 7000AE, ACEX 1K, EPC2,
explicitly, and should only be used for and EPC16 devices can be programmed with
estimating device performance. Post- Jam files; Mercury, APEX II, APEX 20K,
compilation timing simulation or timing FLEX 10K, and ACEX 1K devices can be
analysis is required to determine actual worst- configured with Jam files. In addition to the
case performance. In Altera literature, internal device(s) to be programmed or configured, the
timing parameters are shown in italic type. JTAG chain can contain any device that
complies with the IEEE Std. 1149.1 specification.
IP MegaStoreTM A web site offered by Altera
that makes intellectual property (IP) solutions JEDEC File (.jed) An ASCII file that contains
and information available to designers. programming information. JEDEC files provide
an industry-standard format for transferring
8 Altera Corporation
information between a data preparation system library of parameterized modules (LPM) An
and a logic device programmer. The architecture-independent library of logic
MAX+PLUS II Compiler automatically functions that are parameterized to achieve
generates JEDEC files for the following devices scalability and adaptability. Altera has
during compilation: EP610, EP6101, EP910, implemented parameterized modules from
EP910I, and EP1810 devices (Classic family) as LPM versions 2.0.1 to 2.1.0 that offer
well as EPM5032 devices (MAX 5000 family). architecture-independent design entry for all
The MAX+PLUS II Programmer can use a Quartus II and MAX+PLUS II software-
JEDEC file to program the Altera devices listed supported devices. The Quartus II and
above, in addition to FLASHLOGIC® devices. MAX+PLUS II Compilers include built-in
(All FLASHLOGIC devices are obsolete.) compilation support for LPM functions used in
Optionally, the Programmer can also optionally schematics, Altera Hardware Description
save programming data plus functional test Language (AHDL) TDFs, and EDIF Input Files.
vectors in JEDEC File format. The Quartus II
software does not support JEDEC files. logic array A series of logic array blocks (LABs)
that is used to implement general logic such as
Joint Test Action Group (JTAG) A set of counters, adders, state machines, and
specifications that enables a designer to perform multiplexers. The logic array performs the same
board- and device-level functional verification function as the sea-of-gates in gate arrays.
of a board during production.
logic array block (LAB) A physically-grouped
JTAG boundary-scan testing Testing that isolates set of logic resources in an Altera device. The
a device’s internal circuitry from its I/O LAB consists of a logic cell array and, in some
circuitry. This testing is made possible by the device families, an expander product-term
Joint Text Action Group (JTAG) boundary-scan array. Any signal that is available to any one
test (BST) architecture that is available in all logic cell in the LAB is available in the entire
Mercury, APEX II, APEX 20K, FLEX 10K, LAB. In Mercury, APEX 20K, APEX II,
FLEX 6000, MAX 9000, MAX 7000S, FLEX 10K, FLEX 8000, FLEX 6000, MAX 9000,
MAX 7000A, MAX 7000B, MAX 3000A, and and ACEX 1K devices, the LAB is fed by
ACEX IK devices, and all FLEX 8000 devices FastTrack interconnect paths and a dedicated
except the EPF8452A and EPF81188A devices. input bus. In MAX 7000, MAX 7000A,
Serial data is shifted into boundary-scan cells in MAX 7000B, MAX 3000A, and MAX 5000
the device; observed data is shifted out and devices, the LAB is fed by a programmable
externally compared to expected results. interconnect array (PIA) and a dedicated input
Boundary-scan testing offers efficient PC board bus. In Classic devices, the logic in the LAB
testing, providing an electronic substitute for shares a global clock signal. The LAB is fed by a
the traditional “bed of nails” type of test global bus and a dedicated input bus. In the
fixtures. EP1810 devices, LABs are called quadrants.
Altera Corporation 9
logic element (LE) A basic building block of can be programmed as a flow-through latch, as
Mercury, APEX II, APEX 20K, FLEX 10K, a D, T, JK, or SR flipflop, or bypassed entirely for
FLEX 8000, FLEX 6000, and ACEX 1K devices. pure combinatorial logic. The register can feed
A logic element consists of a look-up table other macrocells or feed back to the macrocell
(LUT)—i.e., a function generator that quickly itself. Some macrocells feed output or
computes any function of four variables—and a bidirectional I/O pins on the device. Macrocells
programmable register to support sequential in FLEX 10K, FLEX 8000, and FLEX 6000
functions. The register can be programmed as a devices are called logic elements.
flow-through latch, as a D, T, JK, or SR flipflop,
or bypassed entirely for pure combinatorial macrofunction A high-level building block that
logic. The register can feed other logic cells or can be used together with gate and flipflop
feed back to the logic cell itself. Some logic primitives in MAX+PLUS II design files. In
elements feed output or bidirectional I/O pins general, a macrofunction is a lower-level design
on the device. file in a MAX+PLUS II hierarchical project.
look-up table (LUT) A function that generates Master Programming Unit (MPU) A hardware
outputs based on inputs and a set of stored data. module that works with zero-insertion-force
The logic element of Mercury, APEX II, sockets and individual adapters to program and
APEX 20K, FLEX, and ACEX 1K devices test Altera devices. The PL-MPU base unit and
includes a four-input look-up table (LUT) that PLM-prefix adapters support both device
can be configured to emulate any logical programming and device testing. The PLE3-12
function of four inputs. base unit, as well as adapters with other
prefixes, support device programming only.
10 Altera Corporation
Logic Device Family Data Sheet for more megafunction An off-the-shelf building block
information. that implements useful functions such as
processors, digital signal processing (DSP)
MAX 7000 An Altera device family based on functions, bus controllers, and interfaces.
the second generation of Multiple Array MatriX
(MAX) architecture. MAX 7000A, MAX 7000B, MegaLAB A basic building block of the
MAX 7000AE, MAX 7000E, and MAX 7000S, APEX 20K MultiCoreTM architecture structure.
devices are enhanced versions of MAX 7000 Each MegaLAB structure contains between 10
devices and are function-, pin-, and and 24 logic array blocks (LABs), depending on
programming file-compatible with MAX 7000 device density, and an embedded system block
devices. MAX 7000A, MAX 7000AE, (ESB) that is configurable as dual-port RAM,
MAX 7000E, and MAX 7000S devices offer up to ROM, or content-addressable memory (CAM),
six pin- or logic-driven output enable signals, or as product-term macrocells.
fast input setup times to logic cells, and multiple
global clocks with optional inversion. In MegaWizard ® Plug-Ins Parameterization tools
addition, MAX 7000A, MAX 7000B, that help configure and customize
MAX 7000AE, and MAX 7000S devices feature megafunctions for individual designs.
ISP and JTAG boundary-scan test circuitry. The MegaWizard® Plug-Ins do not require the use of
MAX 7000A devices are also optimized for third-party tools.
3.3-V operation. See the MAX 7000
Programmable Logic Device Family Data Sheet, the Mercury A high-performance Altera device
MAX 7000A Programmable Logic Device Family family that is built for bandwidth. Mercury
Data Sheet, and the MAX 7000B Programmable devices are programmable application-specific
Logic Device Family Data Sheet for more standard products (ASSPs) that offer I/O
information. standards and a high-speed core used in the
communication and computer industries. They
MAX 9000 An Altera device family based on feature clock-data recovery (CDR) and source-
the third generation of Multiple Array MatriX synchronous differential I/O. See the Mercury
(MAX) architecture, with a higher density than Programmable Logic Device Family Data Sheet for
the MAX 7000 device family. See the MAX 9000 more information.
Programmable Logic Device Family Data Sheet for
more information. MultiCore Altera’s MultiCore embedded
architecture (featured in the APEX 20K device
MAX+PLUS II Altera’s Multiple Array MatriX family) is made up of logic array blocks (LABs)
Programmable Logic User System. The and combines three different types of PLD
MAX+PLUS II software is a set of computer structures: look-up tables (LUTs), product-term
programs and hardware support products that blocks, and enhanced memory blocks. Together,
allow design and implementation of custom these structures make the integration of
logic with ACEX 1K, FLEX 10K, FLEX 8000, complex functions, such as megafunctions, an
FLEX 6000, MAX 9000, MAX 7000, MAX 3000A, easy and efficient process.
MAX 5000, and Classic devices.
Altera Corporation 11
MultiVolt An interface that separates the power logic array block (LAB). A parallel expander is
supply from the output voltage, enabling Altera also a logic option that can be applied to a logic
devices powered at a specific core voltage to function to allow it to borrow such parallel
interface with devices using different voltage expanders. This option can reduce the number
levels. For example, the Altera FLEX 10KA of shared expander product terms required in a
family, which supports the MultiVolt feature, project and increase the speed of a project.
supports 5.0-V, 3.3-V, and 2.5-V levels. However, the project may use additional logic
cells, and may be more difficult to fit.
12 Altera Corporation
plastic quad flat pack (PQFP) A device package Compiler’s Assembler module. This file
offered by Altera. See the Altera Device Package contains the data used to program an Altera
Information Data Sheet and Ordering Information device. The MAX+PLUS II Programmer has the
for more information. option to save functional vectors in a POF.
PowerFit A place-and-route technology in the programming file A file containing data for
Quartus II software that uses the designer’s programming Altera devices. Both the
timing specifications to perform optimal logic Quartus II and MAX+PLUS II software can
mapping and placement. The PowerFit timing- generate programming files. The following
driven router algorithms prioritize which programming file formats are available.
routing resources are used for a critical timing
path in a design. Quartus II software: SRAM Object File (.sof),
Programmer Object File (.pof), Jam File (.jam),
PowerGauge An analysis tool in the Quartus II JAM Byte-Code File (.jbc), Serial Vector Format
software that uses the designer’s simulation File (.svf) Hexadecimal Output File (.hexout),
files to estimate power consumption with Serial Bitstream File (.sbf) and Raw Binary File
customer-specific design files and operating (.rbf).
parameters.
MAX+PLUS II software: FLEX Chain File (.fcf),
power quad flat pack (RQFP) A device package Hexadecimal (Intel-Format) File (.hex), Jam file
offered by Altera. See the Altera Device Package (.jam) JEDEC File (.jed) JTAG Chain File (.jcf),
Information Data Sheet and Ordering Information Programmer Object File (.pof), Raw Binary File
for more information. (.rbf), Serial Bitstream File (.sbf), Serial Vector
Format File (.svf), SRAM Object File (.sof), and
priority FastTrack interconnect A type of Tabular Text File (.ttf).
optimized high-speed interconnect used for
routing critical paths in a design. FLEX Chain Files, JTAG Chain Files,
Programmer Object Files, SRAM Object Files,
product term Two or more factors in a Boolean and JEDEC files are used to program or
expression combined with an AND operator configure devices with the MAX+PLUS II
constitute a product term, where “product” programmer. Test vectors for functional testing
means “logic product.” can be saved in POFs and JEDEC Files. All other
file formats are used to configure Mercury,
programmable interconnect array (PIA) The APEX II, APEX 20K, FLEX 10K, FLEX 8000,
portion of MAX 7000, MAX 3000A, or FLEX 6000, and ACEX 1K devices by other
MAX 5000 devices that routes signals between means. JTAG chain files are used to program or
different logic array blocks (LABs). configure one or more FLEX 10K, MAX 9000,
MAX 7000S, MAX 7000A, MAX 7000B,
programmable logic devices (PLDs) Digital, MAX 3000A devices in a multi-device JTAG
user-configurable integrated circuits used to chain. The Programmer can save data read from
implement custom logic functions. PLDs can an examined device in POF of JEDEC file
implement any Boolean expression or format.
registered function with built-in logic
structures.
Altera Corporation 13
QDR RAM interface standard. EEPROM-based Altera device from being
interrogated. This bit also prevents EPROM- or
quad flat pack (QFP) A device package offered EEPROM-based Altera memory bits from being
by Altera. Plastic QFP (PQFP), power QFP inadvertently reprogrammed. The security bit
(RQFP), and plastic thin QFP (TQFP) packages can be turned on or off for each device in a
are available. See the Altera Device Package project or for the entire project.
Information Data Sheet and Ordering Information
for more information. shared expanders and shareable expanders A
feature of the MAX 9000, MAX 7000,
quad-port RAM The Mercury embedded MAX 3000A, and MAX 5000 device architecture
system block (ESB) supports quad-port RAM that allows logic cells to use uncommitted
memory with four independent ports that can product terms within the same logic array block
operate at different frequencies and can (LAB). A product term that is eligible to be
concurrently access memory arrays to or from shared in this matter is called a shared
up to four ports. (See dual-port RAM for more expander. The MAX+PLUS II Compiler
information about parallel structure.) automatically allocates shareable expanders
when a project is compiled. A shared expander
Quartus II Altera design software that provides can be allocated with EXP primitive.
a comprehensive environment for system-on-a-
programmable-chip (SOPC) design. It supports SignalTap Altera’s logic analysis solution that
Mercury, APEX II, APEX, Excalibur, FLEX 10K, works with the Quartus II software. SignalTap
FLEX 10KE, FLEX 6000, and ACEX 1K PLDs. logic analysis reduces verification times by
allowing engineers to conduct device
verification via internal signal values. The
SignalTap solution consists of the SignalTap
R megafunction, a JTAG communication cable,
and the Quartus II waveform editor software.
RapidLAB interconnect A type of Mercury
interconnect that provides a high-speed small-outline integrated circuit (SOIC) A device
connection to a 10-logic-array-block (LAB)- package option offered by Altera. See the Altera
wide region. Device Package Information Data Sheet and
Ordering Information for more information.
register See flipflop.
SoftMode A technology that integrates C++/C
Report File (.rpt) An ASCII text file, generated compilers and debuggers into the Quartus II
by the Quartus and MAX+PLUS II Compiler’s design software environment to enable
fitter module, that shows how device resources designers to develop object code to run in
are used by the project. If a module preceding Excalibur embedded processor cores.
the Partitioner generates an error, this file is not
generated. If the Partitioner generates an error, SRAM Object File (.sof) A binary file generated
the Report File is generated (in most cases.) by the Quartus II and MAX+PLUS II Compilers;
assembler module that contains the data for
configuring Altera SRAM-based devices.
14 Altera Corporation
static random access memory (SRAM) A read- performance of a project. Because the timing is
write memory that stores data in integrated generated after logic synthesis, partitioning,
flipflops. Mercury, APEX II, APEX 20KE, and and fitting are performed, timing simulation
ACEX devices use SRAM bits to store allows only the nodes in a project that have not
configuration data. See the Configuration been removed by logic optimization to be
Elements Data Sheet for more information. simulated.
Altera Corporation 15
standard netlist file generated by the Verilog
Netlist Writer module of the Compiler. A
Verilog Output File contains functional and
timing information for simulation with the
standard Verilog HDL simulator.
16 Altera Corporation