PIC18F87K22 FAMILY

23.0 12-BIT ANALOG-TO-DIGITAL 23.1 Differential A/D Converter

CONVERTER (A/D) MODULE The converter in PIC18F87K22 family devices is
The Analog-to-Digital (A/D) Converter module in the implemented as a differential A/D where the differential
PIC18F87K22 family of devices has 16 inputs for the voltage between two channels is measured and
64-pin devices and 24 inputs for the 80-pin devices. converted to digital values (see Figure 23-1).
This module allows conversion of an analog input The converter can also be configured to measure a
signal to a corresponding 12-bit digital number. voltage from a single input by clearing the CHSN bits
The module has these registers: (ADCON1<2:0>). With this configuration, the negative
channel input is connected internally to AVSS (see
• A/D Control Register 0 (ADCON0) Figure 23-2).
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2) FIGURE 23-1: DIFFERENTIAL CHANNEL
• A/D Port Configuration Register 0 (ANCON0) MEASUREMENT
• A/D Port Configuration Register 1 (ANCON1)
• A/D Port Configuration Register 2 (ANCON2) Positive Input
CHS<4:0>
• ADRESH (the upper, A/D Results register) Negative Input ADC
• ADRESL (the lower, A/D Results register) CHSN<2:0>

The ADCON0 register, shown in Register 23-1, con-

trols the operation of the A/D module. The ADCON1
Differential conversion feeds the two input channels to
register, shown in Register 23-2, configures the voltage
a unity gain differential amplifier. The positive channel
reference and special trigger selection. The ADCON2
input is selected using the CHS bits (ADCON0<6:2>)
register, shown in Register 23-3, configures the A/D
and the negative channel input is selected using the
clock source and programmed acquisition time and
CHSN bits (ADCON1<2:0>).
justification.
The output from the amplifier is fed to the A/D Con-
verter, as shown in Figure 23-1. The 12-bit result is
available on the ADRESH and ADRESL registers. An
additional bit indicates if the 12-bit result is a positive or
negative value.

FIGURE 23-2: SINGLE CHANNEL

MEASUREMENT

Positive Input
CHS<4:0>
CHSN<2:0> = 000 ADC

In the Single Channel Measurement mode, the nega-

tive input is connected to AVSS by clearing the CHSN
bits (ADCON1<2:0>).

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23.2 A/D Registers
23.2.1 A/D CONTROL REGISTERS

REGISTER 23-1: ADCON0: A/D CONTROL REGISTER 0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-2 CHS<4:0>: Analog Channel Select bits
00000 = Channel 00 (AN0) 10000 = Channel 16 (AN16)
00001 = Channel 01 (AN1) 10001 = Channel 17 (AN17)
00010 = Channel 02 (AN2) 10010 = Channel 18 (AN18)
00011 = Channel 03 (AN3) 10011 = Channel 19 (AN19)
00100 = Channel 04 (AN4) 10100 = Channel 20 (AN20)(1,2)
00101 = Channel 05 (AN5) 10101 = Channel 21 (AN21)(1,2)
00110 = Channel 06 (AN6) 10110 = Channel 22 (AN22)(1,2)
00111 = Channel 07 (AN7) 10111 = Channel 23 (AN23)(1,2)
01000 = Channel 08 (AN8) 11000 = (Reserved)(2)
01001 = Channel 09 (AN9) 11001 = (Reserved)(2)
01010 = Channel 10 (AN10 11010 = (Reserved)(2)
01011 = Channel 11 (AN11) 11011 = (Reserved)(2)
01100 = Channel 12 (AN12)(1,2) 11100 = Channel 28 (Reserved CTMU)
01101 = Channel 13 (AN13)(1,2) 11101 = Channel 29 (Internal temperature diode)
01110 = Channel 14 (AN14)(1,2) 11110 = Channel 30 (VDDCORE)
01111 = Channel 15 (AN15)(1,2) 11111 = Channel 31 (v1.024V band gap)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D (or calibration) cycle in progress. Setting this bit starts an A/D conversion cycle. The bit is
cleared automatically by hardware when the A/D conversion is completed.
0 = A/D conversion has completed or is not in progress
bit 0 ADON: A/D On bit
1 = A/D Converter is operating
0 = A/D conversion module is shut off and consuming no operating current

Note 1: These channels are not implemented on 64-pin devices.

2: Performing a conversion on unimplemented channels will return random values.

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REGISTER 23-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 TRIGSEL<1:0>: Special Trigger Select bits

11 = Selects the special trigger from the RTCC
10 = Selects the special trigger from the Timer1
01 = Selects the special trigger from the CTMU
00 = Selects the special trigger from the ECCP2
bit 5-4 VCFG<1:0>: A/D VREF+ Configuration bits
11 = Internal VREF+ (4.096V)
10 = Internal VREF+ (2.048V)
01 = External VREF+
00 = AVDD
bit 3 VNCFG: A/D VREF- Configuration bit
1 = External VREF
0 = AVSS
bit 2-0 CHSN<2:0>: Analog Negative Channel Select bits
111 = Channel 07 (AN6)
110 = Channel 06 (AN5)
101 = Channel 05 (AN4)
100 = Channel 04 (AN3)
011 = Channel 03 (AN2)
010 = Channel 02 (AN1)
001 = Channel 01 (AN0)
000 = Channel 00 (AVSS)

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REGISTER 23-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

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23.2.2 A/D RESULT REGISTERS Figure 23-3 shows the operation of the A/D result justi-
fication and location of the extended sign bits
The ADRESH:ADRESL register pair is where the 12-bit
(ADSGN). The extended sign bits allow for easier
A/D result and extended sign bits (ADSGN) are loaded
16-bit math to be performed on the result. The results
at the completion of a conversion. This register pair is
are represented as a two's compliment binary value.
16 bits wide. The A/D module gives the flexibility of left
This means that when sign bits and magnitude bits are
or right justifying the 12-bit result in the 16-Bit Result
considered together in right justification, the ADRESH
register. The A/D Format Select bit (ADFM) controls
and ADRESL registers can be read as a single signed
this justification.
integer value.
When the A/D Converter is disabled, these 8-bit
registers can be used as two general purpose registers.

FIGURE 23-3: A/D RESULT JUSTIFICATION

12-Bit Result Right Justified

Left Justified
ADFM = 0 ADFM = 1

ADRESH ADRESL ADRESH ADRESL

Result bits ADSGN bit

Two’s Complement Example Results Number Line

Left Justified Right Justified

Hex Decimal Hex Decimal

0xFFF0 4095 0x0FFF 4095
0xFFE0 4094 0x0FFE 4094
… … … …
0x0020 2 0x0002 2
0x0010 1 0x0001 1
0x0000 0 0x0000 0
0xFFFF -1 0xFFFF -1
0xFFEF -2 0xFFFE -2
… … … …
0x001F -4095 0xF001 -4095
0x000F -4096 0xF000 -4096

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REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES11 ADRES10 ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<11:4>: A/D Result High Byte bits

REGISTER 23-5: ADRESL: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES3 ADRES2 ADRES1 ADRES0 ADSGN ADSGN ADSGN ADSGN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 ADRES<3:0>: A/D Result Low Byte bits

bit 3-0 ADSGN: A/D Result Sign bit
1 = A/D result is negative
0 = A/D result is positive

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REGISTER 23-6: ADRESH: A/D RESULT HIGH BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADSGN ADSGN ADSGN ADSGN ADRES11 ADRES10 ADRES9 ADRES8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 ADSGN: A/D Result Sign bit

1 = A/D result is negative
0 = A/D result is positive
bit 3-0 ADRESH<11:8>: A/D Result High Byte bits

REGISTER 23-7: ADRESL: A/D RESULT LOW BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<7:0>: A/D Result Low Byte bits

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The ANCONx registers are used to configure the As a rule, I/O pins that are multiplexed with analog
operation of the I/O pin associated with each analog inputs default to analog operation on any device Reset.
channel. Clearing an ANSELx bit configures the
corresponding pin (ANx) to operate as a digital only I/O.
Setting a bit configures the pin to operate as an analog
input for either the A/D Converter or the comparator
module, with all digital peripherals disabled and digital
inputs read as ‘0’.

REGISTER 23-8: ANCON0: A/D PORT CONFIGURATION REGISTER 0

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANSEL<7:0>: Analog Port Configuration bits (AN7 and AN0)
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port

REGISTER 23-9: ANCON1: A/D PORT CONFIGURATION REGISTER 1

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANSEL15(1) ANSEL14(1) ANSEL13(1) ANSEL12(1) ANSEL11 ANSEL10 ANSEL9 ANSEL8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANSEL<15:8>: Analog Port Configuration bits (AN15 through AN8)(1)
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port

Note 1: AN15 through AN12 and AN23 to AN20 are implemented only on 80-pin devices. For 64-pin devices, the
corresponding ANSELx bits are still implemented for these channels, but have no effect.

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REGISTER 23-10: ANCON2: A/D PORT CONFIGURATION REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANSEL23(1) ANSEL22(1) ANSEL21(1) ANSEL20(1) ANSEL19 ANSEL18 ANSEL17 ANSEL16
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANSEL<23:16>: Analog Port Configuration bits (AN23 through AN16)(1)
1 = Pin is configured as an analog channel; digital input is disabled and any inputs read as ‘0’
0 = Pin is configured as a digital port

Note 1: AN15 through AN12 and AN23 through AN20 are implemented only on 80-pin devices. For 64-pin
devices, the corresponding ANSELx bits are still implemented for these channels, but have no effect.

The analog reference voltage is software-selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS) or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins. VREF+ has
two additional Internal Reference Voltage selections:
2.048V and 4.096V.
The A/D Converter can uniquely operate while the
device is in Sleep mode. To operate in Sleep, the A/D
conversion clock must be derived from the A/D
Converter’s internal RC oscillator.
The output of the Sample-and-Hold (S/H) is the input
into the converter, which generates the result via
successive approximation.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and the A/D Interrupt Flag bit, ADIF (PIR1<6>),
is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The block diagram of the A/D module is shown in
Figure 23-4.

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FIGURE 23-4: A/D BLOCK DIAGRAM
CHS<4:0>

11111
1.024V Band Gap
11110
VDDCORE
11101 Reserved
Temperature Diode
11100
Reserved CTMU
11011
(Unimplemented)
11010
(Unimplemented)
11001
(Unimplemented)
11000
(Unimplemented)
10111
AN23(1)
12-Bit
A/D 10110
Converter AN22(1)

00100
AN4
00011
AN3
00010
AN2
00001
AN1
00000
AN0

Positive Input Voltage CHSN<2:0>

111
Negative Input Voltage AN6
110
AN5
Reference
Voltage
VCFG<1:0>

11 Internal VREF+ 001

(4.096V) AN0
VREF+ Internal VREF+ 000
10 AVSS
(2.048V)
01
AN3
VREF- VDD
00
VNCFG

AN2

VSS(2)

Note 1: Channels, AN15 through AN12, and AN20 through AN23, are not available on 64-pin devices.
2: I/O pins have diode protection to VDD and VSS.

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After the A/D module has been configured as desired, 2.
the selected channel must be acquired before the
conversion can start. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine acquisition time, see Section 23.3 “A/D
Acquisition Requirements”. After this acquisition 3.
time has elapsed, the A/D conversion can be started. 4.
An acquisition time can be programmed to occur
between setting the GO/DONE bit and the actual start 5.
of the conversion.
To do an A/D conversion, follow these steps:
1. Configure the A/D module:
• Configure the required ADC pins as analog
6.
pins (ANCON0, ANCON1 and ANCON2)
• Set the voltage reference (ADCON1)
7.
• Select the A/D positive and negative input
channels (ADCON0 and ADCON1)
• Select the A/D acquisition time (ADCON2)
• Select the A/D conversion clock (ADCON2)
• Turn on the A/D module (ADCON0)
Configure the A/D interrupt (if desired):
• Clear the ADIF bit (PIR1<6>)
• Set the ADIE bit (PIE1<6>)
• Set the GIE bit (INTCON<7>)
Wait the required acquisition time (if required).
Start the conversion:
• Set the GO/DONE bit (ADCON0<1>)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL)
and, if required, clear bit, ADIF.
For the next conversion, begin with Step 1 or 2,
as required.
The A/D conversion time per bit is defined as TAD.
Before the next acquisition starts, a minimum Wait
of 2 TAD is required.

FIGURE 23-5: ANALOG INPUT MODEL

VDD
Sampling
Switch
VT = 0.6V
ANx RIC 1k SS RSS
RS

VAIN CPIN ILEAKAGE

VT = 0.6V CHOLD = 25 pF
5 pF ±100 nA

VSS

Legend: CPIN = Input Capacitance

VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to VDD
various junctions
RIC = Interconnect Resistance
SS = Sampling Switch
CHOLD = Sample/Hold Capacitance (from DAC)
RSS = Sampling Switch Resistance 1 2 3 4
Sampling Switch (k)

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23.3 A/D Acquisition Requirements To calculate the minimum acquisition time,
Equation 23-1 can be used. This equation assumes
For the A/D Converter to meet its specified accuracy, that 1/2 LSb error is used (1,024 steps for the A/D). The
the Charge Holding (CHOLD) capacitor must be allowed 1/2 LSb error is the maximum error allowed for the A/D
to fully charge to the input channel voltage level. The to meet its specified resolution.
analog input model is shown in Figure 23-5. The
source impedance (RS) and the internal sampling Equation 23-3 shows the calculation of the minimum
switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is
required to charge the capacitor CHOLD. The sampling based on the following application system
switch (RSS) impedance varies over the device voltage assumptions:
(VDD). • CHOLD = 25 pF
The source impedance affects the offset voltage at the • Rs = 2.5 k
analog input (due to pin leakage current). The maxi- • Conversion Error  1/2 LSb
mum recommended impedance for analog sources • VDD = 3V  Rss = 2 k
is 2.5 k. After the analog input channel is selected or
• Temperature = 85C
changed, the channel must be sampled for at least the
minimum acquisition time before starting a conversion.
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.

EQUATION 23-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF

EQUATION 23-2: A/D MINIMUM CHARGING TIME

VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)

EQUATION 23-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ = TAMP + TC + TCOFF
TAMP = 0.2 s
TCOFF = (Temp – 25C)(0.02 s/C)
(85C – 25C)(0.02 s/C)
1.2 s
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s
-(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s
1.05 s
TACQ = 0.2 s + 1.05 s + 1.2 s
2.45 s

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23.4 Selecting and Configuring TABLE 23-1: TAD vs. DEVICE OPERATING
Automatic Acquisition Time FREQUENCIES
The ADCON2 register allows the user to select an AD Clock Source (TAD) Maximum
acquisition time that occurs each time the GO/DONE Device
Operation ADCS<2:0> Frequency
bit is set.
When the GO/DONE bit is set, sampling is stopped and 2 TOSC 000 2.50 MHz
a conversion begins. The user is responsible for ensur- 4 TOSC 100 5.00 MHz
ing the required acquisition time has passed between
8 TOSC 001 10.00 MHz
selecting the desired input channel and setting the
GO/DONE bit. 16 TOSC 101 20.00 MHz
This occurs when the ACQT<2:0> bits 32 TOSC 010 40.00 MHz
(ADCON2<5:3>) remain in their Reset state (‘000’), 64 TOSC 110 64.00 MHz
which is compatible with devices that do not offer RC(2) x11 1.00 MHz(1)
programmable acquisition times.
Note 1: The RC source has a typical TAD time of
If desired, the ACQTx bits can be set to select a pro- 4 s.
grammable acquisition time for the A/D module. When 2: For device frequencies above 1 MHz, the
the GO/DONE bit is set, the A/D module continues to device must be in Sleep mode for the
sample the input for the selected acquisition time, then entire conversion or the A/D accuracy may
automatically begins a conversion. Since the acquisi- be out of specification.
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit. 23.6 Configuring Analog Port Pins
In either case, when the conversion is completed, the The ANCON0, ANCON1, ANCON2, TRISA, TRISF,
GO/DONE bit is cleared, the ADIF flag is set and the TRISG and TRISH registers control the operation of the
A/D begins sampling the currently selected channel A/D port pins. The port pins needed as analog inputs
again. If an acquisition time is programmed, there is must have their corresponding TRISx bits set (input). If
nothing to indicate if the acquisition time has ended or the TRISx bit is cleared (output), the digital output level
if the conversion has begun. (VOH or VOL) will be converted.

23.5 Selecting the A/D Conversion The A/D operation is independent of the state of the
CHS<3:0> bits and the TRISx bits.
Clock
Note 1: When reading the PORT register, all pins
The A/D conversion time per bit is defined as TAD. The configured as analog input channels will
A/D conversion requires 14 TAD per 12-bit conversion. read as cleared (a low level). Pins config-
The source of the A/D conversion clock is ured as digital inputs will convert an
software-selectable. analog input. Analog levels on a digitally
The possible options for TAD are: configured input will be accurately
• 2 TOSC converted.
• 4 TOSC 2: Analog levels on any pin defined as a
• 8 TOSC digital input may cause the digital input
buffer to consume current out of the
• 16 TOSC
device’s specification limits.
• 32 TOSC
• 64 TOSC
• Using the internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than
the minimum TAD. (For more information, see
Parameter 130 in Table 31-29.)
Table 23-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.

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23.7 A/D Conversions ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
Figure 23-6 shows the operation of the A/D Converter value written to the ADRESH:ADRESL registers).
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started After the A/D conversion is completed or aborted, a
after the following instruction to allow entry into Sleep 2 TAD Wait is required before the next acquisition can
mode before the conversion begins. be started. After this Wait, acquisition on the selected
channel is automatically started.
Figure 23-7 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0> Note: The GO/DONE bit should NOT be set in
bits set to ‘010’ and a 4 TAD acquisition time selected. the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the

FIGURE 23-6: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO/DONE bit

Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 23-7: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TACQT Cycles TAD Cycles

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts
Time (Holding capacitor is disconnected)

Set GO/DONE bit

(Holding capacitor continues
acquiring input) Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.

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PIC18F87K22 FAMILY
23.8 Use of the Special Event Triggers
A/D conversion can be started by the Special Event
Trigger of any of these modules:
• ECCP2 – Requires CCP2M<3:0> bits
(CCP2CON<3:0>) set at ‘1011’
• CTMU – Requires the setting of the CTTRIG bit
(CTMUCONH<0>)
• Timer1
• RTCC
To start an A/D conversion:
• The A/D module must be enabled (ADON = 1)
• The appropriate analog input channel is selected
• The minimum acquisition period is set one of
these ways:
- Timing provided by the user
- Selection made of an appropriate TACQ time
With these conditions met, the trigger sets the
GO/DONE bit and the A/D acquisition starts.
If the A/D module is not enabled (ADON = 0), the
module ignores the Special Event Trigger.
Note: With an ECCP2 trigger, Timer1 or Timer 3
is cleared. The timers reset to automati-
cally repeat the A/D acquisition period
with minimal software overhead (moving
ADRESH:ADRESL to the desired loca-
tion). If the A/D module is not enabled, the
Special Event Trigger is ignored by the
module, but the timer’s counter resets.
DS30009960F-page 356
23.9 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined, in part, by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used.
After the power-managed mode is entered (either of the
power-managed Run modes), an A/D acquisition or
conversion may be started. Once an acquisition or con-
version is started, the device should continue to be
clocked by the same power-managed mode clock source
until the conversion has been completed. If desired, the
device may be placed into the corresponding
power-managed Idle mode during the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires that the A/D RC
clock be selected. If bits, ACQT<2:0>, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry into Sleep mode. The
IDLEN and SCS<1:0> bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
 2009-2018 Microchip Technology Inc.
 PIC18F87K22 FAMILY
TABLE 23-2: REGISTERS ASSOCIATED WITH A/D MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP
PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF
PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE
IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8
ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
PORTA RA7(2) RA6(2) RA5 RA4 RA3 RA2 RA1 RA0
TRISA TRISA7(2) TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —
PORTG — — RG5(3) RG4 RG3 RG2 RG1 RG0
TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0
TRISH(1) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0
PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: This register is not implemented on 64-pin devices.
2: These bits are available only in certain oscillator modes, when the FOSC2 Configuration bit = 0. If that
Configuration bit is cleared, this signal is not implemented.
3: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is
unimplemented.

 2009-2018 Microchip Technology Inc. DS30009960F-page 357