15 Reasons Cyient

Outshines Other
Semiconductor Design
Service Providers
 Contents

Executive Summary 01

Outsourced Services 01

Demonstrated Success 01

RTL to GDSII 02

SoC Verification 02

Design Verification 03

Physical Design 03

DFT 04

Analog Mixed Signal Design and 05

Verification

Custom IC Layout 05

Design Services 06

Project Scope That Meets Your 06

Needs

What to expect when working 07

with Cyient

References 07

15 Reasons Cyient Outshines 08

Other Semiconductor Design
Service Providers

Next Steps 08

About Cyient 09

2
 By choosing
an outsourced
Executive Summary Demonstrated Success
services provider,
semiconductor IC engineering teams at both fabless Cyient is an outsourced design services
companies and
IDMs can quickly semiconductor companies and integrated provider with over 350 semiconductor
get access to device manufacturers (IDMs) face the same engineers. It has helped a wide range of
engineers with business challenges of getting their next chip clients over the past 15 years, including
prior experience
to exactly the design to market on time, with the staff at tier-one semiconductor companies in North
new skills that hand, while working within the budget. Finding America, Europe, Taiwan, Japan and APAC.
they need, like In total Cyient has over 14,000 associates,
FinFET design,
out that your existing design and verification
AMS or Formal team is already stretched too thin, or that your located in 38 countries, serving industries
Verification, and engineers don’t have the right experience like Semiconductor, Transportation, Medical,
DFT techniques. Consumer, Energy, Oil & Gas, Aerospace
for the challenge creates a real dilemma to
success. Hiring and training new engineers will and Defense. The semiconductor teams at
simply take too long, so the option of adding Cyient are actively involved in leading-edge IP
a flexible workforce by using an outsourcing development using 10 nm and 14 nm Bulk/SOI
services provider becomes appealing to FinFET technology and collaborate closely with
consider. the fabs.

You will find a complete set of engineering

skills ranging from RTL design and verification
Outsourced Services through IC implementation, using each of the
major EDA tool flows (Synopsys, Cadence,
By choosing an outsourced service company,
Mentor Graphics). Since Cyient owns EDA
you can quickly get access to engineers with Licenses, your team doesn’t incur added costs
prior experience to exactly the new skills that to the services team.
you need, like FinFET design, AMS or formal
verification, and DFT techniques. These Modern SoCs can have hundreds of IP blocks,
engineers have already gone through the and Cyient will help you find just the right IP
learning curve, saving you valuable time and and VIP to meet your requirements, integrate
will complement your existing team for the the IP, and verify it in the context of the
duration of the project. complete system.
Perhaps your project looks like it will run over
budget or that the complexity has increased
to meet new market requirements. Adding an
outsourced team will help meet your budget,
and build your team to the proper size to meet
the market window of opportunity. Moving
from a 28 nm planar CMOS node to 16 nm
FinFET process requires about a 3X increase in
circuit simulation time due to process variation
effects1. So, it’s recommended to be prepared
with more computing and engineering
resources.

01
 RTL to GDSII
Examples of IC design services that included RTL creation, functional verification, logic synthesis,
formal analysis, floorplanning, place and route, DFT, timing closure, and GDSII output are listed in the
following table:

Project Type Business Need Results

802.11n Router
• 65 nm, 8M gates, 500MHz
HD Image Processor
• 90 nm, 6M gates, 237 MHz
• LVDS at 1 GHz
• Derivative SoC development
• 18% die reduction
• Timing closure with 13 modes
across 6 corners
• All engineering RTL to GDSII
• System-level verification
• Timing closure, DFT, physical
design
• First-pass silicon success
• 22.6% die reduction
• 70% manufacturing yield
• Cost savings with team across
US and India
• Design and verification of
complex DSNU, MJPEG, ARM
cache subsystem, SPI, DMA,
Gigabit Ethernet

SoC Verification
Design service projects in this category were focused on the logical verification process of a SoC to
create high coverage stimulus using a metric-driven verification methodology.

Project Type Business Need Results

Cache Coherent Interconnect
Subsystem IP
• 1 Manager, 10 Engineers
• 12-month project
AMS UVM Verification
• 3 Engineers
• 1-month project
ARM Cortex based SoC
• 12 Engineers
• 12-month project
• Mobile platform development
• OVM verification environment
• AMS verification environment
• Metric-driven verification
• Executable verification plan
• Mobile platform with Cortex-M3 • ARM DSM setup
• Low-power verification
• USB and PCIE integration
verification
• Integrated 4 OCP master OVCs,
4 AXI4ACE master OVCs,
1 AXI4 master OVC
• Integrated 5 OCP slave OVCs
and 1 AXI4 slave OVC
• UVM-SV based verification
environment
• Reusable I2C master UVC to
generate I2C transactions
• Environment components
developed with SystemVerilog
and OVM
• USB, PCIE VIP integration

02
 Design Verification
IP blocks and subsystems have been verified across a wide range of domains.

Project Type Business Need Results

Memory Subsystem • Functional verification of
• 8 Engineers cache coherent multiprotocol
• 10-month project interconnect IP
• Memory subsystem IP
verification
DDR-3 • Verify DDR3 PHY, DDR3
• 3 Engineers controller, RLD2/RLD3 PHY
• 6-month project • Augment verification team
Power Management IC • Develop verification
environment using Verilog
• Augment verification team
Ethernet • Verify Ethernet 100M/1G PHY
with Specman/E
• Functional coverage
• Used coverage-driven random
verification with UVM
• Verified AXI4.0, ACE, and OCP
3.0 protocols
• Regressions achieved 100%
pass rate
• Cost savings with team across
US and India
• Design and verification of
complex DSNU, MJPEG, ARM
cache subsystem, SPI, DMA,
Gigabit Ethernet
• Verification environment
created using Verilog
• Developed verification test plan
• Reached 100% regression pass,
100% code coverage
• Verification plan developed
• Wrote checkers using eRM
• Achieved functional coverage
goal

Physical Design
IC design is often divided between front-end and back-end work, and the following projects are in the
back-end where the physical layout is completed at the cell and transistor levels.

Project Type Business Need Results

Video Processor Chip
• 17 million placeable instances
Graphics Chip
• 9 Engineers
• 12-month project
• Implement a video processor
from netlist to GDSII
• Physical design and timing
closure
• Physical verification
• Physical design of 9 blocks
• Full-chip timing closure
• Physical verification
• Used Cadence SoC Encounter
for place and route, Conformal
for equivalence checking
• Mentor Graphics Calibre used
for physical verification
• Completed 9 blocks through
floor planning, place and route,
timing, IR drop analysis, physical
verification
• Timing met

03
 Project Type Business Need Results
Processor • Use libraries from TSMC and
• TSMC 65 nm Virage
• 11 M gates • Fault coverage of 97%
• 275 MHz

Handheld Device • Use libraries from ARM and

• TSMC 90 nm Virage
• 2 M gates • Achieve 99% fault coverage
• 100 MHz

DFT
Design For Test (DFT) is a design service on the front-end of design where the goal is to reach a high
fault coverage goal by using design techniques like scan chains and built-in test (BIST).

Project Type Business Need Results

Digital Video Processor • Cost savings • Used JTAG, scan insertion, and
• 3 Engineers • Time-to-market scan compression
• 4-month project • Lowered ATE test times
• Transition and stuck-at
fault test ATPG with Mentor
TestKompress
Multimedia Chip • Cost savings • Used memory BIST on 320
• 2 Engineers • Memory testing with repair memories with 66 controllers
• 6-month project features • Scan compression with Mentor
• JTAG standards, 1149.1 and TestKompress
1149.6
Mixed-Signal Chip • Cost savings • Hierarchical scan and test
• 4 Engineers • Memory test with repair compression used
• 5-month project features • Memory BIST used
• Analog IP testing • IEEE P1500 test architecture for
• Full-chip scan analog IP
• Tested SerDes, PLL, and DDR

04
 Analog Mixed Signal Design and Verification
Combining both digital and analog IP on a single device is another specialty service offered by Cyient as
shown in the following client examples.

Project Type Business Need Results

Analog Design • High efficiency • 96% max efficiency
• DC-DC Buck Converter • Programmable • Programmable using metal3
• PMIC mask option
Analog Design • Wide temperature range • Operation over -40 to 150C
• CAN PHY Transceiver • High ESD tolerance • ESD tolerance to +/- 20KV
• LVCS Transceiver • Japanese CAN standards • Designed with 0.35um
BCDMOS SOI
PMIC • AMS verification • Analog blocks modeled
• 4 Engineers • eRM environment • Full-chip transistor-level
• 6-month project simulation with NanoSim
• Digital simulations with VCS
and e

Custom IC Layout
Analog and digital IP can be created at the transistor-level to help your team achieve the exact
specifications required when off-the-shelf IP isn’t a good fit.

Project Type Business Need Results

IFPLL • Layout of analog blocks, custom • Layout of analog blocks: PFD, Regulators, VCO
• 2 Engineers digital blocks, and chip level • Layout of custom digital cells
• 6-month project • Use 32 nm SOI technology • Physical verification of blocks
• Chip-level integration and physical verification
SERDES • Layout of analog blocks and • IC layout of analog blocks: OpAmp, DAC, RX
• 4 Engineers custom digital blocks Rotator, TX rotator
• Use 32 nm SOI technology • Layout of custom digital blocks: standard cells,
level shifters
• Physical verification of blocks
Low-power RF • Cost savings • Layout of analog blocks: ADC, PLL, VGA, LDOs
chip • Layout of analog blocks and full • 6 GHz nets required shielding
• 2 Engineers chip • Full chip layout integration and physical
• 6-month project • Use of Cadence tools verification
• TSMC 65 nm LP technology
PMIC • Layout of analog blocks and • Layout of analog blocks: Clock generators,
• 12 Engineers custom digital blocks buck converter, battery charger
• Use of 180 nm DNWELL • Use of Cadence and Mentor tools for layout
process and physical verification
• Physical verification with EM
checks

05
 Design Services
There are three major service areas offered by
Cyient - semiconductor design, programmable
device design and system and software design.
As you can see through the project examples
above, Cyient has extensive experience
delivering services in every phase of the design
and implementation.
• Semiconductor Design
- RTL design and verification
- Logic synthesis and DFT
- Physical design and STA
- Library cell development and
characterization
- Mixed-signal design and verification
- Analog layout
- Post-silicon validation
- Yield enhancement
- Silicon bring-up
• Programmable Device Design
- High-density FPGA-based design
- Soft processor integration
- IP development and integration
- Reference design development
- Firmware development and integration
- RTL design, verification, and validation
- Turnkey designs
• System and Software Design
- OS enablement, porting
- Board support package (BSP)
- Device drivers – core, peripherals
- Audio, video and speech codecs
- Middleware, multimedia components
- 3rd party IP, application integration
- System integration and validation
- Benchmark, compliance testing
- Derivative product development
- Sustenance of platform software
06
Project Scope That Meets Your
Needs
For ASIC and SoC designs a typical design
flow includes multiple steps, and Cyient can
perform some or all of these steps. It really
depends on how you want your existing team
to be assisted in meeting the schedule. The
experienced teams from Cyient have delivered
over 300 ASIC tape-outs with a first-pass
silicon rate of greater than 95%, while meeting
schedule commitments over 95% of the time,
all while providing a 50% cost benefit to clients.
What makes Cyient unique among service
providers is that they provide an on-site
resource for your local team, and that person
manages all of the offshore resources for
you. The outsourced engineers are trained
on each of the EDA vendor tools, flows, and
methodologies, so they start producing quickly
Design Flow
Product Definition
and Design
RTL Design
Functional Verification Planning/Partitioning
Synthesis
DFT
Physical Design with
Timing Closure
Physical Verification
and Tape out
Productization and
Implementation
 Services - Ownership What to expect when working with
Cyient
Client/Cyient
Program management ensures that your team
and Cyient discuss the technical objectives,
identify the capabilities that you already
have, define the role that Cyient will provide,
Cyient

Cyient

Cyient

how to meet your project timeline, and how

team members will connect throughout the
design, verification and validation process. A
Net Cyient member from Cyient will available to be on-site
Cyient

list
with your team to coordinate with a program
DFT management role.
Net
list
Through daily communication, any issue is
quickly raised and dealt with, eliminating the
Cyient

Cyient

Cyient

possibility of any last-minute surprises. This

approach allows Cyient to modify their design
flow or EDA tool usage to meet your schedule
commitment.
Client/Manufacturing Partner

Employees at Cyient have a set of core values

that fit the acronym FIRST – Fairness, Integrity,
Respect, Sincerity, and Transparency. This is
part of their corporate culture, and it helps build
a winning relationship with your design team.
and without draining your EDA licenses, saving
you both time and expense. The result is a
Managers at Cyient are PMP certified, so
flexible business model that is created for
you’ll be able to follow the progress of this
each customer engagement to optimize how
outsourcing approach and know the schedule
services are delivered to meet their needs.
status. A Project Management Professional
(PMP®) credential means that you have a
Founded in 1991, Cyient is publicly traded
person with the experience, education and
on the NYSE as CYIENT. With the necessary
competency to lead and direct successful
corporate governance a public company
semiconductor design projects.
requires, financial transparency provides
much-needed peace of mind when selecting
an outsourcing partner. References

There are processes and procedures in place

1
Design Automation Conference 2015.
within Cyient to ensure that all of your IP and Moving from 28 nm to 16 nm. ARM,
design data are secure and protected. This Freescale, Broadcom, HiSilicon, TSMC,
lets you concentrate on getting to market, Cadence.
knowing that only your team has access to
proprietary information.

07
 15 Reasons Cyient Outshines Other
Semiconductor Design Service Providers
1. Global services provider with more than
14,000 associates in 38 countries, where
there are more than 350 experienced
semiconductor designers
2. Engineering expertise spanning concept
design engineering through manufacturing
including aftermarket services – they
can provide full product services beyond
semiconductor
3. 15 years of design expertise in every
semiconductor engineering design
discipline
4. Many Tier-1 semiconductor clients
5. Extensive resources include complete
design flows from RTL through GDSII using
all three major EDA vendors, helps control
your costs
6. Design verification specialists; analog
mixed-signal (AMS), embedded processor
(ARM), Interface IP, software – using the
latest verification methodologies (UVM,
SystemC and others)
7. Physical design experts who can minimize
die size, ensuring timing closure, achieving
power budget and ensure testability (DFT)
Next Steps
Now that you’ve learned a bit about how
outsourcing with Cyient can complement your
existing design team, please take the next step
and request a semiconductor design services
overview. During this meeting, we will provide
a detailed overview of our success working
with the top semiconductor companies and
understand the ways these experiences can be
applied to your business needs.
08
8. Semiconductor process experience
with the latest process geometries,
providing custom library migration
and characterization for each new
semiconductor node including FinFET
devices
9. Embedded software development for
popular platforms like ARM, MIPS
10. System level software development to
enable operation within Linux, Windows,
Android, MAC OS, iOS, etc.
11. Partnerships with semiconductor eco-
system companies to provide complete
turn-key semiconductor design and
development services
12. Alliances with IP and semiconductor foundry
partners
13. Extensive design expertise in virtually all of
the vertical markets that the semiconductor
industry serves
14. Turnkey services through trusted partners
eliminate the difficulty of dealing with
multiple vendors for packaging, assembly,
manufacturing, design, etc.
15. Circuit board design through manufacturing
and mass production addresses go-to-
market needs
If you have an immediate need, why not
request a semiconductor design project
assessment where we will work with you
to map your requirements with Cyient
services capabilities and staff. We will review
the methods we use to ensure project
communication flows fluidly between your
project team and the Cyient project resources.
 About Cyient
Cyient is a global provider of engineering, NAM Headquarters
manufacturing, data analytics, networks and Cyient, Inc.
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For more information about Cyient, T: +61 3 8605 4815
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© 2016 Cyient. Cyient believes the information in this publication is accurate as of its publication date; such information is subject to change
without notice. Cyient acknowledges the proprietary rights of the trademarks and product names of other companies mentioned in this document.

Updated June 2016

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