1 /**

2 * @file xmc_usic.c
3 * @date 2020-12-05
4 *
5 * @cond
6 *****************************************************************************
7 * XMClib v2.2.0 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015-2020, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Boost Software License - Version 1.0 - August 17th, 2003
13 *
14 * Permission is hereby granted, free of charge, to any person or organization
15 * obtaining a copy of the software and accompanying documentation covered by
16 * this license (the "Software") to use, reproduce, display, distribute,
17 * execute, and transmit the Software, and to prepare derivative works of the
18 * Software, and to permit third-parties to whom the Software is furnished to
19 * do so, all subject to the following:
20 *
21 * The copyright notices in the Software and this entire statement, including
22 * the above license grant, this restriction and the following disclaimer,
23 * must be included in all copies of the Software, in whole or in part, and
24 * all derivative works of the Software, unless such copies or derivative
25 * works are solely in the form of machine-executable object code generated by
26 * a source language processor.
27 *
28 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
29 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
30 * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
31 * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
32 * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
33 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
34 * DEALINGS IN THE SOFTWARE.
35 *
36 * To improve the quality of the software, users are encouraged to share
37 * modifications, enhancements or bug fixes with Infineon Technologies AG
38 * at XMCSupport@infineon.com.
39 *****************************************************************************
40 *
41 * Change History
42 * --------------
43 *
44 * 2015-02-20:
45 * - Initial draft <br>
46 * - Documentation improved <br>
47 *
48 * 2015-05-08:
49 * - Clearing bit fields PDIV, PCTQ, PPPEN in XMC_USIC_CH_SetBaudrate() API <br>
50 *
51 * 2015-06-20:
52 * - Removed version macros and declaration of GetDriverVersion API <br>
53 *
54 * 2015-08-27:
55 * - Added APIs for external input for BRG
configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG() <br>
56 *
57 * 2015-08-28:
58 * - Added asserts to XMC_USIC_CH_ConfigExternalInputSignalToBRG() <br>
59 *
60 * 2015-09-01:
61 * - Fixed warning in the asserts <br>
62 *
63 * 2018-09-29:
64 * - Added XMC_USIC_CH_SetBaudrateEx which uses the integer divider instead of
the fractional divider <br>
65 *
66 * 2019-03-30:
67 * - Changed XMC_USIC_Enable() adding polling to check clock ungate
68 *
69 * 2019-05-07:
70 * - Added XMC_USIC_CH_GetBaudrate(), XMC_USIC_CH_GetSCLKFrequency() and
XMC_USIC_CH_GetMCLKFrequency()
 71 *
72 * 2019-07-01:
73 * - XMC_USIC_CH_SetBaudrateEx() change type of input parameters
74 *
75 * 2019-09-25:
76 * - Fixed XMC_USIC_CH_SetBaudrate() which under certain circumtances, i.e. if
fPERI == baudrate * oversampling, delivers wrong calculations
77 *
78 * 2020-04-30:
79 * - Fixed XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit() and
XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(), avoid disabling the FIFO while the channel
is active.
80 * For new projects please use XMC_USIC_CH_TXFIFO_SetTriggerLimit() and
XMC_USIC_CH_RXFIFO_SetTriggerLimit()
81 *
82 * 2020-12-05:
83 * - Added XMC_USIC_CH_SetBaudrateDivider()
84 *
85 * @endcond
86 *
87 */
88
89 /*******************************************************************************
90 * HEADER FILES
91 *******************************************************************************/
92
93 #include "xmc_usic.h"
94 #include "xmc_scu.h"
95
96 #include <stdlib.h> /* abs */
97
98 /*******************************************************************************
99 * MACROS
100 *******************************************************************************/
101
102 #define USIC_CH_INPR_Msk (0x7UL)
103
104 /*******************************************************************************
105 * API IMPLEMENTATION
106 *******************************************************************************/
107
108 void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel)
109 {
110 XMC_ASSERT("XMC_USIC_CH_Enable: channel not valid", XMC_USIC_IsChannelValid(channel
));
111
112 if ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1))
113 {
114 XMC_USIC_Enable(XMC_USIC0);
115 }
116 #if defined(USIC1)
117 else if ((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1))
118 {
119 XMC_USIC_Enable(XMC_USIC1);
120 }
121 #endif
122 #if defined(USIC2)
123 else if ((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1))
124 {
125 XMC_USIC_Enable(XMC_USIC2);
126 }
127 #endif
128 else
129 {
130 XMC_ASSERT("USIC module not available", 0U/*Always*/);
131 }
132
133 /* USIC channel switched on*/
134 channel->KSCFG = (USIC_CH_KSCFG_MODEN_Msk | USIC_CH_KSCFG_BPMODEN_Msk);
135 while ((channel->KSCFG & USIC_CH_KSCFG_MODEN_Msk) == 0U)
136 {
137 /* Wait till the channel is enabled */
138 }
139
140 /* Set USIC channel in IDLE mode */
141 channel->CCR &= (uint32_t)~USIC_CH_CCR_MODE_Msk;
142 }
143
144 void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel)
145 {
146 channel->KSCFG = (uint32_t)((channel->KSCFG & (~USIC_CH_KSCFG_MODEN_Msk)) |
USIC_CH_KSCFG_BPMODEN_Msk);
147 }
148
149 XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t
rate, uint32_t oversampling)
150 {
151 XMC_USIC_CH_STATUS_t status;
152
153 uint32_t peripheral_clock;
154
155 uint32_t clock_divider;
156 uint32_t clock_divider_min;
157
158 uint32_t pdiv;
159 uint32_t pdiv_int;
160 uint32_t pdiv_int_min;
161
162 uint32_t pdiv_frac;
163 uint32_t pdiv_frac_min;
164
165 /* The rate and peripheral clock are divided by 100 to be able to use only 32bit
arithmetic */
166 if ((rate >= 100U) && (oversampling != 0U))
167 {
168 peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / 100U;
169 rate = rate / 100U;
170
171 clock_divider_min = 1024U;
172 pdiv_int_min = 1U;
173 pdiv_frac_min = 0x3ffU;
174
175 for (clock_divider = 1024U; clock_divider > 0U; --clock_divider)
176 {
177 pdiv = ((peripheral_clock * clock_divider) / (rate * oversampling));
178 pdiv_int = pdiv >> 10U;
179 pdiv_frac = pdiv & 0x3ffU;
180
181 if ((pdiv_int <= 1024U) && (pdiv_frac < pdiv_frac_min))
182 {
183 pdiv_frac_min = pdiv_frac;
184 pdiv_int_min = pdiv_int;
185 clock_divider_min = clock_divider;
186 }
187 }
188
189 channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL |
190 ((clock_divider_min - 1) << USIC_CH_FDR_STEP_Pos);
191
192 channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
193 USIC_CH_BRG_PDIV_Msk |
194 USIC_CH_BRG_PCTQ_Msk |
195 USIC_CH_BRG_PPPEN_Msk)) |
196 ((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) |
197 ((pdiv_int_min - 1U) << USIC_CH_BRG_PDIV_Pos);
198
199 status = XMC_USIC_CH_STATUS_OK;
200 }
201 else
202 {
203 status = XMC_USIC_CH_STATUS_ERROR;
204 }
205
206 return status;
207 }
208
209 XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrateEx(XMC_USIC_CH_t *const channel, int32_t
rate, int32_t oversampling)
210 {
211 int32_t peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
212 int32_t brg_clock = rate * oversampling;
213 int32_t actual_rate_upper;
214 int32_t actual_rate_lower;
215 uint32_t pdiv = 1;
216 uint32_t divider_step;
217 XMC_USIC_CH_STATUS_t status;
218
219 if (peripheral_clock > brg_clock)
220 {
221 divider_step = peripheral_clock / brg_clock; // integer division gets truncated
222 while (divider_step >= 1023)
223 {
224 pdiv++;
225 brg_clock = rate * oversampling * pdiv;
226 divider_step = peripheral_clock / brg_clock; // integer division gets truncated
227 }
228 actual_rate_upper = peripheral_clock / (divider_step * oversampling * pdiv);
229 actual_rate_lower = peripheral_clock / ((divider_step + 1) * oversampling * pdiv);
230
231 // choose better approximation if the peripheral frequency is not a multiple of
the baudrate
232 if (abs(rate - actual_rate_lower) < abs(rate - actual_rate_upper))
233 {
234 divider_step += 1;
235 }
236
237 divider_step = 1024 - divider_step;
238
239
240 channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL |
241 (divider_step << USIC_CH_FDR_STEP_Pos);
242
243 channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
244 USIC_CH_BRG_PDIV_Msk |
245 USIC_CH_BRG_PCTQ_Msk |
246 USIC_CH_BRG_PPPEN_Msk)) |
247 ((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) |
248 ((pdiv - 1) << USIC_CH_BRG_PDIV_Pos);
249
250 status = XMC_USIC_CH_STATUS_OK;
251 }
252 else
253 {
254 status = XMC_USIC_CH_STATUS_ERROR;
255 }
256
257 return status;
258 }
259
260 void XMC_USIC_CH_SetBaudrateDivider(XMC_USIC_CH_t *const channel,
261 XMC_USIC_CH_BRG_CLOCK_SOURCE_t clksel,
262 bool pppen,
263 uint32_t pdiv,
264 XMC_USIC_CH_BRG_CTQSEL_t ctqsel,
265 uint32_t pctq,
266 uint32_t dctq)
267 {
268 uint32_t regval = channel->BRG;
269 regval &= (uint32_t)~(USIC_CH_BRG_CLKSEL_Msk | USIC_CH_BRG_PPPEN_Msk |
USIC_CH_BRG_PDIV_Msk | USIC_CH_BRG_CTQSEL_Msk | USIC_CH_BRG_PCTQ_Msk |
USIC_CH_BRG_DCTQ_Msk);
270 regval |= clksel | (pppen ? USIC_CH_BRG_PPPEN_Msk : 0) | (pdiv <<
USIC_CH_BRG_PDIV_Pos) | ctqsel | (pctq << USIC_CH_BRG_PCTQ_Pos) | (dctq <<
USIC_CH_BRG_DCTQ_Pos);
271 channel->BRG = regval;
272 }
273
274 uint32_t XMC_USIC_CH_GetBaudrate(XMC_USIC_CH_t *const channel)
275 {
276 uint32_t divider;
277 if ((channel->BRG & USIC_CH_BRG_CTQSEL_Msk) == USIC_CH_BRG_CTQSEL_Msk)
278 {
279 // CTQSEL = 3
280 divider = 2;
281 }
282 else
283 {
284 // CTQSEL = 0, 1, or 2
285 divider = (channel->BRG & USIC_CH_BRG_PPPEN_Msk) ? 2 : 1;
286
287 if ((((channel->BRG & USIC_CH_BRG_CTQSEL_Msk) >> USIC_CH_BRG_CTQSEL_Pos) & 0x1) ==
0)
288 {
289 // CTQSEL = 0 or 2
290 divider *= ((channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos) + 1;
291 if ((((channel->BRG & USIC_CH_BRG_CTQSEL_Msk) >> USIC_CH_BRG_CTQSEL_Pos) & 0x2)
!= 0)
292 {
293 // CTQSEL = 2
294 divider *= 2;
295 }
296 }
297 }
298
299 divider *= ((channel->BRG & USIC_CH_BRG_PCTQ_Msk) >> USIC_CH_BRG_PCTQ_Pos) + 1;
300 divider *= ((channel->BRG & USIC_CH_BRG_DCTQ_Msk) >> USIC_CH_BRG_DCTQ_Pos) + 1;
301
302 uint32_t fperi = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
303 float baudrate;
304 if ((channel->FDR & USIC_CH_FDR_DM_Msk) ==
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL)
305 {
306 baudrate = fperi * (((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos
) / 1024.0F);
307 }
308 else
309 {
310 /* Normal divider mode */
311 baudrate = fperi * (1.0F / (1024 - ((channel->FDR & USIC_CH_FDR_STEP_Msk) >>
USIC_CH_FDR_STEP_Pos)));
312 }
313
314 baudrate /= divider;
315
316 return (uint32_t)baudrate;
317 }
318
319 uint32_t XMC_USIC_CH_GetSCLKFrequency(XMC_USIC_CH_t *const channel)
320 {
321 uint32_t divider;
322 divider = (channel->BRG & USIC_CH_BRG_PPPEN_Msk) ? 2 : 1;
323 divider *= ((channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos) + 1;
324 divider *= 2;
325
326 uint32_t fperi = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
327 float baudrate;
328 if ((channel->FDR & USIC_CH_FDR_DM_Msk) ==
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL)
329 {
330 /* Fractional divider mode */
331 baudrate = fperi * (((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos
) / 1024.0F);
332 }
333 else
334 {
335 /* Normal divider mode */
336 baudrate = fperi * (1.0F / (1024 - ((channel->FDR & USIC_CH_FDR_STEP_Msk) >>
USIC_CH_FDR_STEP_Pos)));
337 }
338
339 baudrate /= divider;
340
341 return (uint32_t)baudrate;
342 }
343
344 uint32_t XMC_USIC_CH_GetMCLKFrequency(XMC_USIC_CH_t *const channel)
345 {
346 uint32_t fperi = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
347
348 float baudrate;
349 if ((channel->FDR & USIC_CH_FDR_DM_Msk) ==
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL)
350 {
351 /* Fractional divider mode */
352 baudrate = fperi * (1.0F / (1024 - ((channel->FDR & USIC_CH_FDR_STEP_Msk) >>
USIC_CH_FDR_STEP_Pos)));
353 }
354 else
355 {
356 /* Normal divider mode */
357 baudrate = fperi / (((channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos
) / 1024.0F);
358 }
359
360 baudrate /= 2;
361
362 return (uint32_t)baudrate;
363 }
364
365
366 void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel,
367 const uint16_t pdiv,
368 const uint32_t oversampling,
369 const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)
370 {
371 XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Divider out of range", ((1U
< pdiv) || (pdiv < 1024U)));
372 XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Oversampling out of range",
((1U < oversampling) || (oversampling < 32U)));
373
374 /* Setting the external input frequency source through DX1 */
375 XMC_USIC_CH_SetBRGInputClockSource(channel, XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T);
376
377 /* Setting the trigger combination mode */
378 XMC_USIC_CH_SetInputTriggerCombinationMode(channel, XMC_USIC_CH_INPUT_DX1,
combination_mode);
379
380 /* Configuring the dividers and oversampling */
381 channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
382 USIC_CH_BRG_PDIV_Msk |
383 USIC_CH_BRG_PCTQ_Msk |
384 USIC_CH_BRG_PPPEN_Msk)) |
385 (((oversampling) - 1U) << USIC_CH_BRG_DCTQ_Pos) |
386 (((pdiv) - 1U) << USIC_CH_BRG_PDIV_Pos);
387 }
388
389 void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel,
390 const uint32_t data_pointer,
391 const XMC_USIC_CH_FIFO_SIZE_t size,
392 const uint32_t limit)
393 {
394 /* Disable FIFO */
395 channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk;
396
397 /* LOF = 0, A standard transmit buffer event occurs when the filling level equals
the limit value and gets
398 * lower due to transmission of a data word
399 * STBTEN = 0, the trigger of the standard transmit buffer event is based on the
transition of the fill level
400 * from equal to below the limit, not the fact being below
401 */
402 channel->TBCTR = (uint32_t)(channel->TBCTR & (uint32_t)~(USIC_CH_TBCTR_LIMIT_Msk |
403 USIC_CH_TBCTR_DPTR_Msk |
404 USIC_CH_TBCTR_SIZE_Msk)) |
405 (uint32_t)((limit << USIC_CH_TBCTR_LIMIT_Pos) |
406 (data_pointer << USIC_CH_TBCTR_DPTR_Pos) |
407 ((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos));
408 }
409
410
411 void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel,
412 const uint32_t data_pointer,
413 const XMC_USIC_CH_FIFO_SIZE_t size,
414 const uint32_t limit)
415 {
416 /* Disable FIFO */
417 channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk;
418
419 /* LOF = 1, A standard receive buffer event occurs when the filling level equals
the limit value and gets bigger
420 * due to the reception of a new data word
421 */
422 channel->RBCTR = (uint32_t)((channel->RBCTR & (uint32_t)~(USIC_CH_RBCTR_LIMIT_Msk |
423 USIC_CH_RBCTR_DPTR_Msk |
424 USIC_CH_RBCTR_LOF_Msk)) |
425 ((limit << USIC_CH_RBCTR_LIMIT_Pos) |
426 (data_pointer << USIC_CH_RBCTR_DPTR_Pos) |
427 ((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos) |
428 (uint32_t)USIC_CH_RBCTR_LOF_Msk));
429 }
430
431 void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
432 const XMC_USIC_CH_FIFO_SIZE_t size,
433 const uint32_t limit)
434 {
435 XMC_UNUSED_ARG(size);
436
437 /* STBTEN = 0, the trigger of the standard transmit buffer event is based on the
transition of the fill level
438 * from equal to below the limit, not the fact being below
439 */
440 channel->TBCTR = (uint32_t)((uint32_t)(channel->TBCTR & (uint32_t)~
USIC_CH_TBCTR_LIMIT_Msk) |
441 (limit << USIC_CH_TBCTR_LIMIT_Pos));
442 }
443
444 void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
445 const XMC_USIC_CH_FIFO_SIZE_t size,
446 const uint32_t limit)
447 {
448 XMC_UNUSED_ARG(size);
449
450 channel->RBCTR = (uint32_t)((uint32_t)(channel->RBCTR & (uint32_t)~
USIC_CH_RBCTR_LIMIT_Msk) |
451 (limit << USIC_CH_RBCTR_LIMIT_Pos));
452 }
453
454 void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
455 const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
456 const uint32_t service_request)
457 {
458 channel->INPR = (uint32_t)((channel->INPR & (~(uint32_t)(USIC_CH_INPR_Msk << (
uint32_t)interrupt_node))) |
459 (service_request << (uint32_t)interrupt_node));
460 }
461
462 void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
463 const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
464 const uint32_t service_request)
465 {
466 channel->TBCTR = (uint32_t)((channel->TBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (
uint32_t)interrupt_node))) |
467 (service_request << (uint32_t)interrupt_node));
468 }
469
470 void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
471 const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
472 const uint32_t service_request)
473 {
474 channel->RBCTR = (uint32_t)((channel->RBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (
uint32_t)interrupt_node))) |
475 (service_request << (uint32_t)interrupt_node));
476 }
477
478 void XMC_USIC_Enable(XMC_USIC_t *const usic)
479 {
480 if (usic == USIC0)
481 {
482 #if defined(CLOCK_GATING_SUPPORTED)
483 XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0);
484 while (XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_USIC0));
485 #endif
486 #if defined(PERIPHERAL_RESET_SUPPORTED)
487 XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0);
488 while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_USIC0));
489 #endif
490 }
491 #if defined(USIC1)
492 else if (usic == USIC1)
493 {
494 #if defined(CLOCK_GATING_SUPPORTED)
495 XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1);
496 while (XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_USIC1));
497 #endif
498 #if defined(PERIPHERAL_RESET_SUPPORTED)
499 XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1);
500 while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_USIC1));
501 #endif
502 }
503 #endif
504 #if defined(USIC2)
505 else if (usic == USIC2)
506 {
507 #if defined(CLOCK_GATING_SUPPORTED)
508 XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2);
509 while (XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_USIC2));
510 #endif
511 #if defined(PERIPHERAL_RESET_SUPPORTED)
512 XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2);
513 while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_USIC2));
514 #endif
515 }
516 #endif
517 else
518 {
519 XMC_ASSERT("USIC module not available", 0/*Always*/);
520 }
521 }
522
523 void XMC_USIC_Disable(XMC_USIC_t *const usic)
524 {
525 if (usic == (XMC_USIC_t *)USIC0)
526 {
527 #if defined(PERIPHERAL_RESET_SUPPORTED)
528 XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0);
529 #endif
530 #if defined(CLOCK_GATING_SUPPORTED)
531 XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0);
532 #endif
533 }
534 #if defined(USIC1)
535 else if (usic == (XMC_USIC_t *)USIC1)
536 {
537 #if defined(PERIPHERAL_RESET_SUPPORTED)
538 XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1);
539 #endif
540 #if defined(CLOCK_GATING_SUPPORTED)
541 XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1);
542 #endif
543 }
544 #endif
545 #if defined(USIC2)
546 else if (usic == (XMC_USIC_t *)USIC2)
547 {
548 #if defined(PERIPHERAL_RESET_SUPPORTED)
549 XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2);
550 #endif
551 #if defined(CLOCK_GATING_SUPPORTED)
552 XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2);
553 #endif
554 }
555 #endif
556 else
557 {
558 XMC_ASSERT("USIC module not available", 0/*Always*/);
559 }
560
561 }
562