EXPERIMENT NO.

10

Study of Shift Register (74HC194/74LS95)

Title: Study of Shift Register (74HC194/74LS95)

Objectives:

1) Design and implement pulse train generator using IC74HC194 for pulse
111001 (Use right shift)
2) Design and implement pulse train generator using IC74HC194 for pulse
111001 (Use left shift)
3) Design and implement 4-bit Ring counter using shift register
IC74HC194/IC74LS95.
4) Design and implement 4-bit Twisted ring-counter using shift register
IC74HC194/ IC74LS95

Aim: Design and implement of pulse train genitor and 4-bit Ring Counter/ Twisted ring
Counter using IC74HC194.

Hardware: Digital IC trainer kit, patch cords, power supply, IC’s- 74LS194/74HC95

Theory:

Shift Register:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right.

IC 74LS194:
 The 74LS194 are high-speed devices Shift-left and shift-right capability,
synchronous parallel and serial data transfer.
 It has serial/parallel data input and output capability which means that it can
function as serial-in serial-out, serial in parallel-out, parallel in serial out and
parallel in parallel out shift register.
Pin diagram of Universal Shift Register IC74194

Part A: Functional table verification of shift register IC74194:

A register may operate in any of the modes, like SISO, SIPO, PISO or bidirectional.
IC74194 is a 4bit universal shift register. IC74194 has a four parallel data inputs (D0-D3)
and S0 & S1 are control inputs.

Function Table for IC74194

Operation Inputs Outputs

Mode CP MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3
Reset(clear) X 0 X X X X X 0 0 0 0
Shift Left 1 1 0 X 0 X Q1 Q2 Q3 0
1 1 0 X 1 X Q1 Q2 Q3 1
Shift Right 1 0 1 0 X X 0 Q0 Q1 Q2
1 0 1 1 X X 1 Q0 Q1 Q2
Parallel load 1 1 1 X X Dn D0 D1 D2 D3
Hold X 1 0 0 X X X Q0 Q1 Q2 Q3
Operation-

Parallel Loading- Parallel loading is also accomplished synchronously with Low-to

High clock transitions by applying four bits of data and then driving the mode control
input S1&S0 to logic High state.

Data are loaded into corresponding flip-flops and appear at the outputs with Low-
High clock transition. Serial data flow is inhibited (disabled) during parallel loading.

Serial Shift Right Operation- Shift right operation is accomplished by setting S1-S0=01
and serial data is entered at the shift right serial input DSR, parallel data flow is
inhibited(disabled) during serial shift operation.

Hence D0,D1,D2,D3 inputs become ‘don’t care’, Mode control=1, FF-A is now serial
input, clock is applied to input, Q0 is connected to D1, Q1 to D2 and Q2 to D3 and serial
data is applied at input D0. Data is serially transferred from Q0 to Q1 ,Q1 to Q2 and Q2 to
Q3.

Serial Shift Left Operation- Shift left operation is accomplished by setting SISO=10
and serial data is entered at the shift left serial input DSL, parallel data flow is
inhibited(disabled) during serial shift operation. Hence D0,D1,D2,D3 inputs become ‘don’t
care’. Mode control is applied to 1. FF-D is now serial input. Clock is applied to clock
input. Q3 is connected to D2, Q2 to D1 and Q1 to D0 and serial data is applied to input D3.

Part B: Design and implement pulse train generator using IC74HC194 (Use
right shift)

Design a pulse train generator using universal shift register for following pulse train
111001 use right shift operation.

From the length of sequence determine the number of flip flops as-

L≤2 − 1, where L=Length of the sequence

N=Number of flip-flops

The length of sequence L=6

L≤2 = 2 ≤ 7

N=3

Thus 3 flip flops are required for following sequence.

 State Table-

Here shift right operation is used. So, write sequence under Q0 (MSB) column, and
perform shift operation

Outputs
Clock Decimal
Y=DSR
pulse Equivalent
Q0 Q1 Q2
1 1 1 0 1 6
2 1 1 1 1 7
3 1 1 1 0 7
4 0 1 1 0 3
5 0 0 1 1 1
6 1 0 0 1 4
As in the above state table 7 repeats at 2 and 3rd clock
nd
pulse, so 3 flip-flops are not
sufficient. Hence, 4 flip flops are required.

Outputs
Clock Decimal
Y=DSR
pulse Equivalent
Q0 Q1 Q2 Q3
1 1 1 0 0 1 12
2 1 1 1 0 1 14
3 1 1 1 1 0 15
4 0 1 1 1 0 07
5 0 0 1 1 1 03
6 1 0 0 1 1 09

 Design a combinational circuit from given state by K-map.

Q2Q3
Q0Q1 00 01 10
0 X X 1 X
0
X X 0 X
0
1 1 X 0 1

1 X 1 X X
Y=Q2+Q1+Q3

 Connection diagram for given sequence using IC74194

 Procedure:
1. Connect Vcc and ground pins.
2. Connect MR=1,S1=1 and S0=1
DSL=0, DSR=0. It will perform parallel load operation.
3. Apply D0D1D2D3 =1100 as it is first count in the sequence
4. Apply clock pulse we get Q0Q1Q2Q3=1100.
5. Connect combinational circuit as shown in circuit diagram. The output of
combinational circuit is connected to DSR pin as shown in fig(right shift
operation)
6. Connect MR=1, S1=0, S0=1, DSL=0. It will make shift Register in Right Shift
mode.
Connect D0, D1, D2 and D3 pins to ground.
7. Apply the clock pulse and observe the sequence as per truth table.
Part C: Design and implement pulse train generator using IC74HC194 (Use
left shift)

Design a pulse train generator using universal shift register for following pulse train
111001 use left shift operation.

From the length of sequence determine the number of flip flops as-

L≤2 − 1, where L=Length of the sequence

N=Number of flip-flops

The length of sequence L=6

L≤2 = 2 ≤ 7

N=3

Thus 3 flip flops are required for following sequence.

State Table-

Here shift left operation is used. So, write sequence under Q2 (LSB) column, and perform
shift operation

Outputs
Clock Decimal
Y=DSL
pulse Equivalent
Q0 Q1 Q2
1 0 1 1 1 3
2 1 1 1 1 7
3 1 1 1 0 7
4 1 1 0 0 6
5 1 0 0 1 4
6 0 0 1 1 1

As in the above state table 7 repeats at 2nd and 3rd clock pulse, so 3 flip-flops are not
sufficient. Hence, 4 flip flops are required.

Outputs
Clock Decimal
Y=DSL
pulse Equivalent
Q0 Q1 Q2 Q3
1 0 0 1 1 1 3
2 0 1 1 1 1 7
3 1 1 1 1 0 15
 4 1 1 1 0 0 14
5 1 1 0 0 1 12
6 1 0 0 1 1 09

 Design a combinational circuit from given state by K-map.

Q2 Q3
00 01 10
0 X X 1 X
0
X X 1 X
0
1
1 X 0 0

1 X 1 X X

Y=Q2+Q0

 Connection diagram for given sequence using IC74194

 Procedure:
1. Connect Vcc and ground pins.
2. Connect MR=1,S1=1 and S0=1
DSL=0,DSR=0. It will perform parallel load operation.
3. Apply D0D1D2D3 =0011 as it is first count in the sequence
4. Apply clock pulse we get Q0Q1Q2Q3=0011.
5. Connect combinational circuit as shown in circuit diagram. The output of
combinational circuit is connected to DSL pin as shown in fig(right shift
operation)
6. Connect MR=1, S1=1,S0=0, DSR=0. It will make shift Register in left Shift
mode.
Connect D0, D1, D2 and D3 pins to ground.
7. Apply the clock pulse and observe the sequence as per truth table .

Part D: Design and implement 4-bit Ring Counter using IC74HC194.

Ring counter:

Ring counter is a basic register with direct feedback such that the contents of the register
simply circulate around the register when the clock is running. Here the last output that is
Q3 in a shift register is connected back to the serial input (DSR).
 Truth Table
Clock Pulses Q0 Q1 Q2 Q3
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
7 0 0 1 0
8 0 0 0 1

 Procedure
1. Connect Vcc and ground pins.
2. Connect MR=1,S1=1 and S0=1
DSL=0, DSR=0. It will perform parallel load operation.
3. Apply D0D1D2D3 =1000 as it is first count in the sequence
4. Apply clock pulse we get Q0Q1Q2Q3=1000.
5. Connect combinational circuit as shown in circuit diagram. The output of
combinational circuit is connected to DSR pin as shown in fig.(right shift
operation)
6. Connect MR=1, S1=0,S0=1, DSL=0. It will make Shift Register in Right Shift
Mode.
Connect D0, D1, D2 and D3 pins to ground.
7. Apply the clock pulse and observe the sequence as per truth table.

Part E: Design and implement 4-bit Twisted Ring Counter using IC74HC194.

Twisted Ring counter:

A basic ring counter can be slightly modified to produce another type of shift register
counter called Johnson counter. Here complement of last output is connected back to the
not gate input and not gate output is connected back to serial input (Q3 to DSR). A four
bit Johnson counter gives 8 state output.
 Truth Table
Clock Pulses Q0 Q1 Q2 Q3
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0

 Procedure
1. Connect Vcc and ground pins.
2. Connect MR=1,S1=1 and S0=1
DSL=0, DSR=0. It will perform parallel load operation.
3. Apply D0D1D2D3 =1000 as it is first count in the sequence
4. Apply clock pulse we get Q0Q1Q2Q3=1000.
5. Connect combinational circuit as shown in circuit diagram. The output of
combinational circuit is connected to DSR pin as shown in fig.
 6. Connect MR=1, S1=0, S0=1, DSL=0. It will make Shift Register in Right
Shift Mode. Connect D0, D1, D2 and D3 pins to ground.
7. Apply the clock pulse and observe the sequence as per truth table.

Conclusion: IC 74 LS194 is used as comparator shift register and we have designed

pulse train generator and 4-bit Ring Counter, Twisted ring Counter using IC-
74HC194/IC74LS95

Upon completion of experiment students will be able to:

1. Define and explain shift register

2. Design and implement pulse train generator using IC74HC194 for pulse
111001 (Use right shift)
3. Design and implement pulse train generator using IC74HC194 for pulse
111001 (Use left shift)
4. Design and implement 4-bit Ring counter using shift register
IC74HC194/IC74LS95.
5. Design and implement 4-bit Twisted ring-counter using shift register
IC74HC194/ IC74LS95

Oral Question Bank

Q. No Description

On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On

1 the sixth clock pulse, the sequence is ________.

The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit
2 parallel out shift register that is initially clear. What are the Q outputs after
two clock pulses?

What is a shift register that will accept a parallel input, or a bidirectional

3
serial load and internal shift features, called?
4 How can parallel data be taken out of a shift register simultaneously?
What is meant by parallel load of a shift register?
5
What does the output enable do on the 74395A chip?
6
To operate correctly, starting a ring shift counter requires:
7
A modulus-12 ring counter requires a minimum of ________.
8
Stepper motors have become popular in digital automation systems because ________.
9
 How is a strobe signal used when serially loading a shift register?
10