Question Answers CS501:

Short Questions

1. Explain the significance of the "instruction fetch" stage in a pipelined processor.

Answer: The instruction fetch stage is crucial as it retrieves the next instruction to be
executed from the memory. This stage initiates the processing of an instruction by
loading the instruction bits into a temporary pipeline register, ensuring the smooth flow
of instructions through the subsequent stages of the pipeline.

2. What complications can arise from pipelining and how can they be resolved?

Answer: Complications in pipelining include data dependence, branch delay, and load
delay. These can be resolved using methods such as pipeline stalls, data forwarding, and
introducing nop instructions to handle branches and ensure proper operand availability.

3. Define the term "throughput" in the context of pipelining.

Answer: Throughput refers to the number of instructions processed per second by the
pipeline. It is enhanced by pipelining as multiple instructions can be processed
simultaneously, increasing the overall number of operations performed per unit time.

4. Describe the function of the "data forwarding" technique in resolving data

dependence.

Answer: Data forwarding is a hardware technique used to resolve data dependence by

allowing the output of one pipeline stage to be directly used as input for another stage
without waiting for the completion of the previous instruction. This helps in reducing
pipeline stalls and maintaining efficient instruction flow.

5. Why is it important to have separate data and instruction memories in a pipelined

design?

Answer: Separate data and instruction memories prevent conflicts between data access
and instruction fetch operations. This separation allows for concurrent fetching of
instructions and reading/writing of data, thereby improving the efficiency and speed of
the pipeline.

6. What role do control signals play in a pipelined processor?

Answer: Control signals regulate and direct the flow of data and instructions through the
various stages of the pipeline. They ensure that each stage performs its intended operation
at the right time, maintaining the correct sequence and coordination of processing steps.

7. How does a "branch delay" affect the performance of a pipelined processor?

 Answer: A branch delay occurs when the pipeline must wait to determine whether a
branch will be taken or not. This delay can disrupt the flow of subsequent instructions,
leading to pipeline stalls and reduced performance. Proper handling of branches, such as
through prediction or stalls, is necessary to mitigate this issue.

8. Explain the concept of "pipeline stalls" and when they are used.

Answer: Pipeline stalls are deliberate delays introduced into the pipeline to handle
situations where instructions cannot proceed due to data dependencies or other hazards.
Stalls temporarily halt the progress of instructions to ensure that dependent instructions
have the necessary data available before continuing.

Lecture 17:

Short Questions and Answers

1. What are the essential features of a reset instruction?

o Answer: The essential features of a reset instruction include clearing the control
step counter and reloading the PC to a predefined value. This initializes the
processor state to a known value, which helps in debugging and system
initialization.
2. Describe the indirect approach for PC initialization during a reset operation.
o Answer: In the indirect approach, the PC is initialized with the address where the
address of the startup routine is located. The reset instruction loads the PC with
the address of a jump instruction, and this jump instruction contains the address of
the required routine.
3. What is a machine exception and what are its types?
o Answer: A machine exception is an event that interrupts the normal flow of
execution of instructions in a processor. Types of exceptions include program
exceptions, hardware exceptions, trace and debugging exceptions, nonmaskable
exceptions, and interrupts (external exceptions).
4. Explain the concept of pipelining in processors.
o Answer: Pipelining is a technique that overlaps multiple instruction executions in
time, allowing a new instruction to be issued before the previous one completes.
This increases the number of operations performed per unit time and enhances the
efficient use of functional units in the processor, leading to higher throughput.
5. What is data dependence in pipelining and how is it resolved?
o Answer: Data dependence occurs when an instruction in one stage of the pipeline
uses the result of an instruction in a previous stage. It is resolved using pipeline
stalls, which delay subsequent instructions until the dependent instruction
completes, or data forwarding, which allows data to be passed directly between
stages to avoid delays.
6. What are the different types of resets in the SRC, and what do they initialize?
o Answer: In the SRC, there are two types of resets: Hard Reset and Soft Reset.
Hard Reset initializes the PC and the general registers, while Soft Reset only
initializes the PC.
 7. Describe the process of saving the processor state during exception processing.
o Answer: During exception processing, the processor state, which includes the
current value of the PC, general purpose registers, condition vector, and external
flags, must be saved before jumping to the exception handler routine. This ensures
that the processor can resume normal operation after the exception is handled.
8. What is a nonmaskable exception and give an example?
o Answer: A nonmaskable exception is a high-priority exception reserved for
critical events that cannot be suppressed by the processor. An example is a power
loss, where the processor might save the system state or alert an alternate power
supply.
9. How does a 3-bus SRC architecture enhance instruction execution?
o Answer: The 3-bus SRC architecture enhances instruction execution by allowing
simultaneous read and write operations. With two read ports and one write port,
special purpose and general purpose registers can perform parallel data transfers,
improving overall execution efficiency.
10. Why are separate data and instruction memories preferred in pipelined processors?
o Answer: Separate data and instruction memories are preferred in pipelined
processors to allow simultaneous fetching of instructions and accessing of data,
which minimizes memory access delays and enhances the efficiency of the
pipeline.

Lecture 16: Control Signals Generation and Control Unit

Control Signals for the Store Instruction

1. What are the differences between the store and load instruction time steps?
o The differences between the store and load instruction time steps are in T6 and T7. In
the store instruction, the data from the source register is written to memory in T6 and
T7, whereas in the load instruction, the data from memory is loaded into the destination
register during these steps.

Control Signals for the Branch and Branch Link Instructions

2. Which control signal is issued to enable the write for the program counter if the
condition is met?
o The control signal issued to enable the write for the program counter if the condition is
met is LPC (Load Program Counter).

3. In the branch link instruction, which step is added compared to the simple
conditional branch instruction?
o The step added in the branch link instruction compared to the simple conditional branch
instruction is T5. This step is used to save the current program counter value to the link
register before branching.
Control Signals for the Shift Right Instruction

4. What control signal is activated for the shift right 'shr' instruction?
o The control signal activated for the shift right 'shr' instruction is SHR.

The Control Unit Design

5. What are the primary approaches to design a control unit?

o The primary approaches to design a control unit are Hardwired and Micro-programmed
control units.

6. What input is not used by the control unit?

o The input not used by the control unit is User input signals. The control unit primarily
uses inputs from the timing step generator, the op-code from the decoder, and data
path generated signals.

Hardwired Implementation of the Control Unit

7. Which equation represents the control signal PCout?

o The equation that represents the control signal PCout is: PCout=T0+T3.
(OP20+OP22)+T4.(OP16+OP17+OP18+OP19)PCout = T0 + T3.(OP20+OP22) + T4.
(OP16+OP17+OP18+OP19)PCout=T0+T3.(OP20+OP22)+T4.(OP16+OP17+OP18+OP19)

8. Which equation represents the control signal LPC?

o The equation that represents the control signal LPC is: LPC=T1+T5.OP20+T6.CON.
(OP16+OP17+OP18+OP19)LPC = T1 + T5.OP20 + T6.CON.
(OP16+OP17+OP18+OP19)LPC=T1+T5.OP20+T6.CON.(OP16+OP17+OP18+OP19)

2-Bus Implementation of the SRC Data Path

9. What are the buses named in the 2-bus implementation of the SRC?
o The buses in the 2-bus implementation of the SRC are named the In bus and the Out
bus.

10. Which step is not part of the instruction fetch phase?

o The step that is not part of the instruction fetch phase is T4. The instruction fetch phase
typically involves T0, T1, and T2.

Lecture 15:
Logic Design for the Uni-bus SRC

1. What is the role of the control unit in the SRC?

o The control unit ensures the proper and synchronized functioning of the data path
components, enabling the CPU to execute instructions correctly.
 2. What does the PCout signal do during the fetch operation?
o The PCout signal allows the contents of the Program Counter register to be written onto
the internal processor bus.

3. How does the LMAR signal function in the SRC?

o The LMAR signal enables writing onto the memory address register (MAR), allowing the
value of the Program Counter on the bus to be copied into the MAR.

Control Signals for the Fetch Operation

4. Which control signals are applied during time step T1 of the instruction fetch
phase?
o During T1, the control signals LMBR, MRead, MARout, Cout, and LPC are applied to
transfer data from memory to the MBR and update the Program Counter.

5. What happens during time step T2 of the instruction fetch phase?

o During T2, the control signals MBRout and LIR are issued to transfer the instruction from
the MBR to the Instruction Register (IR).

Memory Address Register (MAR) and Memory Buffer Register (MBR) Circuitry

6. What is the purpose of the Memory Address Register (MAR) in the SRC?
o The MAR provides temporary storage for the address of the memory location to be
accessed and interfaces with the internal CPU bus and external address bus.

7. Describe the function of the Memory Buffer Register (MBR).

o The MBR holds the value read from memory or I/O devices and can load data from both
the internal CPU bus and the external CPU data bus, also driving these buses as needed.

Control Signals for the Add Instruction

8. What is the sequence of control signals for executing the add instruction?
o For the add instruction, during T3, the signals RBE, R2BUS, and LA are applied to transfer
the contents of register rb to the internal CPU bus and register A. During T4, the signals
RCE, R2BUS, ADD, and LC are used to transfer the contents of register rc to the bus,
perform the addition in the ALU, and store the result in register C. During T5, the signals
Cout, RAE, and BUS2R are activated to write the result to the destination register ra.

9. What is the role of the R2BUS signal in the add instruction?

o The R2BUS signal enables the contents of the specified register to be written onto the
internal CPU bus, allowing it to be used as an operand in the ALU.

Sign Extension

10. How is sign extension handled in the SRC?

 o Sign extension is handled by copying the most significant bit of a smaller bit-width value
to all the additional bits in the destination register, ensuring that values are correctly
represented in the 32-bit format of the SRC.

Lecture14:

Short Answer Questions

1. What is the op-code for the unconditional jump instruction?

o The op-code for the unconditional jump instruction is 20.
2. What is the range for the 8-bit constant c2 used in jump instructions?
o The range for the 8-bit constant c2 is -128 to 127.
3. List the possible formats for the jump instruction in the FALCON-A assembler.
o The possible formats are: jump [ra + constant], jump [ra + variable],
jump [ra + address], jump [ra + label].
4. In the mov instruction, which register acts as the source?
o In the mov instruction, the source register is rb.
5. What operation does the INC2 control signal perform?
o The INC2 control signal increments the PC by 2.
6. Which control signal is used to load the Memory Buffer Register (MBR)?
o The control signal used to load the Memory Buffer Register (MBR) is LMBR.
7. What is the size of the data bus in the external FALCON-A CPU interface?
o The size of the data bus in the external FALCON-A CPU interface is 16-bit.
8. Which instructions are available in FALCON-A but not in the SRC processor?
o The instructions available in FALCON-A but not in the SRC processor are in and
out.
9. In the call instruction, where are the contents of the PC stored in step T3?
o In the call instruction, the contents of the PC are stored in buffer register C in
step T3.
10. What does the control signal PCout do?
o The control signal PCout enables the PC to place its contents on the internal bus.

Lecture 13:
1. Describe the function of the brzr rb, rc instruction.
o The brzr rb, rc instruction branches to the address in rb if the value in rc is
zero.
2. What additional step is included in the brlzr ra, rb, rc instruction compared to
the brzr rb, rc instruction?
o The brlzr ra, rb, rc instruction includes an additional step where the current
value of the program counter is saved to ra.
3. Why is a barrel shifter suggested for shift instructions in FALCON-A?
 o A barrel shifter is suggested for shift instructions in FALCON-A to handle
multiple-bit shifts efficiently, avoiding timing problems associated with single-bit
shifts.
4. How many bits wide is the FALCON-A processor bus, and how does it compare to
the SRC processor bus?
o The FALCON-A processor bus is 16-bits wide, whereas the SRC processor bus is
32-bits wide.
5. List the primary differences in the register sets between FALCON-A and SRC
processors.
o FALCON-A has 8 registers, each 16-bits wide, while SRC has 32 registers, each
32-bits wide. Additionally, the special registers (PC, IR, MAR, and MBR) in
FALCON-A are 16-bits wide, compared to 32-bits in SRC.
6. Where are the higher and lower 16-bits of the result stored in the mul ra, rb, rc
instruction in FALCON-A?
o The higher 16-bits are stored in the CH register, and the lower 16-bits are stored
in the C register.
7. Explain the role of the AH and CH registers in FALCON-A.
o The AH register is used to store the higher 16-bits of a 32-bit operand, while the
CH register stores the higher 16-bits of a 32-bit result.
8. What steps are involved in the execution of the div ra, rb, rc instruction in
FALCON-A?
o The first three steps fetch the instruction. In T3, the contents of rb are placed in
buffer register A. In T4, the contents of register R[0] are placed into register AH.
In T5, the division takes place, producing the remainder in CH and the quotient in
C. In T6, the quotient is transferred to register R[ra], and in T7, the remainder is
transferred to R[0].
9. How is the 5-bit immediate constant c1 sign-extended to 16 bits in the addi ra, rb,
c1 instruction?
o The 5-bit immediate constant c1 is sign-extended to 16 bits by replicating the sign
bit (bit 4) to the leftmost 11 positions.
10. What is the op-code for the jz instruction, and what condition does it check?
o The op-code for the jz instruction is 19, and it checks if the contents of the
specified register are zero.

Lecture 12:
Short-Answer Questions

1. What are the two main sub-systems of a processor that are involved in the design
process?
o Answer: The data path and the control unit.
2. Explain the role of the Timing Step Generator in the SRC data path.
o Answer: The Timing Step Generator ensures the correct and controlled execution
of instructions by providing mutually exclusive and sequential timing intervals,
analogous to clock cycles in an actual processor.
 3. Describe the function of the Program Counter (PC) in the SRC.
o Answer: The Program Counter (PC) holds the address of the next instruction to
be executed. Its value is incremented after loading each instruction, and it can also
be updated based on branch decisions.
4. What is the significance of structural RTL in the processor design process?
o Answer: Structural RTL describes how specific operations are performed using
the actual hardware implementation, ensuring that the execution steps satisfy the
time and space requirements of the CPU.
5. How does the Memory Address Register (MAR) interact with the memory sub-
system in the SRC?
o Answer: The Memory Address Register (MAR) takes input from the ALSU as
the address of the memory location to be accessed and transfers the memory
contents at that location onto the memory sub-system.
6. In the context of instruction execution, what is the difference between Behavioral
RTL and Structural RTL?
o Answer: Behavioral RTL describes the abstract behavior of the processor in
response to instructions without binding to a specific implementation, while
Structural RTL shows the actual implementation steps and hardware details
required to execute those instructions.
7. List the seven steps involved in the processor design procedure.
o Answer:
1. ISA Design
2. Behavioral RTL Description
3. Implementation of the Data Path
4. Structural RTL Description
5. Control Unit Design
6. 2-bus and 3-bus designs
7. The machine reset and exceptions
8. Why is it important to consider the effect on overall performance during the design
phase of a processor?
o Answer: Considering the effect on overall performance is crucial because the
design decisions directly impact the execution time (ET), which is dependent on
the instruction count (IC), clock cycles per instruction (CPI), and clock cycle time
(T). Optimizing these factors ensures efficient and effective processor
performance.

By using these MCQs and short-answer questions, you can effectively review and assess
understanding of Lecture No. 12's content on the design process and structural RTL for the SRC.

Lecture 10:
Short-Answer Questions

1. Explain the purpose of the 'push' and 'pop' instructions in the FALCON-E.
 o Answer: The 'push' instruction is used to push the contents of a register onto the
stack, while the 'pop' instruction is used to pop a value from the top of the stack
and store it into a register.
2. Describe the memory organization of the FALCON-E.
o Answer: The memory of FALCON-E is organized as 1-byte cells, with a word
size of 32 bits (4 bytes). It has a memory space of 2^32 bytes, accessed in 4-byte
chunks.
3. What does the 'ret' instruction do in the FALCON-E?
o Answer: The 'ret' instruction is used to return control to the normal flow of a
program after an interrupt or a procedure call concludes.
4. Explain the purpose of the 'ld' and 'st' instructions in the FALCON-E.
o Answer: The 'ld' instruction loads a memory word from a specified address into a
register, while the 'st' instruction stores a value from a register into the memory
location specified by the immediate operand field.
5. How are general-purpose registers encoded in FALCON-E instructions?
o Answer: General-purpose registers are encoded using 3 bits each, allowing
representation of up to 8 registers. For example, R0 is encoded as 000, R1 as 001,
and so on.