2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia)
Wavelet PWM Technique for Cascaded Multilevel
Inverter
Chun Fang Zheng1, Bo Zhang2, Dongyuan Qiu2, Xiaohui Zhang2, Rui Li1, Qing Lin3
1: Department of Ship Engineering 2: School of Electric Power
Guangzhou Maritime Institute South China University of Technology
Guangzhou China Guangzhou China
zcf219@163.com , epbzhang@scut.edu.cn, epdyqiu@scut.edu.cn
Abstract — The wavelet PWM (WPWM) technique has been
applied in the two-level inverters successfully, but it is impossible
to apply directly the WPWM technique to multilevel inverters.
This paper proposes two kinds of WPWM techniques suitable for
a cascaded multilevel inverter, analyzes the control strategy with
the WPWM and obtains the design of its parameters. The
simulation results show the proposed WPWM methods can get
high magnitudes of the output fundamental frequency
component, low total harmonic distortion and simpler digital
implementation.
Keywords—Cascaded multilevel inverters, Wavelet modulation,
SPWM
I. INTRODUCTION
Multilevel inverter is a new type of high voltage large
capacity power converter with the advantages such as improved
voltage waveform on the AC side, smaller filter size, lower
electromagnetic interference and lower acoustic noise [1]. So
multilevel inverter options are attracting greater attention in the
fields of the industrial motor drives, renewable energy, FACTS,
fuel electromagnetic [2]. Three different topologies have been
proposed for multilevel inverters: diode clamped (neutral
clamped), capacitor clamped (flying capacitor), cascaded
multilevel inverter. Among them, cascade multilevel inverter is
the most attractive one, since it requires the least number of
components and increases the number of levels without
requiring high ratings on individual devices, is free of DC
voltage balancing problem, results in simple circuit layout and
is modular in structure. Because of the wide application of
cascaded multilevel inverter, the study of its control strategy is
increasingly highlighted. Many modulation strategies have been
developed for cascaded multilevel inverters such as carrier
based SPWM, specific harmonic elimination (SHE), space
vector modulation (SVM) etc.. But searching an optimizing
PWM control scheme to decrease the harmonic content of
inverter’s output waveform and improve the inverter’s output
performance is always an important research area for inverters
[3-6].
In recent years, S. A. Saleh has proposed and developed the
wavelet modulation techniques on different two-level converters
[7-11]. The wavelet modulation technique is based on
establishing a non-dyadic type multi-resolution analysis (MRA),
which is required to support a non-uniform recurrent sampling-
reconstruction process. The merits of this approach includes
simpler realization by digital algorithm, higher magnitudes of
the fundamental output voltage and lower harmonic contents
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better than the other types of modulation techniques. The
literatures [7-8] have proposed how to implement of a wavelet
modulation technique for single-phase voltage source inverters.
The literatures [9-10] have proposed how to implement of a
wavelet modulation technique for three-phase voltage source
six-pulse inverters. The literature [11] has proposed how to
implement of a wavelet modulation technique for AC-DC
converters. In a word, the current research of the WPWM
technique has been focused on the two-level inverter.
Thus, this paper presents the development and performance
testing of the WPWM technique for cascaded multilevel
inverters. The cascaded multilevel inverter with SPWM
technique is reviewed in Section II. The cascaded multilevel
inverter with WPWM technique is proposed in Section III. The
analysis of WPWM technique for the cascaded multilevel
inverter is provided in Section IV. Conclusion is given in
Section V.
II. CASCADED MULTILEVEL INVERTERS
Cascaded multilevel inverter consists of a series of single-
phase H-bridge converter cells. The desired output voltage can
be synthesized from several separate dc sources (SDCSs).
Fig.1 shows a single-phase structure of a cascade inverter with
SDCSs [1]. In Fig.1, each cell can generate three different
voltage levels, +Vdc, 0 and -Vdc by different combinations of
the switches, S1, S2, S3 and S4. The ac output of each cell is
connected in series such that the synthesized voltage
waveform is the sum of the output of the individual H-bridge
converter cell. Then the number of output voltage level of a
cascade multilevel inverter is 2M+1, where M is the number of
dc sources. A typical output voltage waveform of a single-
phase five-level cascade inverter (M=2) is shown in Fig.2,
where Uan=U1+U2.
One of commonly used control strategies is sinusoidal
pulse width modulation (SPWM). SPWM is realized by
comparing a sinusoidal reference voltage waveform with a
triangular carrier waveform to generate gate signals for the
switches of inverter [12-13]. The multi-carrier SPWM control
methods have been implemented to increase the performance
of multilevel inverters and have been classified according to
vertical or horizontal arrangements of the carrier signal. The
vertical carrier distribution techniques are defined as Phase
Disposition (PD) as shown in Fig.2, Phase Opposition
Disposition (POD), and Alternative Phase Opposition
Disposition (APOD), while horizontal arrangement is known
 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia)
as Phase Shifted (PS) control technique shown in Fig.3.
Besides others, PS-SPWM is only useful for cascaded H-
bridges and Flying capacitors, while PD-PWM is more useful
for NPC [14].
Fig.1 Single-phase structure of a cascade multilevel inverter
Fig.2 Carrier and modulation signals in PD-SPWM
Fig.3 Carrier and modulation signals in PS-SPWM
III. THE WPWM TECHNIQUE FOR CASCADED MULTILEVEL
INVERTERS
A. The principle of WPWM technique
The WPWM technique is based on sampling- reconstructing
a reference-modulating signal in a non-uniform recurrent
manner using sets sampling and synthesis basis functions [7-8].
These sampling basis functions are generated as dilated and
translated versions of the scale-based linearly-combined scaling
function ϕ（j , k ) (t ) . Furthermore, synthesis basis functions are
generated as dilated and translated versions of the scale-based
linearly combined synthesis scaling function ϕ( j , k ) (t ) . The
scale-based linearly-combined scaling function is defined at
scale j as
ϕ j (t ) = φH (2 j +1 t ) + φH (2 j +1 (t − 1 + 2− ( j +1) ))
(1)
and ϕ( j , k ) (t )＝ϕ ( 2 j t − k ) , where j=0, 1, 2, 3, … and φH (t ) is
1 t ∈ [0,1]
the Harr scaling function that is given by φH (t ) =  .
0 t ∉ [0,1]
Also, the synthesis scaling function ϕ (t ) associated with
ϕ (t ) can be defined as
ϕ j (t ) = (φH ) j (t ) − ϕ j (t ) and ϕ( j , k ) (t )＝ϕ ( 2 j t − k )
(2)
Using these two dual scaling functions, a continuous-time
signal xc (t ) can be expanded as
xc (t ) =  xc (t ),ϕ ( 2 j t − k ) ϕ ( 2i t − k )
k j
(3)
where j, k ∈ Z, where Z is the set of integer numbers. Such
form of signal processing suggests that a continuous-time
( )
signal xc (t ), ϕ 2 j t − k can be recovered from its samples
using sets of synthesis functions ϕ ( 2 j t − k ) .
The literature [8] proved that the switching pulses for
inverter can be generated by using dilated and shifted versions
of the synthesis scaling function ϕ( j , k ) (t ) . When each cycle of
xc (t ) is divided by a finite number of sample groups D, the
distance between the sample groups [td1, td2] will change as
scale j changes, where
td 1 = d + 2− j −1
td 2 = d + 1 − 2− j −1 , d = 0,1, 2, ⋅⋅⋅, ( D − 1)
(4)
And referring to the procedure about how to implement the
WPWM technique given in the literature [7], the flowchart for
WPWM is shown as Fig.4 [15], where Tm is the period of the
reference sine wave.
B. PD-WPWM strategy for the cascaded multilevel inverter
According to above flowchart of WPWM, once Tm, j0 and
D are given, the time points (td1 and td2) of each sample group
can be calculated and the driving pulses can be generated by the
time points in each sample group, which can be integrated into
two unipolar-controlled signals (W1 and W2). A simple way is
using same control signals for each H-bridges but its output
waveform has poor quality. Thus, the WPWM technique is not
used to control the switches of cascaded multilevel inverter
directly. Here, select a single-phase cascaded five-level inverter
(M=2) as an example, referring to the concept of PD-SPWM,
the logic control scheme for the switches S1~S4 with PD-
 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia)

WPWM can be derived shown as Fig.5. In Fig.5, W1 and W2 are
generated according to the flowchart of WPWM technique
shown as Fig.4; a pulse P1 has a half-cycle symmetry property,
its frequency is the double of reference sine wave and its pulse
width is variable in order to adjust the distribution of the output
voltage levels; a pulse C1 is a square signal and its frequency is
same as the reference sine wave. Thus, the PD-WPWM
operation principle for the five-level inverter (M=2) can be
shown as Fig.6.
Further study shows that a pulse P2 need to be added to
control a single-phase cascaded seven-level inverter (M=3) by
PD-WPWM, and its logic control scheme for the switches
S1~S4 with PD-WPWM can be derived shown as Fig.7, where
P1 and P2 have same property but the pulse width of P1 and P2
is different. Similarly, when the cells of cascaded multilevel
inverter is M, M pulses need to be added for the control
strategy of PD-WPWM, where M-1 pulses have same property
as P1 but the pulse widths are different.

Fig.7 Logic control scheme for the switches of seven-level inverter

with PD-WPWM technique

C. PS-WPWM strategy for the cascaded multilevel inverter

The PD-WPWM strategy need to add M pulses to control M
cells of the cascaded multilevel inverter, which will make the
logic control scheme be more complex when M increases.
Referring to the concept of PS-SPWM, the logic control
Fig.4 Flowchart to implement the WPWM technique scheme for the switches S1~S4 of five-level inverter with PS-
WPWM can be derived, as shown in Fig.8. In Fig.8, the initial
d0 W1 First cell value of d (d0,d1) is different to realize phase shifted among
S1
j0
WPWM
S3
different cells. Thus, the PS-WPWM operation principle for the
technique W2 five-level inverter (M=2) can be shown in Fig.9.
D S2
S4
P1 Second cell
Pulses S1
S3
S2
C1 S4
Pulses

Fig.5 Logic control scheme for the switches of five-level inverter with
PD-WPWM technique

Fig.8 Logic control scheme for the switches with PS-WPWM

technique

Fig.6 PD-WPWM operation principle of five-level inverter

 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia)

referencing to PD-SPWM and PS-SPWM techniques. The

simulation results have shown that the PD-WPWM and PS-
PWM for cascaded multilevel inverter can get high
magnitudes of the output fundamental frequency component,
low THD and simple digital implementation, which will
promote the application of WPWM technique in power
electronics converters.

Acknowledgment
This research has been supported in part by the Key
Program of the National Natural Science Foundation of China
under Grant 51437005, the National Natural Science
Fig.9 PS-WPWM operation principle of five-level inverter Foundation of China 51277079, the Guangdong Public
IV. ANALYSIS OF WPWM TECHNIQUE FOR THE CASCADED Welfare Research and Capacity Building Foundation
MULTILEVEL INVERTER (2015A010103024) and by the project of Guangzhou Science
and Technology(2014Y200051).
For PD-WPWM, according to Fig.5 and Fig.7, the width
and position of the pulses (W1 and W2) generated by the
WPWM technique are determined when D and j0 are given,
and C1 is a determined square wave when the frequency of the
reference sine wave is given. Therefore, the only way of
changing the control signals for switches is by adjusting the
pulse width of P1 and P2, the distribution of the output voltage
levels is affected. For PS-WPWM, according to Fig.8, the
initial value of d is different to realize phase shifted among
different cells, which will affect the distribution of the output
voltage levels.
In order to verify the control strategy of PD-WPWM and
PS-WPWM techniques for Cascaded multilevel inverter, this
paper selected two single-phase cascaded inverters as
examples, one is five-level and the other is seven-level. The
simulation parameters are input voltage Ud=50V, D=30,
fm=50Hz (fm is the frequency of the reference sine wave), j0=1.
In PD-WPWM, a lots of simulation results show that the
pulse width of P1 for the single-phase cascaded five-level
inverter is near 60% to get smaller THD and higher magnitude
of the output fundamental frequency component; the pulse
width of P1 is near 45% and the pulse width of P2 is near 75%
for the single-phase cascaded seven-level inverter to get smaller
THD and higher magnitude of the output fundamental
frequency component; the output voltage Uab and its spectrum
for the single-phase cascaded five-level and seven-level inverter (a) Five-level
by PD-WPWM are shown in Fig.10(a) and (b), respectively.
In PS-WPWM, a lots of simulation results show that the
d0=0, d1=2.5 for the single-phase cascaded five-level inverter
can get smaller THD and higher magnitude of the output
fundamental frequency component; d0=0, d1=1.2, d2=1.8 for
the single-phase cascaded seven-level inverter can get smaller
THD and higher magnitude of the output fundamental
frequency component; the output voltage Uab and its spectrum
for the single-phase cascaded five-level and seven-level inverter
by PD-WPWM are shown in Fig.11(a) and (b), respectively.

V CONCLUSIONS
This paper develops the WPWM technique for cascaded
multilevel inverters. The logic control scheme with PD-
WPWM and PS-PWM techniques have been obtained
 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia)

(b) Seven-level
Fig.10 Output voltage Uab and its spectrum for single-phase
cascaded inverter controlled by PD-WPWM (b) Seven-level
Fig.11 Output voltage Uab and its spectrum for single-phase
cascaded inverter controlled by PS-WPWM

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