Printed Page: 1 of 1

Subject Code: BCS302

Roll No:

B.TECH
Model Paper -1/2
(SEM III) THEORY EXAMINATION 2023-24
COMPUTER ORGANISATION AND ARCHITECTURE
Time: 3 Hours Total Marks: 70
Note: Attempt all Sections. If require any missing data; then choose suitably.

SECTION A
1. Attempt all questions in brief. 2 x 7 = 14
Q.No. Question Marks CO
a. Differentiate between RISC and CISC. 2 3
b. Define the instruction cycle. 2 3
c. Define Virtual memory. 2 5
d. Define bus and memory transfer. 2 1
e. Differentiate between vertical and horizontal vertical microprogramming 2 3
f. Differentiate Linear and Nonlinear Pipeline Processors. 2 3
g. Compare micro instruction and microprogram. 2 2

SECTION B
2. Attempt any three of the following:
a. Explain the difference between vectored and non-vectored interrupt. 7 5
Explain using examples of each.
b. Explain the IEEE-754 standard for floating point representation. Express 7 2
(314.175)10 in all the IEEE-754 models.
c. Consider a cache consisting of 256 blocks of 16 words each for a 7 4
total of 4096 words and assume that the main memory is
addressable by a 16-bit address and it consists of 4K blocks. How
many bits are there in each of the TAG, SET, and WORD fields for
the 2-way set associative technique?
d. Draw a diagram of a bus system in which it uses a 3 3-state buffer and 7 1
decoder instead of a multiplexer.
e. Differentiate between hardwired and microprogram control units. Explain 7 3
each component of the hardwired control unit organization.

SECTION C
3. Attempt any one part of the following:
a. What do you mean by processor organization? Explain various types of 7 1
processor organization.
b. An instruction is stored at location 400 with its address field at location 7 1
401. The address filed has a value of 500. A processor register r1 contains
the number 200, Evaluate the effective address if the addressing mode of
the instruction is 1. Direct 2. Register direct 3. Register indirect 4. Relative
4. Attempt any one part of the following:
a. How the systematic multiplication process of (-15) × (-16) using Booth’s 7 2
algorithm.
b. Describe the derivation procedure of the look-ahead carry adder by an 7 2
example with the help of a block diagram.
5. Attempt any one part of the following:
a. Write a program to evaluate the arithmetic statement. P = ((X − 𝑌 + 𝑍) ∗ 7 3
(A ^ B))/( C ^ D ∗ E) 10x1=10 By using (i) Two address instructions (ii) One
address instructions (iii) Zero address.
b. Draw the flowchart of the instruction cycle and explain it in detail 7 3
6. Attempt any one part of the following:
a. Discuss 2D RAM and 2.5D RAM with a neat diagram 7 4
b. Calculate the page fault for a given string with the help of LRU and FIFO 7 4
page replacement algorithm size of frame=4 and string
1,2,,3,4,5,1,5,6,7,2,6,7,8,2,3,2,2,2,3,4,4
7. Attempt any one part of the following:
a. With a neat schematic diagram, explain about DMA controller and its 7 5
mode of data transfer.
b. What do you mean by asynchronous data transfer? Explain strobe control 7 5
and handshaking mechanism.

--------Best of Luck-------
 Printed Page: 1 of 1
Subject Code: BCS302

Roll No:

B. TECH
Model Paper -2/2
(SEM III) THEORY EXAMINATION 2023-24
COMPUTER ORGANISATION AND ARCHITECTURE
Time: 3 Hours Total Marks: 70
Note: Attempt all Sections. If require any missing data; then choose suitably.

SECTION A
1. Attempt all questions in brief. 2 x 7 = 14
Q.No. Question Marks CO
a. Perform the following operation on signed numbers using 2’s 2 2
compliment
method: (56)10 + (-27)10.
b. What do you mean by locality of reference? 2 3
c. Describe cycle stealing in DMA. 2 5
d. List three types of control signals. 2 1

e. What do you mean by page fault? What is the hit ratio 2 4

f. list the difference between static RAM and dynamic RAM 2 1

g. Draw a diagram of the bus system using a multiplexer 2 1

SECTION B
2. Attempt any three of the following:
a. Write a program to evaluate the arithmetic statement X= 7 3
𝐴−𝐵+𝐶×(𝐷×𝐸−𝐹) (𝐺+𝐻×𝐾)
i. Using a general register computer with three address
instructions.
ii. ii. Using an accumulator-type computer with one address
b. Discuss the various types of address mapping used in cache memory. 7 4

c. What is a microprogram sequencer? With the help of a block diagram 7 3

explain the working of the microprogram sequencer
d. What is associative memory? Explain with the help of a block diagram. 7 2
Also, mention the situation in which associative memory can be
effectively utilized.
e. What is addressing mods? Explain some addressing modes with a diagram 7 5

SECTION C
3. Attempt any one part of the following:
a. A moving arm disc storage device has the following specifications: 7 1
Number of Tracks per recording surface 200 Disc rotation speed of 2400
revolution/minute Track-storage capacity of 62500 bits Estimate the
average latency and data transfer rate of this device.
b. Describe the Sequential Arithmetic & Logic unit (ALU) using the proper 7 2
diagram

4. Attempt any one part of the following:

a. A Computer uses a memory unit with 256K words of 32 bits each. A 7 2
binary instruction code is stored in one word of memory. The instruction
has four parts: an indirect bit, an operation code, a register code part to
specify one of 64 registers, and an address part. (i) How many bits are
there in the operation code, the register code part, and the address part?
(ii) Draw the instruction word format and indicate the number of bits in
each part. (iii) How many bits are there in the data and address inputs of
the memory?
b. Define interrupt. Also, discuss different types of interrupt. 7 5

5. Attempt any one part of the following:

a. How pipeline performance can be measured? Discuss. Give a space-time 7 3
diagram for visualizing the pipeline behavior for a four-stage pipeline.
b. What is micro programmed control unit? Give the basic structure of the 7 3
microprogrammed control unit. Also, discuss the microinstruction format
and the control unit organization for typical microprogrammed
controllers using a suitable diagram.
6. Attempt any one part of the following:
a. Give the structure of a commercial 8MX 8-bit DRAM chip. 7 4

b. A moving arm disc storage device has the following specifications: 7 4

Number of Tracks per recording surface 200 Disc rotation speed of 2400
revolution/minute Track-storage capacity of 62500 bits Estimate the
average latency and data transfer rate of this device.
7. Attempt any one part of the following:
a. How is virtual memory mapped into physical address? What are the 7 5
different methods of writing into a cache( cache writing policy)?
b. What are the different methods of asynchronous data transfer? Explain in 7 5
detail.
--------Best of Luck-------