Analysis & Design of MOSFET based 10

Transistor SRAM Memory for Low Power

Applications
Ketan Rojasara Maitreya Parekh Bhavesh Soni
Student of EC Department, Student of EC Department. Assistant Professor of EC Department
Ganpat University Ganpat University Ganpat University
Gujarat,384012, Gujarat,384012, Gujarat,384012,
ketanrojasara22@gnu.ac.in maitreyaparekh22@gnu.ac.in bhavesh.soni@ganpatuniversity.ac.in

Abstract: The demand for portable devices like mobile, has three terminals: the drain (D), gate (G), and source
electronics devices and laptops is really high, and people (S). A voltage connected to the gate (G) terminal
want them to work better and use less energy. These regulates current flow between drain (D) and source
gadgets use a type of memory that doesn't use much (S). In terms of relatively high speed and low loss
power, which is important to keep their backup batteries
working. In line with this, a new kind of memory chip has
operation, MOSFETs outperform bipolar transistors.
been created and tested. This chip is called "10T static According to the polarity of the channel, there are N
random-access memory (SRAM) cell." It's designed to type and P type, and according to the control
be more stable, work at a moderate speed, and use less mechanism, there are depletion type with normally on
energy. The LT-Spice tool was used to study how this (deactivated with gate voltage 0 V) and enhancement
chip would work with technology that's incredibly tiny type with normally off (gate voltage 0 V off).
only 18 nanometers wide. To make this new memory chip
special, they used a trick that makes reading information
more stable. They also figured out a way to reduce the The MOSFET allows you to regulate the flow of
power that's wasted when the chip is just sitting around. electricity with a small amount of voltage at its gate,
Imagine it's like turning off lights in empty rooms to save just like you can with a faucet you can turn with a
electricity. This new memory chip is like that it saves handle. As a result, it behaves like a resistor that alters
power when it's not actively working. The great thing is its resistance in response to the voltage applied.
that this new chip is much better at saving power Nowadays, MOSFETs are frequently employed in
compared to the regular memory chip that's usually electrical circuits in place of the JFET, another type of
used. When it comes to reading and writing information, transistor.
this new chip uses way less power about 63.6% less for
reading and 39.9% less for writing than the usual one.
And it's not just about using less power; this new
memory chip is also more reliable. When you want to
read or write something, it's more likely to work well. In
fact, it's about 1.91 times better for reading and 1.53
times better for writing, compared to the old version.
Plus, this new chip makes reading things a bit faster
about 1.2 times faster than the regular chip. But, when it
comes to writing information, it takes a bit longer – about
1.6 times longer than the usual memory chip.

INTRODUCTION
1.1 Introduction of MOSFET:
A type of transistor called a MOSFET functions in
electronic devices like a small switch. It is unique in
that it features a section dubbed the "gate" that is kept
off from the main path through which energy flows. It
resembles a particular gate because of this separation,
which may be opened or closed using a little voltage.
It may have a very high barrier to letting electricity in Figure 1.1.1: Basic MOSFET Structure
as a result of this separation. The MOSFET typically
 The diagram above depicts the MOSFET's
fundamental construction. When compared to the
creation of the JFET, the MOSFET is built
significantly differently. In both enhancement and
depletion modes, the electric field produced by the
gate voltage modifies the flow of charge carriers, such
as electrons in the case of N-channel MOSFETs and
holes in P-channel MOSFETs. Here, two N-type
regions are employed beneath the drain and source
terminals, and the gate terminal is located on top of a
thin metal oxide insulation layer.
1.2 CMOS inverter :
The two cross-coupled inverters are surrounded by the
memory created in the SRAM cell. The circuit
diagram for a CMOS inverter is shown below. The
general CMOS inverter structure is made up of PMOS
and NMOS transistors, with the pMOS transistors
grouped at the top and the nMOS transistors
positioned at the bottom.
Figure 1.2.2 : CMOS Inverter input and output
waveform
Similar to this, when the CMOS inverter receives a high
input voltage, the PMOS transistor is turned off while
the NMOS transistor is turned on to prevent as many
electrons from reaching the output voltage and provide
a low logic output value.
1.3 Introduction of SRAM:
SRAM stands for Static Random Access Memory. The
SRAM Memory used in this work was a 6T SRAM cell,
which features two cross-coupled inverters in addition
to access transistors for reading and writing data. If we
suppose that the first inverter's output is logic 0 and its
input is logic 1, the memory built into the SRAM cell is
stored around the two cross-coupled inverters. As a
result, after one cycle, the second inverter's output will
be logic 1. As long as the SRAM cell is receiving
power, logic 1 will continue to flow in the inverters,
negating the need for routine circuit refreshing.

Figure 1.2.1: The Schematic of Basic CMOS

inverter

This is one approach to connect the CMOS inverter's

PMOS and NMOS transistors. Along with a voltage
supply (VDD) at source terminal of the PMOS
transistor and a ground (GND) terminal at the source
terminal of the NMOS transistor, the drain (D) and gate
Figure 1.3.1: Basic SRAM
(G) terminals of the NMOS transistor are connected.
The input voltage (Vin) is connected to both transistors’
gate terminals, and the output voltage(Vout) is
The use of wireless body-area networks to monitor
connected to the transistors' drain (D) terminals.
patients' health is a significant leap in technology. This
network consists of sensors that are used to gather data
The PMOS transistor turns on when the CMOS inverter
and are attached to people's bodies. The wireless body
receives a low input voltage, whereas the NMOS
area network tracks the patient's health in real time with
transistor switches off by allowing electrons to flow
the aid of signal processing using wireless sensor that
through the gate terminal and producing a high logic
use the processor and SRAM memory.
output value.
SRAM Memory is a sort of semiconductor memory cell
that can store binary data of a single bit; as a result,
power consumption by SRAM Memory should be
lower for lengthy battery backup. It utilizes less power The suggested 9T single ended SRAM cell uses little
and is faster than dynamic SRAM. power. However, this cell's bitline is connected to two
access transistors, which results in a greater bitline
2.1 PROPOSED 6 T SRAM CELL: capacitance.

Traditional (6T) SRAM cells have a straightforward 2.2 PROPOSED 7T SRAM CELL:
architecture, however they have issues with data
disturbance. Let's say a standard 6T cell has a Q= '1'
(QB = '0') storage value. Because of the voltage
division action between transistors M6 and M3, voltage
at QB begins to increase during read. When the voltage
(at QB) reaches the left inverter's (M2-M4) threshold
voltage, transistor M4 can come on, causing the cell to
leak content. Data disruption is the name given to this
issue. The standard 6T employs a stronger pulldown
(M3) transistor as compared to the access transistors
(M6) in order to reduce the problem of data disturbance
during read.
However, the access transistor needs to be more
powerful than the pullup transistor for dependable write
operation. As a result, the access transistor design
requirement for the traditional 6T cell is incompatible.
As a result, it becomes necessary to construct an SRAM
cell that can provide accurate read and write operations
Figure: 2.2.1 Schematic of 7T cell SRAM
Due to the unfavorable time the access transistors'
activation to reach the latch takes, reading in a standard An extra transistor is inserted into ground route of a
6T cell happens quite slowly. In SRAM, a delayed read 6T SRAM Memory in a 7T SRAM Memory
operation does indicate that the response time for a configuration to lessen leakage while the cell is in
specific read operation and write operation would be standby mode. The bottom transistor's purpose in
quite long, leading to more leakage power over this standby mode is to cut off the ground path and stop
extended time period in the idle circuit. The cell is leakage paths through the inverter transistor sources,
unsuitable for use in real applications due to this decline although this cell is unable to speed up reading.
in performance..
2.3 PROPOSED 8T SRAM CELL:

Figure 2.1.1 Schematic of 6T cell SRAM

Researchers have recently suggested a number of

different SRAM cell configurations. To solve the read-
Figure: 2.3.1 Schematic of 8T cell SRAM
related data disturbance issue, an 8T cell is suggested.
The size of the transistors has a significant impact on
the data stability and operation of 6T and 7T SRAM
cells. The ratio of the size of the pull-down transistors
to the access transistors serves as a metric for
describing the stability of 6T and 7T SRAM cells.
Higher improves data stability but at the cost of more
leakage power and more cell area.
An 8T cell approach was employed to solve issue of
data storage destruction during read operations. For
this implementation, the data retention element and the
data output element were separated using separate
write/read bit and word signal lines. A read-disturb-
free operation is provided by this cell implementation.
2.4 10T SRAM CELL
This 10T SRAM cell based on a MOSFET. The PM1
(PMOS1), NM1 (NMOS1), PM2 (PMOS2), and NM2
(NMOS2) transistors, which are connected with back-
to-back invertors, make up the main latch circuitry.
The access transistors, NM3 and NM4, allow the
read/write operation.
Figure 2.4.1 Schematic of 10T cell SRAM
Dynamic loop cutting transistors, also known as NM5
and NM6 transistors, help to widen the write static
noise margin. NM7 and NM8 transistors come
together to form a read decoupled arrangement. This
reduces the conflict between the access transistors and
increases the RSNM. The suggested cell also employs
broader access transistors to improve the writing
capability. The transistor is stacked in order to reduce
read (RD) power consumption. Additionally, a VGD
signal is applied, which reduces bit-line (BL) leakage
current.
3 Read Operation:
depicts the schematic for an SRAM cell with 10
transistors. Pull-down transistors NM1(NMOS1) and
NM2(NMOS2) are connected in series with transistors
NM5(NMOS5) and NM6(NMOS6). Bit-lines are used
to operate the NM5(NMOS5) and NM6(NMOS6)
transistors, which function as dynamic loop cutters.
The supply voltage is coupled to the RD and RBL
signals.
The virtual ground (VGD) or worldline (WL) signals
are connected by GND. Assume that storage node Q
has logic '0' available. It causes the PM2 transistors to
turn on, resulting in a terminal QB logic '1'. Through
the NM7 and NM8 transistors, the voltage at QB
terminal discharges RBL by activating the transistors
NM8. RBL bit-line(BL) logic '0' will therefore be
reachable as a result.
4 Write Operation:
The WL and VGD signals are set to logic high at the
start of the write operation while the RD signal is set
at logic '0'. Bit-line and bit-line bar (BL and BLB)
depend on logic '1' or logic '0' is going to be written on
nodes Q/QB and are connected to complimentary
logics.
When writing logic "1" or "0", bit-line (BL) is
connected with "1" or "0", where bit-line bar (BLB) is
related with "1" or "0." Think about the case when
logic '0' is stored in storage node Q. The
NM5(NMOS5) and NM6(NMOS6) transistors are
respectively turned on and off while BL/BLB stays at
Vdd/GND. As a result, the left inverter's pull-down
intensity is decreased because the left side latch
inverter is now isolated from GND. This shows that
storage node Q's logic '1' is straightforward to
construct.
5 Hold Mode:
Bit-line (BL) leakage current is a significant factor in
hold mode. In order to switch on the transistors that
cut loops, bit-lines (BL) are connected to the power
source. The wake-up time can be cut down. The access
transistors are turned off when the WL signal is set to
ground. In order to isolate the read port, RD/VGD
signals are connected to GND/Vdd.
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CONCLUSION
The conventional 6T, 7T, 8T, and proposed 10T
SRAM Memory implementations are included in this
report's comparison of the performance metrics for
five SRAM cell topologies. Analysis is being done in
particular on each SRAM cell's lowest power
dissipation, read/write delay, and read behavior. While
a 7T SRAM cell would concurrently lower leakage
power and increase data stability, leakage is not
significantly improved compared to an 8T SRAM cell.
This research paper suggests a 10T SRAM cell
architecture to get over this issue, which adds
transmission gate and separate inverter as a single-end
read port. The findings demonstrate that, in
comparison to the 6T and 7T, 8T SRAMs, the 10T
SRAM consistently consumes the least amount of
power, reads faster, and improves read stability.
So MOSFET based 10T SRAM may be a suitable or
good choice for good noise tolerance and low power
applications
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