2638 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO.

3, MAY/JUNE 2021

A Dual Active Bridge Converter With Multiphase

Boost Interfaces for Single-Stage Bidirectional
DC–AC Conversion
Akhil Chambayil , Student Member, IEEE, and Souvik Chattopadhyay , Member, IEEE

Abstract—A novel bidirectional dual active bridge based dc–ac

converter is proposed in this article. The converter has multiphase
boost interfaces at both the dc and ac ports. The interleaved
operation of the multiphase units cancels the ripple currents and
eliminates the input filter requirement. The dc to ac conversion is
carried out in a single stage using only eight switches. The con-
verter utilizes the low-frequency and high-frequency components
in the inverter output to achieve both power conversion and power
transfer across the high-frequency transformer simultaneously. A
thorough analysis of the converter is carried out for the proper
design of the components. Based on the results, a detailed design
method is discussed. A multiresonant controller based phase-shift
control is suggested to eliminate the low-frequency ripple in the Fig. 1. Configuration of grid integration of energy storage systems.
input dc current. Finally, the effectiveness of the proposed con-
verter is validated using results obtained from a 3-kW hardware
prototype.
at times of peak demand [5], [6]. Isolated bidirectional converters
Index Terms—Bidirectional converter, dc–ac converter, dual are more popular for these applications because of their galvanic
active bridge (DAB), isolated converter, multiphase, single-phase, isolation feature and the high voltage conversion ratio possible
single-stage.
through the high-frequency transformer turns ratio [7]. Based
on the working principle, these converters can be classified into
I. INTRODUCTION two-stage topologies or single-stage topologies. In two-stage
ATTERY and supercapacitor-based energy storage sys- topology, the dc to ac conversion takes place in two stages. An
B tems are an integral part of photovoltaic and fuel cell based
clean energy electric systems [2], [3]. While interconnecting
initial dc to dc conversion stage is followed by another dc to ac
inversion stage [8]. The dc to dc conversion stage links the dc
such systems with ac grids at comparatively higher voltage voltage source at a lower voltage level to a regulated dc bus at a
levels, bidirectional power converters are used. They enable higher voltage level. Usually, isolated bidirectional phase-shift
the power flow in both directions allowing both charging and full-bridge (FB) converters or resonant DAB topologies are used
discharging of the batteries or supercapacitors [4]. The config- as dc–dc bidirectional converter [9]–[11]. A dc to ac inversion
uration of the system is depicted in Fig. 1. Apart from this, stage is cascaded with the dc bus to connect it with the grid or to
bidirectional power converters are becoming popular in electric the ac load. The inverter maintains the dc bus voltage constant
vehicle charging applications, where they are used for normal by extracting power from the grid or delivering power to the grid
battery charging functions and also enable the new vehicle-to- or the load. The ac side is operated at unity power factor to meet
grid concept by allowing the vehicle to supply power to the grid the power quality standards and reduce the conduction loss due
to reactive current. The sinusoidal voltage and current at the ac
Manuscript received September 16, 2020; revised December 3, 2020; accepted side draws a power pulsating at double-line frequency from the
January 28, 2021. Date of publication February 9, 2021; date of current version
May 19, 2021. Paper 2020-IPCC-1412.R1, presented at the 2020 IEEE Applied dc bus. Usually, a large capacitor of few thousand microfarads
Power Electronics Conference and Exposition (APEC), New Orleans, LA, is used to absorb this pulsating power and keep the dc bus
USA, Mar. 20–24, and approved for publication in the IEEE TRANSACTIONS steady [12]. Such high capacitance is realized using electrolytic
ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee
of the IEEE Industry Applications Society. This work was supported by a capacitors. The large size and low lifetime of electrolytic capac-
project under the Department of Science and Technology (DST), Government of itors impose serious constraints on the converter development.
India under Project Sanction Letter No. DST/CERI/MI/SG/2017/086(IITKGP). Hence, many solutions are proposed to reduce the dc bus capac-
(Corresponding author: Akhil Chambayil.)
The authors are with the Department of Electrical Engineering, In- itance requirement [13]–[16]. In [14], an auxiliary bidirectional
dian Institute of Technology Kharagpur, Kharagpur 721302, India (e-mail: buck–boost converter is added across the dc bus to control the
akhilc@iitkgp.ac.in; souvik@ee.iitkgp.ac.in). ripple power coming from the ac side. The auxiliary circuit
Color versions of one or more figures in this article are available at https:
//doi.org/10.1109/TIA.2021.3058202. uses two more devices for its operation. A similar approach
Digital Object Identifier 10.1109/TIA.2021.3058202 using a boost–buck ripple eliminator is discussed in [15]. The
0093-9994 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 CHAMBAYIL AND CHATTOPADHYAY: DUAL ACTIVE BRIDGE CONVERTER WITH MULTIPHASE BOOST INTERFACES
complexities due to the auxiliary circuits and their control can
be overcome by using single-stage topologies. In single-stage
topologies, the dc to ac conversion is done in a single stage.
Hence, they are more compact as they require less number of
devices. Also, they can often achieve better efficiency due to
lower switching losses [17].
In [18] and [19], a bidirectional single-stage dc–ac converter
topology employing an FB inverter cascaded with a cyclocon-
verter through a high-frequency transformer is proposed. The
major challenge in this topology is to deal with the voltage spike
arising due to the breaking of the leakage inductor current during
the cycloconverter switching. An asymmetrical naturally com-
mutated phase angle control is proposed in [18] to obtain zero
current switching of the cycloconverter devices with improved
power conversion efficiency. Since the converter cannot guaran-
tee the zero voltage switching (ZVS) of FB inverter switches at
light load conditions, a carrier-based unipolar sinusoidal pulse
width modulation (SPWM) oriented modulation technique is
proposed in [19] to achieve ZVS of FB devices. A modulation
technique for cycloconverter for achieving ZVS operation of the
FB devices is proposed in [20]. Another bidirectional topology
employing a half-bridge converter on the ac side is proposed
in [21]. Using a combined phase-shift and frequency control,
this converter can achieve ZVS of all the devices over the full
range of the ac line voltage.
The high-frequency transformer leakage inductance induced
voltage spike issues are not present in DAB-based topolo-
gies [22]. A low device count DAB-based single-stage topol-
ogy is proposed in [23]. In this topology, the ac side bridge
output consists of a low-frequency component to interface
with the ac grid and a high-frequency component to facilitate
the power transfer with the dc side bridge. Series capacitors
are used to block the low-frequency voltage component from
appearing across the transformer and saturating the core. A
similar approach using a dual active series resonant converter
is proposed in [24]. For high-power applications, such series
dc blocking capacitors based topologies are impractical due to
their large size, expense, and low equivalent series resistance
requirements [25].
In this article, a low device count dual active bridge converter
based single-stage bidirectional dc–ac converter is proposed.
The converter does not employ any series capacitor. Also, the
converter has multiphase boost interfaces at both the dc and ac
ports. The multiphase structure reduces the input and output
current ripples. Hence, the filter capacitance at both the input
and output ports can be reduced. In the following section, the
topology and operating principle of the converter is explained. A
detailed switching analysis is carried out and the power transfer
equation and dab rms current equation are derived in Section III.
A fundamental frequency analysis is carried out in Section IV to
understand the power transfer across the DAB inductor. Device
rms current estimation technique is explained in Section V.
Section VI presents the ZVS analysis of various devices in
the converter. A detailed design methodology is presented in
Section VII. The control architecture is explained in
Section VIII. Finally, the experimental results are presented in
Section IX. Section X concludes the article.
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2639
II. TOPOLOGY AND OPERATING PRINCIPLE OF THE
PROPOSED CONVERTER
The topology of the proposed dc–ac DAB converter is shown
in Fig. 2. The converter consists of two FB circuits linked by a
high-frequency transformer as in a conventional DAB converter.
The inductor Ldab includes the transformer leakage inductance
and extra series inductance added to control the reactive power
flow. Apart from this, the converter has multiphase boost in-
terfaces at both input and output ports. At the dc side, each
leg of the FB and the boost inductor connected to its switch
node form a boost phase unit. At the ac side, the dc bus is
formed by two series-connected capacitors. Each leg of the
ac side bridge along with its capacitive dc bus leg forms two
separate half-bridge inverter units. The inverter phase units are
connected to the load through the filter inductors Lf 1 and Lf 2 ,
respectively. The interleaved operation of the phase units at both
the input and output side reduces the input and output current
ripple. Thus, the filter capacitor requirement at both the input
and output can be minimized. Since the phase units share the
input and output currents, smaller inductors can be used for
current source interfacing at both the ports. Also, the interleaved
operation reduces the effective input and output inductance of
the system, which improves its dynamic response.
A. Operating Principle
The carrier and modulating signals for the gate pulse gener-
ation of both primary and secondary side devices are shown in
Fig. 3. The triangular carriers for the primary side boost phase
units are 180◦ phase-shifted from each other. They have peaks
at 0 and 1. They are compared with a reference signal mp given
as
1
mp = . (1)
2
The boost operation of these units is achieved by operating the
two switches in each unit in a complimentary manner. This way,
the two boost units charge the dc bus capacitor Cdcp to a voltage
of 2Vin , where Vin is the input dc voltage.
The steady-state operation of the converters can be easily
understood by replacing the switching network by an equivalent
voltage source. Assuming the dc bus voltage Vp fairly constant,
the switch node voltages vandc and vbndc can be represented by
a network with a dc voltage of Vin and a high-frequency square
wave ac voltage source of amplitude Vin connected in series.
The high-frequency sources being produced as a result of the
switching action are 180◦ phase-shifted with respect to each
other for each switch node voltages. The dc component in the
switch node voltages get canceled in the differential voltage
vab appearing across the transformer primary, whereas the 180◦
phase-shifted high-frequency components get added. Similarly,
the triangular carriers for each secondary side inverter units
are 180◦ phases shifted from each other. To synthesize an ac
output voltage, the modulating signal for both the inverter units
is selected as follows:
1 mac
ms = + (2)
2 2
 2640
Fig. 2. Circuit schematic of the proposed dc–ac DAB converter.
Fig. 3. Carrier and modulating signals for the gate pulse generation of primary
and secondary side devices.
where mac is the sinusoidal modulating signal given as
mac = M sin(ωl t)
where ωl is the angular line frequency and M is the amplitude
of the ac modulating signal.
The steady-state equivalent circuit is shown in Fig. 4. The
switch node voltages vcnac and vdnac are sine pulsewidth modu-
lated (PWM) voltages. Hence, they are represented by a network
comprising a line frequency voltage source and a switching
frequency square wave voltage source connected in series [26].
The line frequency components being produced as a result of the
sinusoidal modulation are in phase for both the switch node volt-
ages. Whereas, the high-frequency components being produced
due to the switching action are 180◦ phase-shifted from each
other due to the phase-shift in the carrier signals. The differential
voltage vcd contains the sum of the high-frequency components,
whereas the line frequency components get canceled. The power
transfer through the high frequency transformer is facilitated by
the phase-shift between the voltages vab and vcd .
III. SWITCHING ANALYSIS
Determination of the DAB inductor current at the switching
instants is useful for the ZVS analysis of the switches and
deriving the power transfer equation of the converter. In the
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 3, MAY/JUNE 2021
following section, analytical equations for various switching
instants and the DAB inductor current at those switching instants
are derived. In order to simplify the analysis, the following
assumptions are made.
1) The converter is operating under steady-state.
2) The primary and secondary dc bus voltages are ripple-free.
3) The phase-shift φ is constant during steady-state
operation.
4) The ac modulating signal mac is assumed to be constant
within a switching cycle.
The turn-ON instants of various switches within a switching
cycle over a line cycle can be shown as trajectories depicted in
Fig. 5. The y-axis shows a complete swing of the line cycle from
0 to N Ts . Here
Tl
N= (4)
Ts
(3)
where Tl is the time period of the ac modulating signal mac and
Ts is the switching time period.
The x-axis shows the time within a switching cycle ranging
from − T2s to T2s . Since the primary side modulation index mp is
a constant, the primary side switching instants are fixed within
a switching cycle. Hence, to reduce the complexity, the origin
of the x-axis is synchronized with the midpoint of the positive
half of the primary side bridge output.
The turn-ON time of any switch within the kth switching cycle
can be found by projecting the trajectory of that corresponding
switch at kth switching cycle on the x-axis. Since the switching
trajectory is similar for both the positive and negative half cycles
of mac , the analysis is carried out for the positive half cycle
only. The results for the negative half cycle is later found out
from the results obtained for the positive half cycle. A general
expression of turn-ON switching instants of various switches in
the kth switching cycle on the positive half cycle of mac can be
written as follows:
TS
tQ1 (k) = tQ4 (k) = −
4
TS
tQ3 (k) = tQ2 (k) =
4
 CHAMBAYIL AND CHATTOPADHYAY: DUAL ACTIVE BRIDGE CONVERTER WITH MULTIPHASE BOOST INTERFACES 2641

Fig. 4. Equivalent circuit of the proposed dc–ac converter.

 
TS
tQ8 (k) = − 1 − mac (kTs ) − p (5)
4
where p is a factor corresponding to the phase-shift between
primary and secondary side carrier signals and is given by
φ
p= . (6)
Ts /4
Depending on the relative value of p and |mac |, the sequence
of secondary side switching with respect to the primary side
switching within a switching cycle has two patterns. For mac >
p, the switching sequence within a switching half cycle is tQ1 →
tQ8 → tQ7 → tQ2 . And for mac < p, the switching sequence is
tQ1 → tQ5 → tQ8 → tQ2 . The relevant waveforms for the two
patterns are shown in Fig. 6. It can be seen that, for both patterns,
the DAB inductor current has three linear zones with different
slopes within a switching half cycle ranging from [− T4s , T4s ].
The time duration of these intervals is depicted as Δtm1 , Δtm2 ,
and Δtm3 for pattern-I and Δtp1 , Δtp2 , and Δtp3 for pattern-II.
1) Pattern I: The expression of these time intervals can be
calculated using the equations of the switching instants given in
(5). They are listed as follows:
Ts
Δtm1 (k) = tQ8 (k) − tQ1 (k) = (mac (kTs ) + p) (7)
4
Ts
Δtm2 (k) = tQ7 (k) − tQ8 (k) = (−2mac (kTs ) + 2) (8)
4
Ts
Δtm3 (k) = tQ3 (k) − tQ7 (k) = (mac (kTs ) − p). (9)
4
Using the straight line equation, the following relation holds
for the DAB inductor current at various switching instants for
the positive half cycle of mac :
Fig. 5. Trajectory of device turn-ON time of various devices within a switching nVp
cycle over a line cycle.
ILQ8+ (k) = ILQ1+ (k) + × Δtm1 (k) (10)
Ldab
nVp − Vs
ILQ7+ (k) = ILQ8+ (k) + × Δtm2 (k) (11)
  Ldab
TS
tQ5 (k) = − 1 + mac (kTs ) − p nVp
4 ILQ3+ (k) = ILQ7+ (k) + × Δtm3 (k). (12)
  Ldab
TS
tQ6 (k) = 1 + mac (kTs ) + p Also, due to the half-wave symmetry of the dab inductor current,
4
  we can write
TS
tQ7 (k) = 1 − mac (kTs ) + p ILQ1+ (k) = −ILQ3+ (k). (13)
4

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 2642 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 3, MAY/JUNE 2021

Fig. 6. Transformer secondary voltage, secondary bridge output voltage, voltage across dab inductor, and dab inductor current (a) for pattern-I (mac (t) > p)
and (b) for pattern-II (mac (t) ≤ p).

Solving the above equations, the dab inductor current at various 2) Pattern II: Similarly, for pattern-II, the time intervals
switching instants can be found as follows: Δtp1 (k), Δtp2 (k), and Δtp3 (k) are found using (5) as follows:
Ts
ILQ1+ (k) = −A + B(1 − mac (kTs )) (14) Δtp1 (k) = tQ5 (k) − tQ1 (k) = (−mac (kTs ) + p) (21)
4
ILQ8+ (k) = B(1 − mac (kTs )) + A(mac (kTs ) + p − 1) Ts
(15) Δtp2 (k) = tQ8 (k) − tQ5 (k) = (2mac (kTs )) (22)
4
ILQ7+ (k) = −B(1 − mac (kTs )) + A(−mac (kTs ) + p + 1) Ts
Δtp3 (k) = tQ3 (k) − tQ8 (k) = (2 − mac (kTs ) − p). (23)
(16) 4
ILQ3+ (k) = A − B(1 − mac (kTs )) (17) The dab inductor currents at various switching instants within a
switching half cycle is calculated. They are as follows:
where ILQ1+ (k) = −A + B(1 − p) (24)
nVp ILQ5+ (k) = B(1 − mac (kTs )) + A(p − mac (kTs ) − 1)
A= (18)
4Ldab (25)
Vs ILQ8+ (k) = B(1 − mac (kTs )) + A(mac (kTs ) + p + 1)
B= . (19)
4Ldab (26)

Due to the symmetry of the DAB inductor current in both the ILQ3+ (k) = A − B(1 − p). (27)
switching half cycles, the following relations hold:
N
In the negative half cycle of mac , k > . The DAB inductor
2
ILQ2+ (k) = −ILQ4+ (k) current in various switching instants in the negative half cycle
ILQ5+ (k) = −ILQ7+ (k) of mac can be found from the results obtained from the positive
half cycle as shown in the following:
ILQ8+ (k) = −ILQ6+ (k)  
N
ILQ1+ (k) = −ILQ3+ (k). (20) ILQ1− (k) = ILQ4+ k −
2

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 CHAMBAYIL AND CHATTOPADHYAY: DUAL ACTIVE BRIDGE CONVERTER WITH MULTIPHASE BOOST INTERFACES 2643

 
N
ILQ2− (k) = ILQ3+ k−
2
 
N
ILQ3− (k) = ILQ2+ k −
2
 
N
ILQ4− (k) = ILQ1+ k −
2
 
N
ILQ5− (k) = ILQ8+ k −
2
 
N Fig. 7. Region of integration for calculating average DAB inductor current.
ILQ6− (k) = ILQ7+ k −
2
 
N the DAB inductor current follows two patterns within the half-
ILQ7− (k) = ILQ6+ k − line cycle, the region of integration is divided into two regions:
2
  1) region where mac > p and 2) the region where mac < p. The
N angle at which mac = p is found as shown in the following:
ILQ8− (k) = ILQ5+ k − . (28)
2
p = M sin(δ) (32)
A. Power Transfer Equation
 p 
The power transferred through the DAB inductor can be =⇒ δ = sin−1 . (33)
calculated by finding the average power transferred in all the M
switching cycles within a half cycle of the line cycle. The power These regions are depicted in Fig. 7. Now, the average power
transferred in a switching cycle can be calculated by taking over a half-line cycle is calculated as shown in the following:
the product of the average value of DAB inductor current and  δ
the average value of the transformer secondary voltage in a 1 Ts VS (2p − M 2 sin2 (ωl t) − p2 )
Pavg = nVp × d(ωl t)
switching half cycle. π 0 8Ldab
The transformer secondary voltage is a square wave, the  π−δ
Ts VS p(1 − M sin(ωl t))
average voltage is given as follows: + d(ωl t)
δ 4Ldab
vts(avg) = nVp . (29)  π 
Ts VS (2p − M 2 sin2 (ωl t) − p2 )
The average value of DAB inductor current in a switching half + d(ωl t)
π−δ 8Ldab
cycle can be derived from the instantaneous values of DAB
inductor current at switching instants derived in (14)–(17) and nVP VS TS
Pavg =
(24)–(27). For pattern-I, the average value of DAB inductor 4πLdab
 
current in a switching half cycle can be calculated as follows:
 M2 M2
1 1 πp + sin(2δ) − δ − δp − 2M pcos(δ) .
2

i+ (k) = × (ILQ8+ (k) − ILQ1+ (k)) 4 2

dab(avg)_pI Ts /2 2 (34)
1
× Δt1 m (k) + (ILQ7+ (k) − ILQ8+ (k)) × Δt2 m (k)
2 B. RMS Value of DAB Inductor Current

1 The rms value of dab inductor current can be calculated from
+ (ILQ2+ (k) − ILQ7+ (k)) × Δt3 m (k)
2 the instantaneous values of dab inductor current at switching
instants derived in (14)–(17) and (24)–(27). For pattern-I, ex-
Ts Vs p(1 − mac (kTs ))
= . (30) pression of the rms value of dab inductor current over a switching
4Ldab cycle can be found as given in the following:
Similarly, for pattern-II, the average value of dab inductor cur-   tQ7
tQ8
rent over a switching half cycle is given as follows: 1
idab(rms_pI) (k) = i2dab dt + i2dab dt
Ts Vs (2p − mac (kTs )2 − p2 ) TS /2 tQ1 tQ8
i+
dab(avg)_pII (k) = . (31)
8Ldab
 1
Since Ts << Tl , the equation of average dab inductor current in tQ2 2
a switching cycle given in (30) and (31) can be assumed to be a + i2dab dt . (35)
tQ7
continuous function of time. Hence, the average DAB inductor
current over a half-line cycle can be calculated by integrating the The expression of DAB inductor current for each of these
average DAB inductor current equation in a switching half cycle duration is given in Table I. Substituting in (35), the rms value
throughout a half-line cycle and finding the average of it. Since of dab inductor current in a switching cycle for the pattern-I is

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 2644 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 3, MAY/JUNE 2021

TABLE I cycle given in (36) and (38) as shown in the following:

DAB INDUCTOR CURRENT EQUATION FOR VARIOUS TIME DURATIONS WITHIN
A SWITCHING HALF CYCLE FOR PATTERN-I
N

2  2
 2
idab(rms) = idab(rms_Ts ) (k) (39)
N Ts
k=1

where idab(rms_Ts ) (k) is given as


idab(rms_pI) (k), for mac (kTs ) > p
idab(ms_Ts ) (k) = .
idab(rms_pII) (k), for mac (kTs ) < p
TABLE II
DAB INDUCTOR CURRENT EQUATION FOR VARIOUS TIME DURATIONS WITHIN IV. FUNDAMENTAL FREQUENCY ANALYSIS
A SWITCHING HALF CYCLE FOR PATTERN-II
The primary bridge output is a square wave with peaks at
Vp and −Vp . The fundamental frequency component of this
waveform can be represented as follows:
vab1 (t) = E1 cos(ωs t)) (40)
where amplitude E1 is given by
4Vp
E1 = . (41)
π
obtained as follows: The secondary switch node voltages vco and vdo are sinusoidal
 
Ts2 PWM waveforms. The harmonic components of a sinusoidal
idab(rms_pI) (k) = × (nVP )2 − nVP VS [mac (kTs )3 PWM waveform can be found out using the method described
48L2dab
in [26]. Then, the switch node voltage vco can be represented as
− 3mac (kTs )2 + 3mac (kTs )p2 − 3p2 + 2] vco (t) = Vs + Vs M cos(ωl t)
1
 4Vs  1  π   π
∞
2 + J0 ks M sin ks cos(ks ωs t)
+ VS2 2m3ac (kTs ) − 3mac (kTs ) + 1 2
. π ks
ks =1
2 2

(36) ∞ ∞
4Vs   1  π   π
+ Jn ks M sin ks
Similarly, for pattern-II, the expression of the rms value of DAB π k
n =−∞ s
2 2
ks =1 l

inductor current over a switching cycle can be found as follows:

× cos(ks ωs t + nl [ωl t + θo ]) (42)
 
1 tQ8 tQ5 where Jo is the Bessel function of the first kind of order zero.
idab(rms_pII) (k) = i2dab dt + i2dab dt To reduce the complexity of the analysis, the higher order har-
TS /2 tQ1 tQ8
monics of both the line frequency and the switching frequency
 1 components and side band harmonic components can be ignored.
tQ2 2 Then, the switch node voltage vco can be written as follows:
+ i2dab dt . (37)
tQ8 Vs Vs 2Vs  π 
vco (t) = + M cos(ωl t) + J0 M cos(ωs t − φ).
2 2 π 2
The DAB inductor current equation for each of these duration (43)
is given in Table II. Similarly, vdo can be written as follows:

 Vs Vs
 vdo (t) = + M cos(ωl t)
Ts2 2 2
idab(rms_pII) (k) = × (nVP )2 − nVP VS [p3 − 3p2
48L2dab 2Vs  π 
+ J0 M cos(ωs t − φ − π). (44)
π 2
+ 3mac (kTs )2 p − 3mac (kTs )2 + 2]
The bridge output voltage vcd can be written as follows:
1
 vcd (t) = vco (t) − vdo (t) = E2 cos(ωs t − φ) (45)
2
+ VS2 2m3ac (kTs ) − 3mac (kTs )2 + 1 . (38)
4Vs π
where E2 = J0 ( M ).
π 2
The rms value of the DAB inductor current can be calculated The simplified circuit showing power transfer across DAB
from the rms value of DAB inductor current for a switching inductor is shown in Fig. 8. The DAB inductor current can be

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 CHAMBAYIL AND CHATTOPADHYAY: DUAL ACTIVE BRIDGE CONVERTER WITH MULTIPHASE BOOST INTERFACES 2645

The lower device rms current equation can be approximated as


2
Iin (n × idab(rms) )2
Ipri(rms)bot ≈ + . (51)
4 2
In the secondary side, the current entering the switch node
consists of the low-frequency load current and high-frequency
DAB current. From the operating principle of the converter, at
any point in time, one of the devices of each leg has to conduct
(ignoring the dead time). Unlike the primary side, there is no
dc component in the currents entering the secondary side switch
nodes. Hence, on an average, each switch carries half of the
Fig. 8. Power transfer across DAB inductor. load current and the DAB current. The device rms current for the
secondary side devices can be approximated using the following
formula:
written as follows: 
i2ac(rms) (n × idab(rms) )2
idab (t) = Idab_s1 cos(ωs t + δ) (46) Isec(rms) ≈ + . (52)
2 2
where
 VI. ZVS ANALYSIS
E12 + E22 − 2E1 E2 cos(φ)
Idab_s1 = (47) For ZVS operation of a device, it is necessary that the device
ωs Ldab current (for an N-channel MOSFET, the device current polarity is
 
−1 Vs J0 considered positive, when the current direction is from the Drain
δ = tan . (48)
nVp terminal to the Source terminal of the device) polarity is negative
before the turn-ON gate pulse is applied so that this current can
Therefore, the rms value of the fundamental frequency compo- discharge the drain-to-source capacitance first and subsequently
nent is conduct through the body diode during the dead-time period.
Idab_s1 The necessary conditions for ZVS of various devices are shown
Idab_rms = √ . (49) in Fig. 9.
2
The primary side device currents are the sum of the trans-
former current and boost inductor current. The transformer pri-
V. DEVICE RMS CURRENT ESTIMATION
mary current can be calculated by multiplying the DAB current
A method to estimate the device rms currents is explained by the turns ratio of the transformer. The input current is assumed
here. From Fig. 2 and the operating principle of the con- to be a constant dc current for the ZVS analysis.
verter, it can be concluded that at any time during the op- The instantaneous value of the boost inductor current at the
eration of the converter (ignoring the dead time), two diago- turn-ON of the upper and lower devices can be found out from
nal switches of the primary side bridge conduct. The current Fig. 10. The ripple current ΔIbst can be written as follows:
entering the switch nodes consists of the boost inductor current
Vin
and the transformer primary current. Ignoring the ripple cur- ΔIbst = Ts (53)
rents in the boost inductors, the boost inductor currents can be 8Lbst
assumed to be essentially dc in nature. Since the currents through where Lbst = Lbst1 = Lbst2 .
the devices Q1 and Q3 must flow through the dc bus capacitor The boost inductor currents at turn-ON of the upper devices
Cdcp under steady-state, they cannot be dc in nature. Hence, can be written as
the upper devices carry only the high-frequency transformer Iin Vin
current. Whereas, the lower devices Q2 and Q4 carry both the ibst_Q1 = ibst_Q3 = + Ts . (54)
2 8Lbst
boost inductor current and the transformer current. Since all the
devices are operated at 50% duty ratio, the transformer current Similarly, the boost inductor currents at turn-ON of the lower
is shared equally between the two pairs of diagonal switches. devices can be written as
From Fig. 2, it can be seen that the dc component of the boost Iin Vin
ibst_Q2 = ibst_Q4 = − Ts . (55)
inductor current is equal to half of the input dc current. Hence, 2 8Lbst
the rms value of the current carried by the upper devices can be These values are substituted in the ZVS conditions for the
written as primary devices shown in Fig. 9 and are shown in Table III.
itp(rms) The secondary side device currents are the sum of DAB
Ipri(rms)top ≈ √ inductor current and filter inductor current. Each filter inductor
2
current consists of half of the load current and a switching
n × idab(rms)
≈ √ . (50) frequency ripple. The filter inductor current at the switching
2 instants of its corresponding leg devices can be approximated

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 2646 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 3, MAY/JUNE 2021

Fig. 9. ZVS conditions of the devices.

Fig. 10. Boost inductor current waveform.

TABLE III Fig. 11. Filter inductor current waveform.

ZVS CONDITIONS FOR PRIMARY SIDE DEVICES

TABLE IV
ZVS CONDITIONS FOR SECONDARY SIDE DEVICES

by assuming the low-frequency load current component to be

constant within a switching interval. Fig. 11 shows the filter
inductor current iLf 1 and the voltage across the filter inductor
Lf 1 . The value of iLf 1 at the turn-ON of the top devices Q5 and
Q7 can be approximated as follows:
And the instantaneous value of filter inductor current at the turn-
ON of the bottom devices can be approximated as
iac
iLf 1 _Q5 = iLf 1 _Q7 = − ΔiLf 1 (56)
2
iac
iLf 1 _Q6 = iLf 1 _Q8 = + ΔiLf 1 . (58)
where the ripple current ΔiLf 1 is given by 2

1 Vs
− vac These values are substituted in the ZVS conditions for the
ΔiLf 1 = × 2
ms T s . (57)
2 Lf 1 secondary devices shown in Fig. 9 and are shown in Table IV.

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 CHAMBAYIL AND CHATTOPADHYAY: DUAL ACTIVE BRIDGE CONVERTER WITH MULTIPHASE BOOST INTERFACES 2647

where Cdcs1 = Cdcs2 = Cdcs . The current iaclf is given by

vac
iaclf = = IL sin(ωl t −  − ψ) (62)
ZL
where vac is the load voltage given by
vac = Vm sin(ωl t − ) (63)
and ZL = |ZL |∠ψ is the load impedance and  is the phase-shift
of the load voltage with respect to the ac modulating signal. IL
can be written as
Vm
IL = . (64)
|ZL |
Substituting in (61), the voltage vc_ac can be found as follows:
IL
vc_ac = − cos(ωl t −  − ψ). (65)
2ωl Cdcs
Fig. 12. AC side of the converter. Now, (59) and (60) can be rewritten as follows:
Vs IL
vdcs1 = + cos(ωl t −  − ψ) (66)
2 2ωl Cdcs
VII. DESIGN AND IMPLEMENTATION
The converter specifications are given in Table IV. One of Vs IL
vdcs2 = − cos(ωl t −  − ψ). (67)
the main objectives of designing a DAB converter is to re- 2 2ωl Cdcs
duce the reactive power transferred through the high-frequency From Fig. 12, vaclf can be written as
transformer to reduce the associated conduction losses. The
vaclf = vac + vlf (68)
magnitude of DAB inductor current depends on both the primary
side and secondary side dc bus voltages, DAB inductance, and where vaclf is the inverter output voltage and can be written as
transformer turns ratio. The primary dc bus voltage is decided follows:
by the source voltage. But the secondary dc bus voltage has to
vaclf = vdo − vdcs2 . (69)
be selected to generate the specified output voltage at all loading
conditions. The secondary dc bus requirement calculation is The switch node voltage vdo can be written in terms of the dc
explained in detail in the following section. bus voltage and secondary modulating signal ms as follows:
 
1 M
vdo = + sin(ωl t) × Vs . (70)
A. Secondary DC Bus Voltage Calculation 2 2
The secondary side of the converter is shown in Fig. 12. In this From (67) and (70), vaclf can be written as follows:
figure, vaclf is the line frequency component of the voltage vdnac  
M
and iaclf is the line frequency component of the line current iac . vaclf = sin(ωl t) × Vs − vc_ac . (71)
2
The voltage ripple produced by the high frequency component of
the line current is not substantial. The iaclf current splits equally The voltage drop vlf across the filter inductor is insignificant
at the neutral point nac and flows through the capacitors Cdcs1 and can be ignored. Hence, from (68) and (71)
and Cdcs2 . This line frequency current creates line frequency M Vs IL
voltage ripple in the dc bus capacitor voltages vdcs1 and vdcs2 . vac = sin(ωl t) + cos(ωl t −  − ψ)
2 2ωl Cdcs
These voltages can be written as follows:
M Vs IL
Vm sin(ωl t − ) = sinωl t + cos(ωl t −  − ψ).
Vs 2 2ωl Cdcs
vdcs1 = − vc_ac (59) (72)
2
Solving (72), the following relations are obtained:
Vs   2 1/2
vdcs2 = + vc_ac (60) 2 Vm IL sin(ψ) IL
2 Vs = Vm2 − + (73)
M ωl Cdcs 2ωl Cdcs
 
where vc_ac is the line frequency voltage ripple in the dc bus IL cos(ψ)
capacitors. Since the current direction is opposite to each other  = −tan−1 . (74)
2Vm ωl Cdcs − IL sin(ψ)
in the capacitors, these voltage ripples are 180◦ phase-shifted.
Now, the minimum dc bus voltage required to satisfy the
vc_ac can be written as follows
converter specification described in Table IV can be calculated
 using (73). It is found out to be
1 iaclf
vc_ac = dt (61)
Cdcs 2 Vs = 778 V.

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 2648 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 3, MAY/JUNE 2021

TABLE V
CONVERTER ELECTRICAL PARAMETERS

TABLE VI
COMPONENT SPECIFICATION

Fig. 13. RMS current of various devices.

B. High-Frequency Transformer Design and DAB Inductor

The high-frequency transformer turns ratio is selected to keep
the conduction loss in the primary and the secondary side devices
minimum. The conduction loss in the devices can be calculated
using the device rms current calculated in (50)–(52). The device
RMS current distribution is shown in Fig. 13. The primary side
device conduction loss is given as
pswcnd(pri) = 2Ipri(rms)
2
top
Rdson(pri) + 2Ipri(rms)
2
bot
Rdson(pri). (75)
The secondary side device conduction loss is given as
pswcnd(sec) = 4Isec(rms)
2
Rdson(sec) (76)
where Rdson_pri and Rdson_sec are the primary and secondary side
device ON-resistance, respectively.
From (34), the DAB inductance can be written as follows:
n×K
Ldab = (77)
Pavg
where n is the turns ratio and K is a constant given by Fig. 14. (a) Switch conduction loss versus transformer turns ratio. (b) [DAB
  inductance, rms value of DAB inductor current, turn-ON current of primary side
bottom device] versus transformer turns ratio.
VP VS TS M2 M2
K= πp + sin(2δ) − δ−δp2 − 2M pcos(δ) .
4π 4 2
Fig. 13(b). From the figure, it can be found that the conduction
Now, the DAB inductance can be plotted as a function of turns
loss is minimum around a turns ratio of 3. Also the turn-ON
ratio. The rms value of the DAB inductor current is calculated
current iton(Q2) is negative for this value, which satisfies the ZVS
using (39). The total conduction loss in the devices can be
operation of the primary side devices. Hence, the turns ratio of
calculated from (75) and (76) as follows:
3 is selected and the corresponding DAB inductance is found
pswcnd(tot) = pswcnd(pri) + pswcnd(sec) . (78) out to be 132 μH. Based on the above design procedure, a 3-kW
converter prototype is designed. The converter parameters are
Fig. 13(a) shows the plot of pswcnd(tot) versus the transformer
shown in Table V. The high-frequency transformer design details
turns ratio. From the ZVS conditions of the devices shown in
are shown in Table VI. The winding and core configurations are
Table III, it is found that the primary side bridge bottom devices
shown in Fig. 14.
are more prone to non-ZVS operation near the zero crossing
of mac . The turn-ON current of the primary side bottom device
C. ZVS Regions
iton(Q2) is calculated for mac = 0 and plotted as a function of
transformer turns ratio. The plots of DAB inductance Ldab , The ZVS regions are calculated for the devices for specifica-
idab(rms) , and iton(Q2) as a function of turns ratio are shown in tions mentioned in Tables V and VIII and using the equations

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 CHAMBAYIL AND CHATTOPADHYAY: DUAL ACTIVE BRIDGE CONVERTER WITH MULTIPHASE BOOST INTERFACES
TABLE VII
TRANSFORMER DESIGN DETAILS
Fig. 15. Transformer winding and core configuration.
Fig. 16. Trajectory of turn-ON instant currents of primary side top devices over
a line cycle for various operating power conditions.
described in Tables III and VII. The turn-ON currents of the
primary side, top and bottom devices for the complete cycle
of the ac modulating signal mac , for various operating power
conditions are plotted in Figs. 16 and 17, respectively. It can be
seen that the turn-ON currents of all the primary side devices are
negative throughout the complete line cycle of mac at the rated
power of 3000 W. Hence, at rated power, these devices operate
in ZVS throughout the line cycle. The turn-ON currents of the
secondary side devices for a complete cycle of the ac modulating
signal mac for various operating power conditions are plotted in
Figs. 18 and 19, respectively. It can be seen that, at rated power,
around 70% of the positive half cycle of the load current, the top
devices lose ZVS. For the bottom devices, a similar non-ZVS
zone occurs in the negative half cycle.
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2649
Fig. 17. Trajectory of turn-ON instant currents of primary side bottom devices
over a line cycle for various operating power conditions.
Fig. 18. Trajectory of turn-ON instant currents of secondary side top devices
over a line cycle for various operating power conditions.
Fig. 19. Trajectory of turn-ON instant currents of secondary side bottom
devices over a line cycle for various operating power conditions.
VIII. CONTROL
The main control parameters of the converter are the phase-
shift φ and the secondary side modulating signal ms . The control
scheme is shown in Fig. 20. The power transfer between the
primary and secondary bridges is controlled by the phase-shift
φ. The main objective of phase-shift control is to regulate the
secondary dc bus voltage at its reference value. The output power
being of single-phase ac nature contains second harmonic com-
ponents. Any strict control effort of the secondary dc bus voltage
may henceforth force the converter to extract second-harmonic
power from the primary side dc bus. This is undesirable since the
 2650
Fig. 20. Overall control architecture of the proposed dc–ac converter.
second harmonic ripple in the primary side dc bus voltage will
result in the same harmonic components in the input current.
Hence, the secondary dc bus voltage control consists of an outer
dc bus voltage control and an inner input current control. Both
the controllers are of proportional–integral (PI) type. The outer
dc bus control being a slow controller derives an essentially dc
input current reference. This current reference Iin∗ is compared
with the actual input current. The error is processed using a
faster PI controller to derive the phase-shift component φdc .
The closed-loop controller adjusts φdc so as to keep the input
current constant and regulates the secondary dc bus voltage at its
reference value. Apart from this, an “input current low frequency
ripple controller” is used to further control the low frequency
ripples in the input current. The input current is compared with
zero reference and the error is passed through a multiresonant
controller tuned to second and fourth harmonic line frequency
to derive the phase-shift component φac . It is added to the
phase-shift component φdc derived from the secondary dc bus
voltage controller to generate the combined phase-shift φ.
The secondary side modulating signal ms is derived based on
the mode of operation of the converter. In the stand-alone mode,
the converter is connected to an ac load. In order to regulate the
output ac voltage, the controller consists of an outer ac voltage
control loop and an inner proportional multiresonant controller-
based current control loop. The sensed ac voltage is multiplied
with a unit sine wave. The product has an average value equal
to half of the ac voltage peak. This is compared with a reference
equal to half of the peak of the required output ac voltage. The
error is processed through a PI controller to generate the ac
current peak reference. This reference signal is passed through
a limiter block. The limits are set to keep the ac current within the
safe limit. For forward power flow, the current limit is positive,
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 3, MAY/JUNE 2021
and for reverse power flow, the current limit is negative. The
output from the limiter block is multiplied with the unit sine wave
to generate the ac current reference. The reference current is
compared with the actual load current and the error is processed
through a proportional multiresonant controller to get the ac
modulating signal mac . By adding 21 to mac , the secondary side
modulating signal ms is obtained. The multiresonant controller
is tuned to the fundamental and the third harmonic line frequency
to attenuate the third harmonic components in the ac current.
In grid-connected mode, the limit for the current limiter is
∗
decided from the power reference Pref . For forward power flow,
∗
Pref is positive, and for reverse power flow, it is negative. Since
power is injected into the grid at unity power factor, the current
reference is calculated by dividing the power reference by the
rms value of the grid voltage. √The peak current reference is
calculated by multiplying it by 2. The peak current reference
is set as the current reference limit in the limiter block. Since the
ac output voltage is decided by the grid, the outer voltage loop is
allowed to saturate by setting the voltage reference appropriately.
For forward power flow, the voltage reference is set higher than
the grid voltage peak. Hence, the voltage controller saturates
and the current reference is decided by the positive limit of the
limiter block. For reverse power flow, the ac voltage reference is
set less than the grid voltage peak. Hence, the voltage controller
saturates to the negative limit of the current limiter.
The unit sine wave signal is generated using a phase locked
loop (PLL). The sensed load voltage vac and the grid voltage
vgrid are inputs to the PLL. In the stand-alone mode, the static
transfer switch str is kept open and vac is used as the reference
for unit sine-wave generation. While in grid-connected mode,
the static transfer switch str is closed. Since vgrid is now equal to
vac , the PLL generates a sine signal synchronized with the grid
 CHAMBAYIL AND CHATTOPADHYAY: DUAL ACTIVE BRIDGE CONVERTER WITH MULTIPHASE BOOST INTERFACES 2651

Fig. 21. Photograph of the converter prototype.

TABLE VIII Fig. 22. Efficiency from experimental results.

TEST CONDITION

voltage. When the converter is operating in the stand-alone mode

and the grid has come back (str is still open), the PLL varies its
frequency and phase to synchronize itself to the grid frequency
and phase. At the specific instant when these are matched, the
PLL sends a control signal to turn-ON the switch str to transition Fig. 23. Output voltage, output current, and secondary dc bus voltage.
into grid-connected mode. The modulating signal ms and the
phase-shift φ derived by the controllers are given to the gate pulse
generation block to generate the gate pulses for the secondary
side devices.

IX. EXPERIMENTAL RESULTS

The photo of the hardware prototype is shown in Fig. 21. The
specifications of the main components used are listed in Table V.
The converter is designed to interface a 70-V dc system with a
230-V ac system. The switching frequency is 50 kHz. The gate
pulse generation and control are implemented using XC3S400
field programmable gate array (FPGA)-based control board.
The experimental results are taken in the stand-alone mode of Fig. 24. Filter inductor currents.
operation with operating parameters specified in Table VIII. The
steady-state waveforms are captured using the digital oscillo-
scope Lecroy Waverunner 6050 A. The efficiency plot based on
experimental results is shown in Fig. 22.
The output voltage, output current, and the secondary dc
bus voltage are shown in Fig. 23. The characteristic second-
harmonic power due to the single-phase ac load is reflected
as second-harmonic ripple in the secondary dc bus voltage.
The load being resistive, the voltage and current are in phase.
The filter inductor currents are shown in Fig. 24. The high-
frequency ripples are 180◦ phase-shifted for both the filter
inductor currents. The transformer secondary voltage, the DAB
inductor current, and the secondary bridge output voltage are Fig. 25. Transformer secondary voltage, DAB inductor current, and secondary
shown in Figs. 25 and 26. Fig. 25 shows the waveforms near bridge output voltage (near zero crossing of mac ).

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 2652
Fig. 26. Transformer secondary voltage, DAB inductor current, and secondary
bridge output voltage (near peak of mac ).
Fig. 27. Boost inductor currents.
Fig. 28. Primary input voltage, primary dc bus voltage, and input current.
the zero-crossing of the ac modulating signal, while Fig. 26
shows the waveform near the peak of the ac modulating signal.
The boost inductor currents are shown in Fig. 27. Due to the
interleaved operation of the input boost phase units, the boost
inductor current ripples are 180◦ phase-shifted from each other.
The input voltage, input current, and primary dc bus voltage are
shown in Fig. 28.
X. CONCLUSION
In this article, a DAB converter with multiphase boost in-
terfaces for dc–ac bidirectional conversion applications is pro-
posed. The single-stage conversion is accomplished using only
eight devices. The converter is suitable for medium power appli-
cations such as solar PV integration and electric vehicle battery
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 3, MAY/JUNE 2021
charging. The novel modulation strategy employed utilizes both
low-frequency and high-frequency components in the inverter
PWM voltage. The low-frequency component is used to shape
the output current, while the high-frequency component is used
for power transfer. The detailed design guideline is provided to
achieve ZVS of the primary side devices. Most of the secondary
side switching transitions are ZVS, though, depending on the
load current, for some duration in the positive half cycle of the
load current, the top devices lose ZVS. Whereas, the bottom
devices lose ZVS for the same duration of time in the negative
half cycle. The floating nature of the dc buses at both primary
and secondary sides makes the converter suitable for cascading.
Hence, multiple units of the converter can be cascaded for
high-power dc–ac applications such as data center power supply.
A detailed study of cascaded operation will be discussed in
future work. The multiphase boost interfaces at both the ports
reduce the input and output current ripples and, hence, eliminate
the filter capacitor requirements. Experimental results taken at
1200 W from a hardware prototype verify the feasibility of the
topology.
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[20] N. Kummari, S. Chakraborty, and S. Chattopadhyay, “An isolated high-
frequency link microinverter operated with secondary-side modulation for
efficiency improvement,” IEEE Trans. Power Electron., vol. 33, no. 3,
pp. 2187–2200, Mar. 2018.
[21] F. Jauch and J. Biela, “Single-phase single-stage bidirectional isolated
ZVS ac-dc converter with PFC,” in Proc. 15th Int. Power Electron. Motion
Souvik Chattopadhyay (Member, IEEE) received
Control Conf., 2012, pp. LS5d.1-1–LS5d.1-8.
the B.E. degree from the Bengal Engineering College,
[22] J. Everts, F. Krismer, J. Van den Keybus, J. Driesen, and J. W. Kolar, “Op- Howrah, India, in 1988, and the M.Sc. and Ph.D. de-
timal ZVS modulation of single-phase single-stage bidirectional dab ac-dc
grees from the Indian Institute of Science, Bangalore,
converters,” IEEE Trans. Power Electron., vol. 29, no. 8, pp. 3954–3970,
India, in 1990 and 2002, respectively, all in electrical
Aug. 2014.
engineering.
[23] S. Chakraborty and S. Chattopadhyay, “A dual-active-bridge-based novel He is currently an Assistant Professor with the
single-stage low device count dc-ac converter,” IEEE Trans. Power Elec-
Department of Electrical Engineering, IIT Kharag-
tron., vol. 34, no. 3, pp. 2339–2354, Mar. 2019.
pur, Kharagpur, India. From 1991 to 1995, he was
[24] F. M. Ibanez, “Bidirectional series resonant dc/ac converter for energy stor-
with the Crompton Greaves, Ltd., Bombay, India,
age systems,” IEEE Trans. Power Electron., vol. 34, no. 4, pp. 3429–3444,
and from 1996 to 1998, he was with Cegelec India,
Apr. 2019.
Ltd., Noida, India. From 2002 to 2003, he was an Assistant Professor with
[25] A. Gertsman and S. Ben-Yaakov, “Zeroing transformer’s dc current in
the Department of Electronics Engineering, Jalpaiguri Government Engineering
resonant converters with no series capacitors,” in Proc. IEEE Energy College, Jalpaiguri, India. From 2003 to 2004, he was an Assistant Professor
Convers. Congr. Expo., 2010, pp. 4028–4034.
with the Department of Electrical Engineering, IIT Madras, Chennai, India.
[26] D. Holmes and T. Lipo, Pulse Width Modulation for Power Converters:
His research interests include design, analysis, control, and modeling of power
Principles and Practice, (IEEE Press Series on Power Engineering).
converters.
Hoboken, NJ, USA: Wiley, 2003.

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