Proceedings of the International Conference on Edge Computing and Applications (ICECAA 2022)
IEEE Xplore Part Number: CFP22BV8-ART; ISBN: 978-1-6654-8232-5
Analysis of UART Communication Protocol
Pranjal sharma
2022 International Conference on Edge Computing and Applications (ICECAA) | 978-1-6654-8232-5/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICECAA55415.2022.9936199
Department of ECE
Ajay kumar garg engineering college Ajay kumar garg engineering college
Ghaziabad, india
Pranjalsharma4698@gmail.com
Abstract— Universal Asynchronous Receiver Transmitter
(UART) communication protocol is developed for transmitting
inputs between computer hardware devices. The main goal of
Universal Asynchronous Receiver Transmitter (UART)
communication protocol is to provide consistent and high-quality
results. The proposed framework integrates with clock signal to
generate frequency values with the concerned system statement.
It eliminates the functional element that pretends selecting the
baud rate value and defined structural elements. The proposed
system has recognized a defined aspect of eventual attributes,
which may indulge upon many processed sources. It has evolved
through distinct accomplishment of resultant value to calculate
the system function by utilizing the terms and values of eventual
attributes. It may be processed to operate on the system while
ensuring inter-dependence. This has been performed via
transmitter and receiver terminals that propagate the val ue of
the defined resource statement function. It extends the system
function by leveraging distinct outcomes. This approach can
generate effective and quality resultant value to ensure the
defined functional statements. The transmission of source and
destination information may be beneficial for maintaining a
system with a predicted value, which will be generated based on
the defined system sources and determinants.
Keywords— Universal Asynchronous Receiver Transmitter
(UART), Baud rate, Clock signal, transmitting end, receiver end
and Verilog.
I. INT RODUCT ION
In general, Universal Asynchronous Receiver Transmitter
(UART) communication protocol is defined as a hardware
type of communication protocol. This protocol is evolved in a
asynchronous serial aspect as depicted in Fig.1.1. The system
evolves with configurable approach with no clock signal
evolved among concern system approach. It has transmitting
end, which transfer its value towards receiver end with
interfacing node [1].
There are two signals namely transmitting signal at source
node and receiving signal at destination node. The
development of this serial data transmission mechanism is
necessary for the computer hardware systems. An
interconnection process has been carried out by wires to
demonstrate the system activities and generate effective
function. The block diagram of Universal Asynchronous
Receiver Transmitter (UART) communication protocol is
depicted below.
978-1-6654-8232-5/22/$31.00 ©2022 IEEE
Authorized licensed use limited to: Nirma University Institute of Technology. Downloaded on January 04,2024 at 03:40:49 UTC from IEEE Xplore. Restrictions apply.
Anup kumar Naresh kumar
Department of ECE Department of ECE
Ajay kumar garg engineering college
Ghaziabad, india Ghaziabad, india
anupkumar@akgec.ac.in nareshkumar@akgec.ac.in
The features of Universal Asynchronous Receiver Transmitter
(UART) are evolved with various advantages. This may be
sustained to reach the values of various confinement models in
order to act accordingly with distinct result statements. It acts
as a clock generator to accomplish an effective and valid
utilization of system value with respective attributes. This may
act accordingly with the signal obtained from transmitter and
receiver end in the system propagation approach.
Fig.1.1. Universal Asynchronous Receiver Transmitter (UART) Se rial
Transmission process [2]
It usually acts to retain the knowledge value of certain stages
of eventual approaches to constraint through valid
deterministic values. It may reside to calculate the function in
the frequency range to define the distinct attributes. The
protocol act as an input and output register to recognize its
state value through distributive structural information
attributes. It may retain knowledge value of concern control
state function with register by their discrete value towards
valid statement. This could ensure predominant value to
feature certain system statement with valid enrolment
activities to consolidate clock signal and results. For a
legitimate outcome aspect, this also incorporates the auto band
system, which transmits and receives based on buffer
statement techniques.
The function of UART communication protocol describes the
individual entity. It regulates the systematic functional value
with a deterministic attribute to sort the quality result value by
defined resources. The system enumerates its value with
accomplishment of valid data and result statement. It has
possibility to convert parallel to serial data for outbound
323
 Proceedings of the International Conference on Edge Computing and Applications (ICECAA 2022)
IEEE Xplore Part Number: CFP22BV8-ART; ISBN: 978-1-6654-8232-5
approaches to undergo communication process. The function
process through serial into parallel incoming communication
aspect is used for clarity and results [3]. This could develop a
difference between two modes of functional values with the
sustained elements. The additional feature of parity checker
which may able to propagate its value retained and shows up
their defined categorization of concern system values. The
utilization of Universal Asynchronous Receiver Transmitter
(UART) communication protocol could lead with distinct
approach to evaluate with deterministic features [4]. It evolves
by duplex data transmission approaches which in part
recognize activity of system through two ways of
communication approach. It doesn’t consider power lines were
two wires from external source is required to act upon system
with defined values and aspects.
Fig.1.2. Functions of Universal Asynchronous Receiver Transmitter
(UART) communication protocol [5]
This system doesn’t require any clock signal to generate value
for certain stages of eventual activities taken part. It undergoes
a basic error detection system which could define an
occurrence of risk aspect raised among system resource
statement aspect.
However, system has effective resource which may evolve
among system attributes. This could lead with limitation
statement value for act according to impact raised upon
system values.
The system evolves with improper dimension which does not
suit for frame. It regulates value of eventual aspect with
regulative factor which may lead to enroll with structural
functional elements.
The speed of data communication activity is lower towards
their speed when compared with other approaches sustained
Fig.1.2. It relates with defined sources to proceed with
effective accomplishment of values. The transmitter and
receiver value can be selected for input range of system value
but it requires baud rate for valid accomplishment of distinct
result statement values. It may able to ensure effective activity
978-1-6654-8232-5/22/$31.00 ©2022 IEEE
Authorized licensed use limited to: Nirma University Institute of Technology. Downloaded on January 04,2024 at 03:40:49 UTC from IEEE Xplore. Restrictions apply.
of system value with certain error raised in between system
function. It may able to project with modification or
optimization required for deterministic system functional
values and results.
The application of Universal Asynchronous Receiver
Transmitter (UART) communication protocol evolves such as
communication with computers of far distance of 900 meters.
It evolves distinct resultant value which may able to act
according to its result through effective approaches.
The success of data transfer of system variables using a serial
port. It generates system data factor to reside over effective
and quality accomplishment of desired values. It results with
predominant role of resultant data values and system
functions. The selection of baud rate could confess with
distinct transmission of speed. These approaches of
developing microcontroller value to console with wireless data
communication.
II. LIT ERAT URE REVIEW
A verification of the global asynchronous receiver
transmitter communication protocol is shown by Yamini et al.
in [6]. Its article's primary goal is to use software simulation to
develop and deploy a full-duplex UART module (SV). It is a
serial communication protocol that allows devices to
communicate without the need for a clock cycle. It sends
digital signals that have been converted to serialized mode.
Input that would be acquired in serial format is transformed to
input and output. The baud rate generator, receiver,
transmitter, interruption, and FIFO elements are all designed
as part of the UART design process. Confirmation entails
checking its concept via establishing a regulatory framework
that permits simulation reuse and lowers code development.
To test the difficult-to-reach corner situations, randomization
was applied. Employing computer applications the design is
modeled by Questasim. Both the assessor graph and the
technical breadth are entirely covered.
Data transmission between Internet of Things (IoT) devices or
the involvement of various gadgets has become done through
high-speed connections. Although low-speed interfaces like
the universal asynchronous receiver/transmitter (UART),
serial peripheral interface (SPI), or inter-integrated circuits
were always present with embedding microcontrollers (I2C).
The physical layer for transmitting or receiving sensor data is
provided by these interfaces. The key benefits are the
inexpensive cost of having them as integrated peripherals in
the microcontroller and, indeed, the low electricity
consumption involved with driving the interfaces. In addition
to being a local communication interface, UART can be used
for inter-device communication (e.g., device status, sending
erroneous messages, performing software updates). In the
examples above, UART data transmission is not secure and is
susceptible to mistakes. This technique offers a frame that
facilitates UART connection with embedded real-time
systems. The signal handling function was added towards the
information framework implementation to ensure that the
communication process does not impede the device's real-time
functioning.
324
 Proceedings of the International Conference on Edge Computing and Applications (ICECAA 2022)
IEEE Xplore Part Number: CFP22BV8-ART; ISBN: 978-1-6654-8232-5
According to Kiran et al. [8], establishing a communication
protocol between two pieces of electrical equipment was
critical for every embedded platform. The proper operation of
the system would be implied by testing and validating such a
protocol. Mobility and distance between the System under
Test (SUT) and the test engineer are frequently encountered
obstacles that need to be taken into account. Testing using
wireless technology is the answer to this issue. The goal of
this work is to provide a wireless testing and validation system
for communication protocols. The finished product consists of
test equipment with probes for measuring and probing signals
in real time, as well as a web application backed by the cloud
with a graphical user interface (GUI) for presenting the
signals. That electronic device could transmit the information
with either a 512-byte width on the MQTT (Message Queue
Telemetry Transportation) brokerage, then deliver it to the
clouds, as well as test this signal at a potential rate of 400 kilo
samples per second. Using the TI-CC3200 Simple link Wi-Fi
board and the IBM Blue mix cloud-based Node RED
application was designed to make the device. Many industrial
and medical applications for real-time signal probing and
monitoring could benefit from this verification and testing for
data utilizing a cloud-based GUI.
This significance in data transfer has been understood, and in
the modern world, these serial communication ports are
incorporated in even high-end FPGA's. Keerthi Nayani et al.
[9] developed an approach based on the revolutionary
advances that serial communication has made in the previous
forty years. UART is a serial communication protocol that is
used in FPGAs' UART ports as a transmitter and receiver to
send and receive data asynchronously. UART translates serial
data to parallel for transmission and parallel data to serial for
reception. The UART has a buffer for quick information
transfer, and the cache can hold up to 2 bytes of memory.
Whenever the acceptance machine really isn't ready to take the
information, it contains additional memories that control the
abundance of data and reveal opinions regarding
communication modes, flow of information from ports, and
transmission statuses. When UART has a sizable buffer to
store the data arriving from the transmitter and receiver, it can
glide the data. The buffer's size is determined by how the
UART is built. As a component of telemetry, an avionics
technology, remote data acquisition units (RDAU) used in
missiles utilize the Universal Asynchronous Receiver
Transmitter procedures.
High performance of the SPI Interface Protocol with Single
Master and Single Slave configuration is described by Pallvi
et al. [10]. This mixture contains 8-bit data transmission and
has all the important elements needed for contemporary
applications like ASIC or SOC (System on Chip). SPI (Serial
Peripheral Interface), which was developed by the company
Motorola, is a protocol for serial synchronous communication
between a master and slave machine. It can also be used to
provide communication between a microcontroller and
numerous additional and related devices, such as external
ADCs, DDCs, and EEPROMs. Communication channels are
currently quite basic. Two distinct protocols exist. Inter-I2C
978-1-6654-8232-5/22/$31.00 ©2022 IEEE
Authorized licensed use limited to: Nirma University Institute of Technology. Downloaded on January 04,2024 at 03:40:49 UTC from IEEE Xplore. Restrictions apply.
and SPI are first. These two procedures have been well
thought out for communication between Integrated Circuits
and on-board peripherals. SPI is the most widely used protocol
for data stream transfers at low to medium speeds, including
intra-and inter-chip. The complete RTL was developed in
Verilog for synthesis, and then System Verilog was used to
write the verification architecture. This process demonstrates
the coverage code and functional correctness of the SPI
design. Using Spartan 3E, the implementation is carried out.
System Verilog and constraint-based randomization
techniques will be used to successfully finish and verify the
whole design of the SPI with one Master and one Slave
configuration. It can run in full duplex mode and has been
reported to have 100% code and functional coverage.
The UART for data connection is primarily implemented and
analyzed in Akshatha et al.'s [1]. The baud rate generator,
transmitter, and receiver modules are all implemented using
the finite state machine (FSM). The Cadence RTL Compiler
was used for synthesis, utilising the 45 nm and 90 nm General
Process Design Kit (GPDK) library files, while Cadence
NCSIM was used for simulation. The UART was created
using a 50 MHz clock frequency and a baud rate of 9600 bps.
Power consumption has significantly grown as a result of the
VLSI chip designs' increased speed and complexity.
According to a comparative inves tigation of power and delay
for various clock times, the Power Delay Product (PDP) and
total power both improve with longer clock periods. Whilst
employing the 45 nm technology, better outcomes could be
seen compared to the 90 nm library.
In order to increase the overall amount of data transmitted
through the bilateral relay system, chen et al. introduced a
work that proposes an ideal time allocation for the system
[17]. The two-way transmission's conveyance rate is
calculated utilising the destined data rate and the effective
conveyance probability to have an ideal time assignment. The
study has suggested an ideal time assignment for each
connection taking into account the learned details of data
conveyance. The evaluation of performance data revealed that
the coverage, dependability, and capacity of the wireless
network were all enhanced by the bidirectional relay network
with the best time allocations.
Rapid improvements in wireless communication networks,
which B. Sathesh created, have raised the attractiveness of
portable or mobile gadgets and the networks built around them
[18]. These mobile networks are decentralized, have dynamic
topologies, and experience abrupt changes in the structure
since they are built utilising volunteer portable devices. The
device's limited energy supply and mobility are the key causes
of the topological alterations. Improper task distribution and
poor portable device selection lead to high energy
consumption, which results in network link failures and
topology changes. Because of this, the study proposes the
hybridised optimization technique to deal with the multi-
objective problem that these decentralized networks face. The
network simulator is used to verify the proposed method -2 to
demonstrate the throughput, energy use, and network lifetime
attained by the suggested strategy.
325
 Proceedings of the International Conference on Edge Computing and Applications (ICECAA 2022)
IEEE Xplore Part Number: CFP22BV8-ART; ISBN: 978-1-6654-8232-5

The transmitter's hold register contains the data-byte that will

III ARCHITECTURE
A. Design of UART communication Protocol
The UART communication protocol evolved to act for
communicating with hardware components in computers. It
illustrate sustained features of various accomplishment of
determined values to anticipate with distinct attributes. The
design of UART communication protocol evolves with
deterministic activity of sustained features of various blocks
[11]. The transmitter and receiver, which are both included in
the UART block diagram, are shown below. Three blocks
make up the transmitter section: control logic, a shift register,
and a transmit hold register. The receiver portion also has
control logic, a shift register, and a receive hold register. A
baud-rate generator generally offers these two portions. When
the transmitter portion and reception section must broadcast or
receive data, this generator is employed to generate the
required speed.
The transmitter's hold register contains the data-byte that will
be broadcast. Up until a byte of data is broadcast or received,
the shift registers in the transmitter and receiver shift the bits
to a right or left. For determining when to read, a book (or)
write logic is employed.
The speed that is generated by the baud-rate generator
between the transmitter and receiver varies from 110 bps -
230400 bps. Microcontroller baud rates typically range from
9600 to 115200. The transmitter and receiver, which are both
included in the UART block diagram, are shown below. Three
blocks make up the transmitter section: control logic, a shift
register, and a transmit hold register. The receiver portion also
has control logic, a shift register, and a receive hold register. A
baud-rate generator generally offers these two portions. When
the transmitter portion and reception section must broadcast or
receive data, this generator is employed to generate the
required speed.
Fig.3.1. UART Architecture protocol
be broadcast. The transmitter's and receiver's shift registers
cause the A byte of information is transferred or received by
shifting the baud rate generator's bits between the transmitter
and receiver to the right or left. When and how to receive or
write is determined by a read (or) publish control logic.
The speed that is generated by the baud -rate generator
between the transmitter and receiver ranges from 110 bps -
230400 bps. Microcontroller baud rates typically range from
9600 to 115200.
As the above figure UART protocol is designed.
Fig.3.2. UART Architecture diagram [7]
B. UART Transmitter end
The communication protocol which act as source to ensure
value defined for accomplishment. It retrieves through FIFO
module to retain information and data access. The purpose of
data transfer is to convert parallel data into serial data for
aspects of quality. This may deal with defined value across
shift registers to accompany through internal data bus aspect.
The utilization of First in First Out to accompany with distinct
factors by adding parallel value to structure system with parity
check bits.
The component that directs data by data to produce distinct
results. The conceptualization of the system statement at this
step of the data-factoring process uses the transmitting pin
values at the source end as the UART transmitting end value.
The figure of UART transmitting end is
C. UART Receiver end
The UART receiver end also act as transmitter end through
shift register which recognize its activities. The module First
in First Out module act as defined structural value to
recognize its distributive attributes approaches.
D. FIFO

978-1-6654-8232-5/22/$31.00 ©2022 IEEE 326

Authorized licensed use limited to: Nirma University Institute of Technology. Downloaded on January 04,2024 at 03:40:49 UTC from IEEE Xplore. Restrictions apply.
 Proceedings of the International Conference on Edge Computing and Applications (ICECAA 2022)
IEEE Xplore Part Number: CFP22BV8-ART; ISBN: 978-1-6654-8232-5

When the UART interrupts the CPU to transmit data between 45nm to 90nm. The power factor delivered through system is
the FIFO and CPU memory, it depends on the size of the 133.8µW. The delay resulted upon research process is 1ns.
FIFO buffers (RAM, where applications running on the CPU
have access to the data). As a result, the size of FIFOs can
have an impact on an application's overall performance as well
as latencies for writing to it and reading from of the serial
port, which are typically on the scale of milliseconds.
For instance, if we set the reception buffer to 1, every time a
byte is received, the UART would interrupt its processor and
send a memory cards to CPU memory. If data is constantly
being accepted at the port, even though this will enable a
particular byte accessible in RAM as quickly as feasible after
coming at the many interruptions will result from this port. As
a result, those interrupts receive extra CPU processing, which
can impact performance if other programmers are running.
Therefore, using a higher receive FIFO size is frequently
advantageous for overall performance if delays on the order a
few millisecond are acceptable for serial processes.
We should be aware that an interruption will frequently
happen to ensure that you can receive & access data if only 4
Fig4.a
bytes ever were received, regardless of the receiving FIFO
size is, or example, 14 bytes. Similar to this, it transmit FIFO
size determines how many bytes can be moved from RAM to
a transmit FIFO at once. In light of this, if indeed the transmit
FIFO length sending additional data on every interrupt will let
you transfer big volumes of data with less latency.
E. Baud rate generator
The baud rate generator approaches system with restricted
outcomes [12]. It restrict system limit through defined value to
accomplish with certain resultant attributes.
Shift registers
The shift registers is utilized to control activities of system
value with defined structural approach. It integrate system to
stimulate predominant value sustained through effective
aspect in communication protocol.

IV SIMULAT ION RESULT

The stimulation was carried out using modeling software.
VHDL, Verilog, SystemVerilog, and mixed-language designs Fig.4.b
Figure 4 a & b Simulation result of UART operations [5]
can be verified and simulated using ModelSim software. A
serial driver chip connects the Rx and Tx pins of a
microcontroller-based embedded device's controller to the
COM port of a computer during UART transmission (like
MAX232 for RS-232 protocol). The data stream is then
verified using applications like HyperTerminal. The
simulation result value of UART communication protocol
evolves with discrete outcome. It has an ability to act
according to defined resources and evolve with valid
accomplishment of data functional values. It denotes value of
sustained result with individual entity to act through individual
entity value and sustained attributes. This has an ability to
develop system through definition of transmission towards
communication protocol. It result value which might
drastically improves system value towards distinct resultant
statements. The error prediction of system consoled would be
valued through delivering data outcomes. The power delay
Fig.4.2. Error detection of UART protocol [13]
product resulted through UART communication protocol as

978-1-6654-8232-5/22/$31.00 ©2022 IEEE 327

Authorized licensed use limited to: Nirma University Institute of Technology. Downloaded on January 04,2024 at 03:40:49 UTC from IEEE Xplore. Restrictions apply.
 Proceedings of the International Conference on Edge Computing and Applications (ICECAA 2022)
IEEE Xplore Part Number: CFP22BV8-ART; ISBN: 978-1-6654-8232-5
V CONCLUSION AND FUT URE WORK
Thus, summarization of UART communication protocol
analysis has been resulted with required outcomes in Fig 4a
and Fig 4b. This could be possible through defining factors
and events taken part towards detailed accomplishment of
AES algorithm and FIFO architecture. The illustration of
FIFO architecture is processed due to effective result value
due to transmission of data towards their lines without any
efficient result attributes. The simulation result has proven
their value which is determined according to functional system
statements. The supporting factor for hardware approach deals
with distinct value regarding FPGA board. The integration of
FPGA and AES algorithm to perform their values as expected
result. The limitation has processed with defined sector to
function through modernized value of bus through System on
Chip (SoC).
REFERENCES
[1] Akshatha, "Design and Implementation of Power-Efficient FSM based
UART ," https://iopscience.iop.org/article/10.1088/1742 -
6596/2161/1/012052/pdf, pp. 1-9, 2022.
[2] Umakanta, "Universal Asynchronous Receiver and T ransmitter
(UART ),"
https://www.researchgate.net/publication/308988751_Universal_Asynch
ronous_Receiver_and_T ransmitter_UART , pp. 1 -12, 2018.
[3] Bidisha, "Universal Verification Methodology Based Verification of
UART Protocol,"
https://www.researchgate.net/publication/348452220_Universal_Verific
ation_Methodology_Based_Verification_of_UART_Protocol, pp. 1-19,
2020.
[4] Dawoud, "Serial Communication Protocols and Standards RS232/485,
UART /USART , SPI, USB, INST EON, Wi-Fi and WiMAX,"
https://ieeexplore.ieee.org/document/9227663, pp. 1 -11, 2020.
[5] j. Asha, "Design and Verification of Functional Blocks of 32-Bit
Microprocessor," https://www.irjet.net/archives/V8/i9/IRJET -
V8I9301.pdf, pp. 1-8, 2021.
978-1-6654-8232-5/22/$31.00 ©2022 IEEE
Authorized licensed use limited to: Nirma University Institute of Technology. Downloaded on January 04,2024 at 03:40:49 UTC from IEEE Xplore. Restrictions apply.
[6] Yamini, "Design and Verification of UART using System,"
https://www.ijeat.org/wp-
content/uploads/papers/v9i5/E1135069520.pdf, pp. 1-12, 2020.
[7] C. C. Mihai, "Protocol over UART for Real-T ime Applications,"
https://ieeexplore.ieee.org/document/9663605, pp. 1 -15, 2020.
[8] Kiran, "T esting and validation of UART using cloud based GUI,"
https://ieeexplore.ieee.org/document/8256704, p p. 1-6, 2021.
[9] K. Nayani, "esign and Implementation of Uart Protocol for Avionics
Applications," https://ieeexplore.ieee.org/abstract/document/9065366,
pp. 1-20, 2020.
[10] Pallavi, "Design & Verification of Serial Peripheral,"
https://www.ijrte.org/wp-content/uploads/papers/v8i6/F7356038620.pdf,
pp. 1-4, 2020.
[11] Wilder, "Internet of things: a multiprotocol gateway as,"
https://arxiv.org/pdf/2108.00098.pdf, pp. 1 -10, 2020.
[12] V. K. I. a. E. V. Nosov2, "Serial communication protocol for FPGA-
based systems," https://iopscience.iop.org/article/10.1088/1742 -
6596/1326/1/012044, pp. 1-8, 2021.
[13] Sarmad, "Baud rate variations effect on virtual channel,"
https://pdfs.semanticscholar.org/9732/04e2321d4d2eb214eabcc2f58a54f
9be059e.pdf, pp. 55-63, 2020.
[14] A. Pietro, "Static analysis for discovering IoT vulnerabilities,"
https://link.springer.com/article/10.1007/s10009-020-00592-x, pp. 1-15,
2020.
[15] Sardi, "DESIGN AND IMPLEMENTATION OF UART WIT H FIFO
BUFFER USING VHDL,"
http://ictactjournals.in/paper/IJME_Vol_5_Iss_1_Paper_4_724_730.pdf,
pp. 1-19, 2020.
[16] G. Juraj, "Implementation of Secure Communication via the RF Module
for Data Acquisition,"
https://www.hindawi.com/journals/js/2019/7810709/, pp. 1-12, 2020.
[17] Chen, Joy Iong Zong, and Kong-Long Lai. "Data Conveyance
Maximization in Bilateral Relay System using Optimal T ime
Assignment." Journal of Ubiquitous Computing and Communication
T echnologies (UCCT ) 2, no. 02 (2020): 109 -117.
[18] B. Sathesh, A. "Optimized multi-objective routing for wireless
communication with load balancing." Journal of trends in Computer
Science and Smart technology (T CSST ) 1, no. 02 (2019): 106 -120.
328