IRFR4615PbF

IRFU4615PbF
HEXFET® Power MOSFET

Applications
D
VDSS 150V
l High Efficiency Synchronous Rectification in SMPS RDS(on) typ. 34m:
42m:
l Uninterruptible Power Supply
l High Speed Power Switching
G max.
l Hard Switched and High Frequency Circuits
S
ID 33A

D D

Benefits
l Improved Gate, Avalanche and Dynamic dV/dt S
S D
Ruggedness G G
l Fully Characterized Capacitance and Avalanche
DPak IPAK
SOA IRFR4615PbF IRFU4615PbF
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
G D S
Gate Drain Source

Standard Pack Orderable Part Number

Base Part Number Package Type
Form Quantity
IRFR4615PbF Tube/Bulk 75 IRFR4615PbF
D-PAK
IRFR4615TRLPbF Tape and Reel Left 3000 IRFR4615TRLPbF
IRFU4615PbF I-PAK Tube/Bulk 75 IRFU4615PbF

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 33
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 24 A
IDM Pulsed Drain Current c 140
PD @TC = 25°C Maximum Power Dissipation 144 W
Linear Derating Factor 0.96 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery e 38 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range
°C
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy d 109 mJ
IAR Avalanche Current c See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy c mJ

Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Casej ––– 1.045
RθJA Junction-to-Ambient (PCB Mount) i ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110

Notes  through ˆ are on page 11

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Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 150 ––– ––– V VGS = 0V, ID = 250μA
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.19 ––– V/°C Reference to 25°C, ID = 5mA c
RDS(on) Static Drain-to-Source On-Resistance ––– 34 42 mΩ VGS = 10V, ID = 21A f
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 100μA
IDSS Drain-to-Source Leakage Current ––– ––– 20 VDS = 150V, VGS = 0V
μA
––– ––– 250 VDS = 150V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG(int) Internal Gate Resistance ––– 2.7 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 35 ––– ––– S VDS = 50V, ID = 21A
Qg Total Gate Charge ––– 26 ID = 21A
Qgs Gate-to-Source Charge ––– 8.6 ––– VDS = 75V
Qgd Gate-to-Drain ("Miller") Charge ––– 9.0 –––
nC
VGS = 10V f
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 17 ––– ID = 21A, VDS =0V, VGS = 10V
td(on) Turn-On Delay Time ––– 15 ––– VDD = 98V
tr Rise Time ––– 35 ––– ID = 21A
ns
td(off) Turn-Off Delay Time ––– 25 ––– RG = 7.3Ω
tf Fall Time ––– 20 ––– VGS = 10V f
Ciss Input Capacitance ––– 1750 ––– VGS = 0V
Coss Output Capacitance ––– 155 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 40 ––– pF ƒ = 1.0MHz (See Fig.5)
Coss eff. (ER) Effective Output Capacitance (Energy Related) h ––– 179 ––– h
VGS = 0V, VDS = 0V to 120V (See Fig.11)
Coss eff. (TR) g
Effective Output Capacitance (Time Related) ––– 382 ––– VGS = 0V, VDS = 0V to 120V g
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 33
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

(Body Diode)c ––– ––– 140

p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 21A, VGS = 0V f
trr Reverse Recovery Time ––– 70 ––– TJ = 25°C VR = 100V,
ns
––– 83 ––– T = 125°C IF = 21A
f
J
Qrr Reverse Recovery Charge ––– 177 ––– TJ = 25°C di/dt = 100A/μs
nC
––– 247 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 4.9 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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1000 1000
VGS VGS
TOP 15V TOP 15V
12V 12V
10V 10V
100

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

8.0V 8.0V
7.0V
100 7.0V
6.0V 6.0V
5.5V 5.5V
BOTTOM 5.0V BOTTOM 5.0V
10
10
5.0V
1

1
5.0V
0.1
≤60μs PULSE WIDTH ≤60μs PULSE WIDTH
Tj = 25°C Tj = 175°C
0.01 0.1
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0

RDS(on) , Drain-to-Source On Resistance

ID = 21A
VGS = 10V
ID, Drain-to-Source Current (A)

2.5
100
TJ = 175°C

2.0
(Normalized)

TJ = 25°C
10

1.5

1
1.0
VDS = 50V
≤60μs PULSE WIDTH
0.1 0.5
2 4 6 8 10 12 14 16 -60 -40 -20 0 20 40 60 80 100120140160180

VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 14.0
VGS = 0V, f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED ID= 21A
C rss = C gd 12.0
VGS, Gate-to-Source Voltage (V)

C oss = C ds + C gd VDS= 120V

10000
10.0 VDS= 75V
C, Capacitance (pF)

VDS= 30V
Ciss 8.0
1000
Coss 6.0

Crss 4.0
100

2.0

10 0.0
1 10 100 1000 0 5 10 15 20 25 30 35
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

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1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

100
100μsec
100
1msec

T J = 175°C 10
10msec

T J = 25°C
10 DC
1
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
1.0 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

40 190
Id = 5mA
35 185

180
30
ID, Drain Current (A)

175
25
170
20 165

15 160

155
10
150
5
145
0 140
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.0 500
EAS , Single Pulse Avalanche Energy (mJ)

ID
450
2.5 TOP 2.8A
400 5.3A
350 BOTTOM 21A
2.0
Energy (μJ)

300
1.5 250

200
1.0
150

0.5 100

50
0.0 0
-20 0 20 40 60 80 100 120 140 160 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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10

Thermal Response ( Z thJC ) °C/W

1
D = 0.50

0.20
0.10 R1 R2 R3 R4 Ri (°C/W) τi (sec)
0.1 R1 R2 R3 R4
τJ 0.02324 0.000008
0.05 τJ
τC
τ
0.02 τ1 τ2
0.26212 0.000106
τ1 τ3 τ4
τ2 τ3 τ4
0.01 0.50102 0.001115
0.01 Ci= τi/Ri
Ci i/Ri
0.25880 0.005407
Notes:
SINGLE PULSE
1. Duty Factor D = t1/t2
( THERMAL RESPONSE )
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100
Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)

0.01
10

0.05
0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

120 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
100 ID = 21A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
80 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
60
during avalanche).
6. Iav = Allowable avalanche current.
40 7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
20 D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0 PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

25 50 75 100 125 150 175 Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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6.0 30
IF = 14A
5.5
VGS(th) , Gate threshold Voltage (V)

25 V R = 100V
5.0
TJ = 25°C
4.5 TJ = 125°C
20
4.0

IRRM (A)
3.5 15
ID = 100μA
3.0 ID = 250uA
ID = 1.0mA 10
2.5
ID = 1.0A
2.0
5
1.5

1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/μs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

35 800
IF = 21A IF = 14A
30 V R = 100V 700 V R = 100V
TJ = 25°C TJ = 25°C
25 TJ = 125°C 600 TJ = 125°C
IRRM (A)

20 500
QRR (A)

15 400

10 300

5 200

0 100
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/μs) diF /dt (A/μs)
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

1000
IF = 21A
900
V R = 100V
800 TJ = 25°C
TJ = 125°C
700
QRR (A)

600

500

400

300

200

100
0 200 400 600 800 1000
diF /dt (A/μs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS

VGS
90%
D.U.T.
RG
+
- VDD

V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50KΩ

12V .2μF
.3μF

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER
WITH ASS EMBLY INTERNATIONAL
LOT CODE 1234 RECT IFIER IRFR120 DAT E CODE
AS S EMBLED ON WW 16, 2001 LOGO 116A YEAR 1 = 2001
IN THE AS S EMBLY LINE "A" 12 34 WEEK 16
LINE A
Note: "P" in as sembly line pos ition AS SEMBLY
indicates "Lead-Free" LOT CODE
"P" in ass embly line position indicates
"Lead-Free" qualification to the consumer-level

PART NUMBER
INT ERNAT IONAL
OR RECT IFIER IRFR120
DAT E CODE
P = DES IGNAT ES LEAD-FREE
LOGO PRODUCT (OPTIONAL)
12 34
P = DES IGNAT ES LEAD-FREE
PRODUCT QUALIFIED T O THE
AS S EMBLY
CONS UMER LEVEL (OPTIONAL)
LOT CODE
YEAR 1 = 2001
WEEK 16
A = ASS EMBLY S ITE CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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 IRFR/U4615PbF

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

EXAMPLE: THIS IS AN IRFU120 PART NUMBER

INTERNAT IONAL
WITH AS SEMBLY
RECTIFIER IRFU120 DAT E CODE
LOT CODE 5678
LOGO 119A YEAR 1 = 2001
AS SEMBLED ON WW 19, 2001
56 78 WEEK 19
IN THE ASS EMBLY LINE "A"
LINE A
ASS EMBLY
LOT CODE
Note: "P" in ass embly line position
indicates Lead-Free"

OR
PART NUMBER
INTERNAT IONAL
RECTIFIER IRFU120 DATE CODE
LOGO P = DESIGNAT ES LEAD-FREE
56 78 PRODUCT (OPT IONAL)
YEAR 1 = 2001
ASS EMBLY
LOT CODE WEEK 19
A = ASS EMBLY S IT E CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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 IRFR/U4615PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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†
Qualification Information
Industrial
Qualification level
(per JEDEC JESD47F†† guidelines)
MSL1
D-PAK
Moisture Sensitivity Level (per JEDEC J-STD-020D††)
I-PAK Not applicable

RoHS Compliant Yes

† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/product-info/reliability

†† Applicable version of JEDEC standard at the time of product release.

Notes:
 Repetitive rating; pulse width limited by max. junction
temperature.
‚ Limited by TJmax, starting TJ = 25°C, L = 0.51mH
RG = 25Ω, IAS = 21A, VGS =10V. Part not recommended for use
above this value .
ƒ ISD ≤ 21A, di/dt ≤ 549A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
„ Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
† Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application
note #AN-994
ˆ Rθ is measured at TJ approximately 90°C

Revision History
Date Comments
•Updated datasheet to new IR corporate formatting template
5/16/2013
•Updated Orderable part number from "IRFR4615TRPbF" to "IRFR4615TRLPbF", on page 1

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

11 www.irf.com © 2013 International Rectifier May 16, 2013

IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
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