CHAPTER 7

FLIP-FLOPS AND
REGISTERS

Objectives

ƒ Sequential circuits

ƒ SR, D and JK Flip-flops

ƒ Registers

ƒ Calculator
 104

7.1 Sequential Circuit

Logic circuits are classified in two categories. The logic circuits

considered thus far have been combinational circuits, whose output is
a function of only the present input. The basic building block of
combinational circuits is the logic gate.

Input Combinational Ouput

Logic Gates

Most digital systems are made up of combinational circuits and

memory elements. This circuit is known as sequential logic circuits.
The output of the circuit depends not only on the present input but on
previous inputs as well. This history of a sequential circuit’s input is
retained through the use of storage devices, that is the memory.

Input Combinational Ouput

Logic Gates

Memory

In this chapter we introduce a number of common memory elements

including latches and flip-flops.

7.2 Set-Reset Latch (SR Latch)

The logical operation of the SR latch is summarized in the excitation

table below.

S
Q S Q
SR
Latch
R Q
R Q

Input Present Next

State State
S R Q Q*
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x
 105

The equation for SR latch is Q* = S + R.Q . We can classify the operation

of the latch into three modes.

Mode 1:
S=R=0. Q*=Q. The next state Q* is equal to the present state Q. So,
there is no change of state.

Mode 2:
S=1, R=0. Q* = 1, representing set operation.

Mode 3:
S=0, R=1. Q*=0, representing reset operation.

The truth table for SR latch can be written as:

S R Q Q Mode
0 0 Q Q Hold
0 1 0 1 Re set
1 0 1 0 Set
1 1 0 0 Pr ohibited(invalid)

Example 1:
Assume that the initial state Q=0. Determine the Q waveform for the
SR latch.

S
R

Reset Reset Set Hold Reset Reset

Initialstate
Q=0 Output Q changes states
immediately when S or R
changes

The output of SR latch changes states immediately when S or R

changes.
 106

7.3 SR Flip-Flop

The operation of SR flip-flop is similar to that of the simple SR latch.

The characteristic equation is Q* = S + R.Q . The difference is that, the
latch output reacts immediately to any output changes, while the flip-
flop output changes are controlled by the clock pulse CLK. A flip-flop
with a small triangle on its CLK input indicates that this input is
activated only when the clock changes from a 0 to a 1 () occurs. This
is known as the positive-going transition or positive-edge triggered.

Input Present CLK Next

State State
SET
S R Q Q*
S Q 0 0 0 0
0 0 1 1
0 1 0 0
R CLR
Q
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

The truth table can be written as

CLK S R Q Q Mode
0 0 Q Q Hold
0 1 0 1 Re set
1 0 1 0 Set
1 1 0 0 Pr ohibited (invalid )

Example 1:
Assume that the initial state Q=0. Determine the Q waveform for the
SR flip-flop.

CLK 1 2 3 4 5 6 7 8

Hold Set Hold Reset Set Set Hold Reset

Output Q changes states

(reacts) when the CLK
changes from 0 to 1
 107

7.4 D Flip-Flop

The D flip-flop has only a single data input D and a clock input CLK.
The SR flip-flop can be converted to a D flip-flop by adding an inverter.
Data is transferred from the input D to the output Q on the 0 → 1
transition of the clock pulse.

SET SET
S Q D Q CLK D Q
0 0
R CLR
Q CLR
Q 1 1

Example 1:
Assume that Q=0 initially. Determine the Q waveform for the D flip-
flop.

CLK 1 2 3 4

7.5 D Latch

The edge-triggered D flip-flop in 7.4 will respond to the D input on the

0 to 1 clock transition. The D latch operates differently. It has an
enable input E. When E=0, the output Q is ‘latch’ to the present state
and cannot change even if D changes. When E=1, the Q output is
equal to D.

E D Q
D Q
0 x Nochange
E Q 1 0 0
1 1 1
Example 1:
Assume that Q=0 initially. Determine the Q waveform for the D flip-
flop.

1 2 3 4

Output Q changes states

immediately when D
changes
 108

7.6 Application of D flip-flop

Consider a simple calculator as shown below. When the number 7 is

pressed on the keyboard, a decimal 7 appears on the display.
However, when the key is released, the number 7 disappears from the
output display. To solve this problem, a 4-bit storage register has
been added to store the number. It can be said that the number 7 is
latched on the display.

789
456 Encoder Decoder
123
0

Without storage register

Gnd

S9 DISP1
74147
I9 abcdefg.
S8 I8 74LS48
I7 A3 A3 g
I6 A2 A2 f
I5 A1 A1 e
S7 I4 A0 A0 d
I3 c
I2 b
I1 a
S6
test
RBI RBO
S5

S4

S3

S2

S1

S0
 109

789 4-Bit
456 Encoder Storage Decoder
123 Register
0

With memory (latch)

A 4-bit storage register can be constructed using 4 D flip-flop. The

input data is transferred into the D flip-flop on a 0 → 1 clock pulse.

9
4321
4321

D0 Q0
D1 Q1
D2 Q2
D3 Q3
5V Load CP
+V
TP1

R2
1k

9
4321 4321

D Q
_
CP Q

D Q
_
CP Q

D Q
_
CP Q

D Q
_
CP Q

V1
5V Load
+V

R1
1k
 110

SET
D Q

CLR
Q

1 1 D
SET
Q
2 2
3 MSB
3 A CLR
Q
4 4 B
5 Enkoder Dekoder
SET
D Q
5 C
6 LSB
6 D
Q
7 7
CLR

8 8 SET
D Q
9 9
0 CLR
Q

When a number is pressed on the keyboard, the output of the OR

gate is 1. This 0 → 1 clock transition will transfer the data, from the
encoder into the D flip-flop. When the key is released, the number
will remain lit on the seven-segment display. The number is latched
on the display.

Gnd

S9
74147
I9 abcdefg.
S8 I8 74LS48
I7 A3 A3 g
I6 A2 D0 Q0 A2 f
I5 A1 D1 Q1 A1 e
S7 I4 A0 D2 Q2 A0 d
I3 c
I2 D3 Q3 b
I1 a
CP
S6
test
RBI RBO
S5

S4

S3

S2

S1

S0
 111

7.7 Simple Calculator

This is a simple add and subtract calculator. It has two storage

register A and B. The Control Load input is used to load the number
presses on the keyboard, into register A or register B. The
Add/Subtract Control = 1 for addition and 0 for subtraction.

Add two numbers 2+3.

1. Load 0 into register A and B.

• Load A = 1 and Load B = 1.
• Press 0.
Output of OR gate = 1. A clock transition 0 → 1 will transfer the
number 0 into register A and B.
Register A=0. Register B= 0. Number 0 is displayed.

2. To perform addition, Add/Sub Control = 0.

3. Load Register A = 2.
• Load A = 1 and Load B = 0.
• Press 2.
Output of OR gate = 1. A clock transition 0 → 1 will transfer the
number 2 into register A.
Number 2 is displayed.

4. Load Register B = 3.
• Load B = 1 and Load A = 0.
• Press 3.
Output of OR gate = 1. A clock transition 0 → 1 will transfer the
number 3 into register B.

5. Register A + Register B = 2+3. The answer 5 is displayed.

 Register
A

7 8 9 a
4 5 6 Control 4 Bit f b
Encoder g
1 2 3 Load Adder Decoder
e c
0 d

Add/
Register
Subtract
B
Control
112
 SET
D Q A1
B1
L CLR
Q
Σ1 A a
SET
D Q A2 b
Σ2 B c
B2
L CLR
Q 7 Segment d
SET
4 Bit Adder Σ3 C Decoder e
D Q A3
f
B3 Σ4 D g
L CLR
Q

D
SET
Q A4
8
B4
L CLR
Q

1 Register A
2 1 Y
3 2
4 3 A MSB
7 8 9 4 B Add/Subtract
5 Load A Control
4 5 6 6 5 C LSB
1 2 3 6 D Load B
7
0 8 7
9 8
Z Control Load
0 9

SET
D Q

x
L CLR
Q
SET
D Q

L CLR
Q
SET
D Q

L CLR
Q

SET
D Q

L CLR
Q

Register B
113
 114

Exercises

1. Assume that Q=0 initially. Determine the Q waveform for the SR

latch.

Q=0

Mode

2. Assume that Q=0 initially. Determine the Q waveform for the SR

flip-flop.

CLK 1 2 3 4 5 6 7 8

Q=0

Mode

3. Assume that Q=0 initially. Determine the Q waveform for the D flip-
flop.

CLK 1 2 3 4 5 6 7 8

Q=0

Mode