UNIT-5

Digital design process flow using HDL

Modules and Po s
Compiler Directives
Data types and operators
Introduction to VHDL-modelling styles
HDL
• Hardware Description Language (HDL) is a specialized
computer language used to describe the structure and
behavior of electronic circuits, most commonly to design ASICs
and program FPGAs.
• A hardware description language looks much like a
programming language such as C or ALGOL; it is a textual
description consisting of expressions, statements and control
structures.
Syntax and structure
• The basic syntax elements in HDL o en include identifiers, data
types, operators, and a ributes.
• HDL structure consist a textual description involving many
inputs, outputs, signals operators, components, multiple
architectures, and comments.Each and every HDL uses a
different structure and design method.
Verilog HDL
• Verilog, is a hardware description language (HDL) used to
model electronic systems. It is most commonly used in the
design and verification of digital circuits at the register-transfer
level of abstraction.
• Verilog and VHDL are two primary hardware description
languages (HDLs) engineers and designers use to model,
simulate, and synthesize digital systems. These languages are
crucial in developing integrated circuits (ICs), field-
programmable gate arrays (FPGAs), and other digital hardware.
Verilog HDL
• Verilog is a Hardware Description Language (HDL). It is a
language used for describing a digital system such as a network
switch, a microprocessor, a memory, or a flip-flop. We can
describe any digital hardware by using HDL at any level.
• Verilog Abstraction Levels
• Verilog suppo s a design at many levels of abstraction, such as:
• Behavioral level
• Register-transfer level
• Gate level
Advantages of HDL
• HDLs can be used to design and describe the layout of digital
systems from simple flip-flop memory units to complex
communications protocols. Circuit Design: It provides a way to
design digital circuits that meet the required specifications.
Digital design process flow using HDL
• In any design, specifications are wri en first. Specifications
describe abstractly the functionality, inte ace, and overall
architecture of the digital circuit to be designed. At this point,
the architects do not need to think about how they will
implement this circuit. A behavioral description is then created
to analyze the design in terms of functionality, pe ormance,
compliance to standards, and other high-level issues.
Digital design flow using HDL
Explanation
• Unshaded blocks show the level of design representation,
shaded blocks show processes in the design flow.
• This design flow is typically used by designers who use HDLs
• Specifications describe abstractly the functionality,inte ace and
overall architecture of the digital circuit to be designed.
• A Behavioral description is then created to analyze the design in
terms of functionality,pe ormance compliance to standards
and other high level issues.
• Behavioral descriptions are o en wri en with HDLs
• It is manually conve ed to an RTL description in an HDL
• The designer has to describe the data flow that will implement
the desired digital circuit
• From this point onwards,the design process is done with the
assistance of EDA tools
• Logic synthesis tools conve the RTL description to a gate level
netlist
• Logic synthesis tools ensure that the gate level netlist meets
timing,area and power specifications
• The gate level netlist is input to an Automatic place and route tool,
which creates a layout.
• The layout is verified and then fabricated on a chip
• Thus,most digital design activity is concentrated on manually
optimizing the RTL description of the circuit.
• A er RTL descrition is frozen,EDA tools are available to assist the
designer in fu her processes
• Behavioral synthesis tools can create RTL descriptions from a
bahavioral or algorithmic description of the circuit
• Designers will simply implement the algorithm in an HDL at
avery abstract level
• EDA tools will help the designer to conve the behavioral
description to a final IC chip.
VHDL-INTRODUCTION
• VHDL stands for Very High-Speed Integrated Circuit(VHSIC) Hardware
Description Language. It is a programming language used to model a
digital system by dataflow, behave
• Describing a Design includes,
• In VHDL an entity is used to describe a hardware module. An entity can be
described using,
• Entity declaration
• Architecture
• Configuration
• Package declaration
• Package body
Difference between VHDL and Verilog
VHDL
It allows the user to define
data types.
I t s u p p o r ts t h e M u l t i -
Dimensional array.
It allows concurrent procedure
calls.
A mod operator is present.
Unary reduction operator is
not present.
It is more difficult to learn.
Verilog
It does not allow the user to
define data types.
It does not suppor tthe Multi-
Dimensional array.
It does not allow concurrent
calls.
A mod operator is not present.
Unary reduction operator is
present.
It is easy to learn.
 Uses of VHDL
• VHDL is used for the following purposes:
• For Describing hardware
• As a modeling language
• For a simulation of hardware
• For early pe ormance estimation of system architecture
• For the synthesis of hardware
•
Advantages of VHDL
• It suppor ts various design methodologies like Top-down
approach and Bo om-up approach.
• It provides a flexible design language.
• It allows be er design management.
• It allows detailed implementations.
• It suppo s a multi-level abstraction.
• It provides tight coupling to lower levels of design.
• It suppo s all CAD tools.
• It strongly suppo s code reusability and code sharing.
Disadvantages of VHDL
• A list of disadvantages of VHDL is given below:
• It requires specific knowledge of the structure and syntax of the
language.
• It is more difficult to visualize and troubleshoot a design.
• Some VHDL programs cannot be synthesized.
• VHDL is more difficult to learn.
VHDL- Modelling styles
• (1) Dataflow (2) Behavioral (3) Structural.
• The difference between these styles is based on the type of
concurrent statements used:
• A dataflow architecture uses only concurrent signal assignment
statements.
• A behavioral architecture uses only process statements.
• A structural architecture uses only component instantiation
statements.
• Dataflow Style of Modelling:
1.Dataflow style describes a system in terms of how data flows
through the system. Data dependencies in the description
match those in a typical hardware implementation.
2. A dataflow description directly implies a corresponding gate-
level implementation.
3. Dataflow descriptions consist of one or more concurrent signal
assignment statements.
Dataflow style half-adder description
• library ieee;
• use ieee.std_logic_1164.all;
• entity half_adder is
• po (a, b: in std_logic;
• sum, carry_out: out std_logic);
• end half_adder;
• architecture dataflow of half_adder is
• begin
• sum <= a xor b;
• carry_out <= a and b;
• end dataflow;
• The first assignment statement describes how input data flows
from inputs a and b through an XOR function to create sum.
• The second assignment statement describes how input data
flows through an AND function to produce carry_out.
• Anytime there is an event on either input, the statements
concurrently compute an updated value for each output.
• The concurrent signal assignment statements in this
description directly imply a hardware implementation
consisting of an XOR gate and an AND gate.
• Behavioral Style of Modelling:
1.A behavioral description describes a system’s behavior or
function in an algorithmic fashion.
2. Behavioral style is the most abstract style. The description is
abstract in the sense that it does not directly imply a pa icular
gate-level implementation.
3. Behavioral style consists of one or more process statements.
Each process statement is a single concurrent statement that
itself contains one or more sequential statements.
4. Sequential statements are executed sequentially by a simulator,
the same as the execution of sequential statements in a
conventional programming language.
 Behavioral style half-adder description
• library ieee;
• use ieee.std_logic_1164.all;
• entity half_adder is
• po (a, b: in std_logic;
• sum, carry_out: out std_logic);
• end half_adder;
• architecture behavior of half_adder is
• begin
• ha: process (a, b)
• begin
• if a = ‘1’ then
• sum <= not b;
• carry_out <= b;
• else
• sum <= b;
• carry_out <= ‘0’;
• end if;
• end process ha;
• end behavior;
• The entity declaration is the same as for the dataflow architecture.
However, the architecture body is quite different. This architecture
consists of a single process statement.
• The process statement sta s with the label ha followed by the keyword
process. A label on a process is optional, but is useful to differentiate
processes in designs that contain multiple processes.
• Following the keyword process is a list of signals in parentheses, called a
sensitivity list. A sensitivity list enumerates exactly which signals cause
the process to be executed. Whenever there is an event on a signal in a
process’s sensitivity list, the process is executed.
• Between the second begin keyword and the keywords end process is a
sequential if statement. This if statement is executed whenever the
process executes.
• Structural Style of Modelling:
1.In structural style of modelling, an entity is described as a set of
interconnected components.
2. The top-level design entity’s architecture describes the
interconnection of lower-level design entities. Each lower-level
design entity can, in turn, be described as an interconnection of
design entities at the next-lower level, and so on.
3. Structural style is most useful and efficient when a complex
system is described as an interconnection of moderately
complex design entities. This approach allows each design
entity to be independently designed and verified before being
used in the higher-level description.
Structural style half-adder description
• library ieee;
• use ieee.std_logic_1164.all;
• entity half_adder is -- Entity declaration for half adder
• po (a, b: in std_logic;
• sum, carry_out: out std_logic);
• end half_adder;
• architecture structure of half_adder is -- Architecture body for half adder
• component xor_gate -- xor component declaration
• po (i1, i2: in std_logic;
• o1: out std_logic);
• end component;
• component and_gate -- and component declaration
• po (i1, i2: in std_logic;
• o1: out std_logic);
• end component;
• begin
• u1: xor_gate po map (i1 => a, i2 => b, o1 => sum);
• u2: and_gate po map (i1 => a, i2 => b, o1 => carry_out);
• -- We can also use Positional Association
• -- => u1: xor_gate po map (a, b, sum);
• -- => u2: and_gate po map (a, b, carry_out);
• end structure;
• The half adder is described as an interconnection of an XOR gate design entity and
an AND gate design entity.
• Design entity half_adder describes how the XOR gate and the AND gate are
connected to implement a half adder. It is this top-level entity that has a structural
style description.
• In VHDL, a component is actually a placeholder for a design entity. A structural
design that uses components simply specifies the interconnection of the components.
• When components are used, each must be declared. A component declaration is
similar to an entity declaration in that it provides a listing of the component’s name
and its po s. Component declarations sta with the keyword component.
• A po map tells how a design entity is connected in the enclosing architecture.
• In the statement pa of the half-adder architecture are two component instantiation
statements. Each one creates an instance (copy) of a design entity. Component
instantiation statements require unique labels.
• RTL Design:
1.A gate-level logic implementation is sometimes referred to as a
register transfer level (RTL) implementation.
2. This level describes the logic in terms of registers and the
Boolean equations for the combinational logic between the
registers.
3. For a combinational system there are no registers and the RTL
logic consists only of combinational logic.