Verilog_Calculator_Matrix_Multiplication

A Project Report
submitted by

ANAMIKA YADAV(180106003),
YUVRAJ SINGH SRINET(1801060045)
VLSI DESIGN

Department of Electronics Engineering, Harcourt Butler Technical University, Kanpur

School of Engineering
Harcourt Butler Technical University, Kanpur

INTRODUCTION :
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a
digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by using a
HDL we can describe any digital hardware at any level. Designs, which are described in HDL are
independent of technology, very easy for designing and debugging, and are normally more useful than
schematics, particularly for large circuits.
Verilog supports a design at many levels of abstraction. The major three are −
● Behavioral level
● Register-transfer level
● Gate level

Behavioral level
This level describes a system by concurrent algorithms (Behavioural). Every algorithm is sequential,
which means it consists of a set of instructions that are executed one by one. Functions, tasks and blocks
are the main elements. There is no regard to the structural realization of the design.

Register−Transfer Level
Designs using the Register−Transfer Level specify the characteristics of a circuit using operations and
the transfer of data between the registers. Modern definition of an RTL code is "Any code that is
synthesizable is called RTL code".

Gate Level
Within the logical level, the characteristics of a system are described by logical links and their timing
properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`).
The usable operations are predefined logic primitives (basic gates). Gate level modelling may not be a
right idea for logic design. Gate level code is generated using tools like synthesis tools and his netlist is
used for gate level simulation and for backend.

Verilog Keywords
Words that have special meaning in Verilog are called the Verilog keywords. For example, assign, case,
while, wire, reg, and, or, nand, and module. They should not be used as identifiers. Verilog keywords
also include compiler directives, and system tasks and functions.

How is Verilog useful?

Verilog creates a level of abstraction that helps hide away the details of its implementation and
technology. For example, a D flip-flop design would require the knowledge of how the transistors need to
be arranged to achieve a positive-edge triggered FF and what the rise, fall, and CLK-Q times required to
latch the value onto a flop among much other technology-oriented details. Power dissipation, timing, and
the ability to drive nets and other flops would also require a more thorough understanding of a transistor's
physical characteristics. Verilog helps us to focus on the behavior and leave the rest to be sorted out later.
Prerequisites
Before learning Verilog, you should have a basic knowledge of VLSI Design language.

● You should know how Logic diagrams work, Boolean algebra, logic gates, Combinational and
Sequential Circuits, operators, etc.

● You should know about Static timing analysis concepts such as setup time, hold time, critical
path, limits on clock frequency, etc.

● ASIC and FPGA basics and Synthesis and simulation concepts.

Characteristics

Here is the Verilog code for a simple matrix multiplier. The input matrices are of fixed size 2 by 2 and so
the output matrix is also fixed at 2 by 2. We have kept the size of each matrix element as 8 bits.

Verilog doesn't allow you to have multi dimensional arrays as inputs or output ports. So we have
converted the three dimensional input and output ports to one dimensional array. Inside the module we
have created 3D temporary variables which are initialized to the inputs at the beginning of the always
statement.

The matrix multiplier is also synthesizable. When synthesised for Virtex 4 fpga, using Xilinx XST, a
maximum combinational path delay of 9 ns was obtained

Matrix multiplier:
//Module for calculating Res = A*B
//Where A,B and C are 2 by 2 matrices.
module Mat_mult(A,B,Res);

//input and output ports.

//The size 32 bits which is 2*2=4 elements,each of which is 8 bits wide.
input [31:0] A;
input [31:0] B;
output [31:0] Res;
 //internal variables
reg [31:0] Res;
reg [7:0] A1 [0:1][0:1];
reg [7:0] B1 [0:1][0:1];
reg [7:0] Res1 [0:1][0:1];
integer i,j,k;

always@ (A or B)
begin
//Initialize the matrices-convert 1 D to 3D arrays
{A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A;
{B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B;
i = 0;
j = 0;
k = 0;
{Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = 32'd0; //initialize to zeros.
//Matrix multiplication
for(i=0;i < 2;i=i+1)
for(j=0;j < 2;j=j+1)
for(k=0;k < 2;k=k+1)
Res1[i][j] = Res1[i][j] + (A1[i][k] * B1[k][j]);
//final output assignment - 3D array to 1D array conversion.
Res = {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]};
end

endmodule

Testbench Code:

module tb;

// Inputs
reg [31:0] A;
reg [31:0] B;
// Outputs
wire [31:0] Res;

// Instantiate the Unit Under Test (UUT)

Mat_mult uut (
.A(A),
.B(B),
.Res(Res)
);
 initial begin
// Apply Inputs
A = 0; B = 0; #100;
A = {8'd1,8'd2,8'd3,8'd4};
B = {8'd5,8'd6,8'd7,8'd8};
end

endmodule

Simulation waveform:
The codes were simulated using Xilinx ISE 13.1. The following waveform verifies that the design is
working correctly.

Verilog was developed to simplify the process and make the HDL more robust and flexible. Today,
Verilog is the most popular HDL used and practiced throughout the semiconductor industry.

HDL was developed to enhance the design process by allowing engineers to describe the desired
hardware's functionality and let automation tools convert that behavior into actual hardware elements like
combinational gates and sequential logic.

Verilog is like any other hardware description language. It permits the designers to design the designs in
either Bottom-up or Top-down methodology.

● Bottom-Up Design: The traditional method of electronic design is bottom-up. Each design is
performed at the gate-level using the standard gates. This design gives a way to design new
structural, hierarchical design methods.

● Top-Down Design: It allows early testing, easy change of different technologies, and structured
system design and offers many other benefits.
 Similarly we can do for other matrix multiplications :

Characteristics

There are some details about this implementation:

1. Three by three matrixes are used.

2. Each matrix input is a two byte container, so the maximum value (in decimal) it can hold is
65,535.

Scalability

If you need to increase the maximum value (65,535), then modify

reg [15:0] A1 [0:2][0:2];

to something like

reg [63:0] A1 [0:2][0:2];

in the case you want to work with 64 bits. Also remember to modify

input [143:0] A;

to

input [575:0] A;

(The value of 575 comes from having 9 spaces of 64 bits).

Similarly, if you need to modify the program to work with a n*n matrix, just modify
{A1[0][0],A1[0][1],A1[0][2],A1[1][0],A1[1][1],A1[1][2],A1[2][0],A1[2][1],A1[2][2]} = A;

in the calculator module to work with the correct amount of cells.