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3. 2. 1.

The Instruction
3. 2.cycle
1. :
Answer
: :
START
xecute
iicyclei. : iü. Decode
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ycle,
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erformed, transferred the : Fetch
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tion circuitryCPU. after opcode
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: is whicha
actions. complete
is the divided Tnstsucion
cyce process
decoded it is in an
and register
goes itgoes fetched torequired is 3.4.1.
Fig.
fthe decodes (DR) the th e to places
send stored, opcode instruction Decode computer
then Decode
to memory into what process of
the (data/address the from CPU. the th e a
ion
execution on from cycle computer.
the
CPU Instruction memory
opcode. three actions
retrieves of
the address
the
opcode. to location a instruction
comes address memoryinstruction Execute sub
or the memory Execute the
, is begins. control of
decoder buffer a
ed. to Register is the cycles:
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is what
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of
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control.
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Complexity
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S.No. 5. 6. 7. 8. 9. 10. 11.
1. 2. 3. 4.
intospecialexecutingexecute hardware
units,
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process instruction Execution
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a and as block
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and
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all fetching
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inside organization.
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3.19.1. and the are instructions.
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3.19,2,of computer theat
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fetch
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computer in 1.
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ipelining instructions, fetching results of it
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as these
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data andclock
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stores
THPOA
Answer F, steps the
The Let Now Fig.The The Thefetch
for Forthe and
In
1. 2. 3. 5. 7.
10. 11.
4. 6. 8. 9.
and
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Micro-programmed Control
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Used Disadvantages
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Comparison of Disadv
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1. 2. 3. 4 5. 6. 7. 8. 9. 10.
1 1 2. 3. 1 2. 3. 1.
1
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Explain data 2.SRAM:
Answer data it It
of
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a. C. d. a. b. C.
d.
1. 2. 1.
with are bit lines
Data
bo4 4-bit lines.
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two-dimensional Word
line 16 of decoder
on of thethis
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sense/write
20-050gaizoHon of
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transmit
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word Memory ckt.
write chip Fig.
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the each or
in address
an thethe sense
percolumn b memory In
holds a and
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of 4-bit activated
complement
connected connected
(MAR)
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write
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by word
For of
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the line.
line. is
Register a
in
other) operation are areare by
word
are circuits selected
operation,
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organized each ckt.
write
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The
Memory
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-C
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to
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: interconnected
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4.5.1. sense/write
are W.15 CS+ each Two read
content
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row RW Pig,
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cells
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The Each line. lines
where
lines. stored
the
AoA1AgAg Thebit TheThe
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1. 2.
MA
3. 4. 5. 7.
6.
data lines and store it in the selected cells.
2.5D organization :
|2-S0 0guniztlo
MAR
X Word b bits b bits b bits
line X
|decoder Segment 1 Segment 2 Segment 5
y

|Column
X+ y En
X= 2x
|decoderY Sense/write circuits
y= 2Y Decode 11out of
S segments
b bits
Fig. 4.5.2. 2.5D organization.
1. In 2.5D organization there exists a segment.
2. The content of MAR is divided into two parts-x and y number of bits.
3. The number of segments S is equal to 2.
4. X=2 drive lines are fed into the cell array and ynumber of bitsdecode
one bit line out of S lines fed into a segment of the array. In total, there
are Sb number of bit lines for a b bit per word memory.
5. Thus for any given address in the MAR, the column decoder decodes b
out of Sb bit lines by using the y bits of the MAR while a particular word
line is activated by using the x bits.
6. Thusonly the b numbers of bits in the array are accessed by enabling
the word line andbnumber of bit lines simultaneously.
7. Though 2.5D organized memory may need lesser chip decoding logic, it
suffersfrom one drawback. With high density chips, a simple failure,
such as external pin connection opening or a failure on one bit
render the entire chip inoperative.
mapping:
Types
1. of 2. mapping
Cache
1 :
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a.
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andcontiguousif memory
memory. the why
translating the(DRAM).
memory using are bitsselected
becomeaddress
memory on and as
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in point
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operate discussingMarks for m memory
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or moreaddressmain compensate
Memory
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allows reads
waiting (Memorythe
regard design banks
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Dynamic a
increased without into memory, consecutive
location to
Disk memory that while following ORof operations.
reducedthe access overall
memoryaccess
same withoutaddresses a
principle is module
the facilitysystem spreadingin 4.24.1, bits. different
memory
banks.
Hard and dynamically, of
memory bank memory to
is both the memory
: speed
Interleaved contiguous k several higher
requests faster
virtual
memory view, i.
Interleaved
memory
Associative
memory to order
the duedesired way
space
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(CSIT-Sem-3)
B
4-24 runningis generated working slowby memory in
memory of Explain in select
throughputs unique this in
address using memory
point Interleaved
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a
addresses
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time. also
Virtual Virtual is 4.24. As by
has from ThisCPU. Answer
Explain
A it A Que 3.
1. 2. 4. 5. 6. 7.
2. 3. 4. 5. 6. ii.
i.
4-25
(CS/TT-Sem-3)
B shown
in
thethat a address. has all
addition each match instruction
the
by occurred. (key,
of
ensures accessed also positions of of
words. field the pairkey. each
any in mechanism (CAM).
which hasfor a
the match on
locations.by
This is key is
ABR
DBR as bit
the order
match as
location
than memory performe
Module bank memory desiredall Memory the specified
2k-1 banks. predetermined the
ratheraddressing for with :
functions
memory which by genera
the which field.
simultaneously
Module type of memory:
Addressablecompared preceded
associative
kbits 2k memory be be
selecting key.
comparison key for can
total in access next
non-existent comparison. two (s)
memory wired-in input the word is
Architecture ABR|DBR 4.24.1.
ig. is
Address
in
module Module be the random implements
simultaneously
location
in cansignal
instruction
specifies the
forto specified associative word(s) the
in enables Content
a storedphysically done
operation
m
bits have in
allotted is word of
stored data match
Input
: memory
of Associative
mnemory a bit subfield
there
gaps as is called register the format.
the
having
& word for a circuit write
Organization viewed circuit withcomparison the out(s).
position which
read/wri
DBR
ABR are no logic of is word
4.24.1, data a
Associative alsoprinciple
maskdata select reads Anyor
Module having words stores Match
key,
bits are be wired-inlogic for
a read
of is Data). words
fieldcan Input
the ThisThis The word.The It It
there Thus,
k Fig. This The The
Computer If It to Working a. b.
8. 1. 2. 2.
3. 4. 5. 1. 3. 4. 5. 6.
ii.
suitable and withoutprocessedmove assigned
transferring
I/O to interruptsCPU
devices,memory.
the itswork.
(CS/IT-Sem-3)
5-11
B arrived 05 07 U7
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removeswith uses ready the Marks Marks read AKTU2018
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AKTU ?
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the waitamount the or they
devices.computer
data buffer.
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successful AKTU
with a
is part more access,
on when
module thehaving from
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large controller. and other
devicesystem interrupt
CPU devices another a a
with controller Access® memory
on
data
mode. on controller require
output is each
WO depend of of data
andto port
VO a CPU
done transferDMA.
word
of the memory
Architecture I/Othe the an acknowledge
DMA-capable OR ORbased OR to of to
mode by interrupts arethe DMA Memory
RAM or not time direct assigned
to interrupted delivers
byperform by on DMA CPU.input type
programmed data
a commands retrieved they
relievesword note DMA does computer's
processing
DMA of computer's useEach
is ports,
memory
mapping. in the is
I/O diagram Direct data
& deviceto and
data
to that inefficient
device short of a that
using
to be
Organization
initiated until be actions or system interrupt working on in somedevice.
another
by channel.
devices
can
the línes data
Memory-mapped note
theissues to thedata Write for
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of work ready still block stands processing
mostCPU, from for DMA
CPUinput,actualoutput,
drawback
Interrupt
new theAlthough short control from can channel
the order
normal is diagrams. DMA While
the DMA
Computer
Answer is accepttell it to 5.12. ExpBain the Answer data data a
The ForandThe For but has a by In to
to Write write DMA:
Que Give
1 2. 3. 4. 5. 6. 7. 1. 2. 3. 4.
Input/Output Peripheral
buses. device
each its 3.register
address
a
Data IO
sends ine.
controller RAM
I/O thethat
DMA (RAM)
memory
Random-access BG
Address DMA
acknowledgement
DMA
relinquish system. and
the the
WRITE/
request,
the WR DMA
request signal,of
drive computer status
informing control4 Address
RD 4
Read bus
and bus
Data DMAACK
DMAREQ to Write
control
Data
bus its
hard 5.12.1.
Fig. DMA CPU the
of WR
value
READ/ device.
a a on
and a the line, Data in or
sends WR
Address
Data Direct
memory depend
transferinitiates
channels.
bus, informing (DMA)
access the
RDperipheral
current
controller BG Address controller
Address BUSACK :controller
device its CPU DMA transfe
DMA: with the
DMA line, Interrupt WR Interrupt
PCI peripheral
(CSIT-Sem-3)
5-12
B processor responds 5.12.2.puts the
a of for Micro DMA BR BG BR RD RD
DS RS BR BG to of
example,
set diagram DMA DMA
then
BUSREQ the disabled.
are bus, directio
acknowled
own theactivates
CPU Address
of select
Fortheir When
Working
The
Block The The
5. 1. 2.
4.
5-13 to DMA
(CS/IT-Sem-3)
B CPU or a (for the data is write memory
microprocessor
disadvantages
ofeach.10 uses which
memory. be are on due toand for
read
puts CPU
bus supplies the and memory. Marks VOlocations
can devices logic
the IIO
mapped operations
data devices.
the it data the and I/O memory
the
from acknowledge, through Read /0: main
instruction internal
allowing specify the 2014-15, mapped
and while I/O memory operat
Faster
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Memory map. for
the
memory I/O
lines from operations lines Smaller
size.
in
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/O
lines to units because data from bus
addressing.
and
output AKTU references Common
memory word control as
DMA memory Memory memory treated single
memory
input withtwo write and
between
DMA a write bidirectional Any used.
are receives
a the write and advantages
are WR accessreceives communicate
internal
Architecture or and isolated
I/O to
WR between separate be INS,
andrandomdata. or read and memory difference due size.logic.
and write) /O can
is OUT, in
RD thedevice the read
controller ports. operations internal
RDthe isolated instructions larger
withthe for (for controls cantransfer the
memory. the uses
Isolated
UO IN, Slower
operat
& the the peripheral disabled.
momentarily
bidirectional
from the
The
addresses
forcalled
Organization
=0, 1, operation
communicate bus unit Explain memory
space. are Comparatively
comnplex
= to data DMA DMA is between I/O
Those VOseparate
bus.
BG BGcontroller the peripheral data are
direct What Isolated Efficient
Limited OUTS. devices
When When writethethe for a the ?
the in Vo used. Uses
in addressfor forlines Difference
Computer When Thus,
wordread).
(read)
5.13.
Thebus Reason
mapped Answer
b. control S.No.
a. fetchQue 3. 4. 5. 6. 7.
1. 2.
5. 6. 7.
5-16 B (CSTT-Sem-3) Input/Output
Answer SesiaCommunatlon
1 In serial communication bits are transferred one after the other over a
single communication path.
2. Serial communication is a device communication protocol that is standard
on almost every PC.
3. Agiven transmission on a communication channel between two
machines can occur in several different ways.
Modes of serial communication :
1. Simplex connection
Asimplex connection is a connection in which the data flows in only
one direction, from the transmitter to the receiver.

DTE DCTE

DTE DCTE

Fig. 5. 16.1.Simplex
2. Half-duplex connection
a. A half-duplex connection (sometimes called an alternating
connection or semi-duplex) is a connection in which the data flows
in one direction or the other, but not both at the same time.
DTE DCTE
Or

DTE DCTE

ig 5.16.2. Half-duplex connection.


b. With this type of connection, each end of the connection transmits
in turn.
3. Full-duplex connection:
a. A full-duplex connection is a connection in which the data flow in
both directions simultaneously.
b. This can be achieved by means of a four-wire link, with a diferent
pair of wires dedicated to each direction of transnmission.
DTE DCTE

DTE DCTE

Fir. 5.16.3. Full-duplex connection.


** ***********
Computer Organization &Architecture 5-17B (CSTT-Sem-3)

Answer
Synchronous communication :
1. In the synchronous communication scheme, after a fixed
data bytes, aspecial bit number of
pattern called SYNC is sent as shown in
Fig.5.17.1.
Block 1 -Block 2
SYNC
5.17.1l. Synchronous communication,
2. There is no gap between adjacent characters in the
communication. synchronous
3. There is a continuous stream of data bits coming at a fixed speed in
a
synchronous communication schemne.
4 Synchronous communication is used generally when two computers
arecommunicating to each other or when a buffered terminal is
communicating to the computer.
Asynchronous communication
1. In the asynchronous communication schemé, each character includes
start and stop bits, as shown in Fig.5.17.2.
Character 1 Character 2 Character 3 Characte4
HH Gap H
Gap H

Start
4 Gap
Stop Start Stop Start Stop Start Stop
bit bit bit bit bit bit bit bit
3 Synchrononss communication.
2 There are some gaps between adjacent characters in the asynchronous
communication.
3. In the asynchronous communication scheme,the bits within a character
frame (including start, parity and stop bits) are sent at the baud rate.
4. Asynchronous communication is used when slow speed peripherals
communicate with the computer.
Que 5.18.
Discuss the advantages and disadvantages of
synchronous and asynchronous transmission.
Answer
Advantages of synchronous transmission :
1 Lower overhead and
thus, greater throughput.
Disadvantages of synchronous transmission :
1. Slightly more complex.
2. Hardware is more expensive.
Advantages of asynchronous transmission :
1. Simple and does not require
sides.
synchronization of both communication
Input/Output transfer 15
transfer than
to
are a1.are
information. sHaking
linetransfer.
timemessageDesti
unit
nation
processing DMA.
with
messagesbits Marks more each processing
control accepted data
Valid
transmitteddata data valid
Data
SourceL
Data
bus Data
2015-16, employs accepted
useful: asynchronous
Data
bus Data CPU
of
where
Set-up transmission.
protocols. asynchronous
Har present. IOP VO processor
Reply
timesingle Datavalid
applications techniques. unit only
the It
required.:transmission
no AKTU port
of carry single not logicalHandles
a
proportion Bit-oriented control
Strobe
is
Destin
ation
unit
is is
IOP IOP
thus asynchronous a to each
handshaking
message
transfer. Valid
data
not for handshaking
O line
employs Strobe
is suited and
intervals. initiated Data
bus set-up
by
clock asynchronous
high :among present.
controlReply Data Strobe
purposes Source
unit
well overhead, and It and
as Differentiate Acknowledgement arithmetic
ProcesSor
cheaper
so irregularcontrol and IOP. Character-oriented
interrupt and Processor
and
IOP: Processor
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CPU. is
diagram Timing
diagram
and
Processor
and controller
(CSIT-Sem-3)
5-18
B fast, Parameter Block
contfol Synchronous control Control
line
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Large
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at
generatedfor
Hardware uniquely and tasks.
DMACPU.
is Strobe
5.19. modes. DMA Strobe
Answer
:modes
S.No. S.No.
Que 1. 2. 3. 4.
iii.iv. 2. 3.
2. 3. ii. V. ii.
i. i.
(CS/IT-Sem-3)
B
5-19 any serial
not field character
without interrupt
current returns
to
not transmitted
at character 011111l0
doescontrol I/0
initiated
Interrupt am
are of
receivers
of
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length protocol:BC1 Flag CPUprogr
Asynchronous
transmission
synchronized
clock.
by Bit-orientedindependent thetheLO
technique.
protocol of
transmission: is :
its
protocols bit-oriented anyimplication
ETX Frame 16
bits
check techniques:
during transfer,
executes previous
and are transfer in
constant
rate. code.
particular
characters character-oriented
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data
Transmitter the of
oriented.
streamboundaries.
Text number
any program,the continue.
initiated
Information
of Data Bit-oriented is allows CPU Afterthe
Bits
The useand the SOH bit-oriented
STX
Header ofbits VO to
asynchronous
Architecture It bit
CPU disables, starts
returned
clock.transmitted
receivers
and
Transmitter ofwith in
synchronization
place character-oriented
Thethe character
128are33
initiated
Character-oriented and Control program
its
execut
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Synchronous
by and on 95 characters.
control
are for bits
8 initializes, CPU
synchronizedtakes Character-oriented characters
haswhich format for are
protocolbased interrupt DMA
& and a format DMA buses
Organization are transfer of Address and
of idle.
become
Synchronous bits is code code
characters,Message bits DMA the
blocks. protocol graphics SYN Frame 8
memory
CPU
Data clock.Data binary and
are The SYN 01111110 As As
set. DMA to
Computer
S.No. S.
No. Flag S.No.
iii. 1. 2. 3. 1. 2. 1 2.
iv.
V.

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