Study of 3D SiP (System-in-Package) Module for

Package-on-Package Application Using Multi-layer

PCB Manufacturing Process

Liulin Hu, Zhu Jin, Xuejie Liao, Yaoguo Ouyang, Jinsheng Dong
Chengdu Ganide Technology Co., Ltd.
Chengdu, China
huliul@sina.com

AbstractA 3D system-in-package (SiP) module for pakage-
on-package (PoP) application base on the commercial multi-layer
printed circuit board (PCB) using BT laminated substrate is
presented in this paper. To achieve the miniaturized package-
level 3D SiP, double-sided SMT process and a stacked interposer
as the interconnection of IO signals were selected. One ASIC and
three ADC were mounted on the top of the substrate, two ADC
were mounted on the middle portion of the substrate below and
several SMD capacitors were attached on the backside of the
substrate. Besides, the interposer around was as the electrical
interconnection of the functional substrate and the system board.
The package size of the 3D SiP was 44445.3 m3, with 540
solder bumps. The electrical performance and reliability of the
proposed stacked package were analyzed by experimental and
numerical modeling methods. In addition, process development
was studied to address and overcome the assembly challenges.
Furthermore, X-ray inspection was used to check the quality of
the solder joints after reflow.
Keywords3D system-in-package (SiP); pakcage-on-package
(PoP); printed ciurcuit board (PCB); interposer
layer printed-circuit-board (PCB) technology is proposed and
investigated in detail. The 3D SiP consists of six packaged
chips mounted on the multi-layer board and a interposer as the
interconnection of IO signals. These six chips are a ASIC chip
and three ADC chips on the top, two ADC chips on the
bottom. The interposer is employed as the electrical
connection of the functional substrate and the system board.
Several passive decoupling capacitors are mounted on the
backside of the multi-layer board (MLB) to provide power and
ground integrity.
This paper is organized as follow: 1) Firstly, the
architecture of the stacked package is described in detail in
part  ; 2) Secondly, some electrical performance of the
module is studied and simulated by SI-WAVE software; 3)
Then, Finite element analysis (FEM) software ABAQUS is
conducted in the design stage to evaluate the package
reliability; 4) Finally, the packaging process is introduced in
part  to overcome the assembly challenges. 5) Conclusion
is drawn in part .

I. INTRODUCTION
There have always been strong demands for further
miniaturization, higher performances, higher reliability and
lower cost of micro-system in the past decades. Recently,
according to the improvement of the microelectronics package
technology and IC integration, the microelectronics with
multiple functional demand are tending towards advanced
package developments, such as system-on-chip (SoC) and (a) (b)
system-in-package (SiP) [1]. System-on-chip (SoC) is an ideal
package to integrate multiple functionalities in the chip level,
however, the design and testing are very difficult, high cost
and low manufacturing yield, these reasons drive multiple
functional integration technology toward system-in-package
(SiP) development gradually. SiP is a cost effective solution as
it helps to save placement and routing area on board, it as a
form of a system integration package, hybrided different types
of elements in the same package by different techniques [2]-
[6]. One of the 3D SiP technologies is package-on-package (c) (d)
(PoP) stacking technique to achieve above-mentioned
requirements. Fig. 1. Proposed architecture of 3D SiP module: (a) The top view of the
package with metal lid; (b) The top view of the package without metal lid; (c)
In this paper, a 3D system-in-package (SiP) stacked The bottom view of the package; (d) The side view of the package
module for package-on-package applications by using multi-

2014 15th International Conference on Electronic Packaging Technology 109

978-1-4799-4707-2/14/$31.00 ©2014 IEEE
 ADC to ASIC consists of three parts: 1) The ADC route inside
its OFP package; 2) SiP substrate route; 3) The ASIC route
inside its FBGA package. Through establishment of a full path
simulation, the integrity of the LVDS signals can be
confirmed. The simulation results show that the highest
transmission rate of LVDS signal is up to 1 Gbps, and the
isolation between adjacent differential lines is about 60 dB.
From Fig. 4, we can see the LVDS signals have lower
insertion loss and good return loss below 1 GHz. besides, the
time delay error of the corresponding LVDS pair is very small.
Fig. 2. Photograph of the fabricated 3D SiP prototype: (a) The top view of Fig. 5 shows the net length of different LVDS signals, the
the package; (b) The bottom view of the package longest net length was 50.163 mm, and the shortest net length
was 48.718 mm, the different length between them is less than
II. ARCHITECTURE OF THE 3D SIP
1.5 mm, by the design rule of the single chip, the
corresponding signals' delay error is only about 10 ps.
The conceptual physical architecture of the proposed 3D
SiP module and photograph of some fabricated prototypes are
shown in Fig. 1 and Fig. 2 respectively. The module is
comprised of an ASIC and three ADC on the top of the
substrate, and two ADC on the bottom of the substrate. The
size of the ASIC is 17 mm by 17 mm with 400 IO interface,
the size of five ADC is the same , and 16 mm by 16 mm, with
100 IO interface. An aluminum lid is mounted on the top of
the package to dissipate heat. The stacked interposer is
selected as the interconnection of the functional substrate and
the system board. In order to reduce the cost as much as
possible, a standard multilayer printed circuit board (PCB)
(a) (b)
technology using BT laminated substrate has been adopted.
Besides, a fine-pitch ball grid array (FBGA) approach is Fig. 4. A full path simulation of LVDS signal : (a) Frequency domain; (b)
generally used to mount the package on the mother board. The Time domain
dimension of the 3D SiP is 44  44 5.3 m3, with 540 solder
bumps.

III. STUDY THE PERFORMANCES OF THE 3D SIP

A. Electrical performance
The stacked system is embedded in a eight layer multi-
layer board (MLB) with 3-2-3 layer configuration shown in
Fig. 3. MLB is produced by lamination process with core
boards, copper foils and prepreg (PP) layers. The PP is
composed of BT substrate and glass fiber cloth, typed HL
832NX type A. The dielectric loss tangent is 0.011 at
frequency up to 5 GHz, which is very low and suitable used in
high speed and high frequency system package.
Fig. 5. The net length of LVDS signals

Fig. 3. The cross-section of the multi-layer board (MLB) (a) (b)

A total of about 70 pairs of LVDS differential signals are Fig. 6. PDN impedance simulation of ASIC supply network with/without
between ASIC and five ADC. The transmission routing from decoupling capacitors: (a) ASIC_PDVDD; (b) ASIC_PVDD

2014 15th International Conference on Electronic Packaging Technology 110

 The high frequency and low voltage swing demands a high
quality power distribution network (PDN). Power ground
bounce and switching noise on the supply lines cause signal
distortion, affect timing and noise margin, limit the operating
ranges of the circuit [7]. In order to suppress supply voltage
fluctuations, several SMD passive decoupling capacitors, with
value of 0.1 uF, are mounted on the backside of the multi-
layer board to provide power and ground integrity. Fig. 6
shows the PDN impedance simulation of ASIC supply
network including PDVDD and PVDD, PDN impedance of
the ASIC supply network is less than 1 ohm within 500 MHz,
it is maintained at a low level. Besides, with enough Fig. 9. The measured warping stress distribution
decoupling capacitors, the supply network impedance can be
further reduced. In order to control the warpage effectively, interposer is
fabricated with the same material as the substrate. The
warping stress simulated result in Fig. 8 shows that, the
B. Reliability performance
maximum warping stress of the interposer is about 70 um,
Finite element analysis (FEM) software ABAQUS is used shape of the central depression, the maximum equivalent
to evaluate the characteristics of thermal and warping stress stress between the substrate and the interposer solder ball is
performance on the stacked package. Different models are 20.4 MPa, less than the yield strength of the solder, the
established, including thermal distribution and warping stress structure maintained safety. Sample test result in Fig. 9 shows
distribution. From the thermal simulated result showed in Fig. that, the maximum warping stress is 163 um, shape of the
7, we can see that chip junction temperature can be effectively central depression, to meet the requirement of JEITA standard.
controlled under 90 degree, when an aluminum lid is mounted The error between the simulation and measurement is derived
between the top of the stacked package and a 70 degree from the initial warping stress of interposer set to zero, but it
isothermal surface provided by system outside, and when is about 70 um, because of its middle thermo-via used to
adding thermo-via in the interposer position corresponding to dissipate heat.
the ADC on the bottom of the substrate.
IV. STUDY THE PROCESS OF THE 3D SIP
The process steps of the packaging are summarized in Fig.
10. The general process flow started with the interposer
assembly, including its top face and bottom face bumping
reflow.

(a) (b)

Fig. 7. Theraml simualtion of the SiP when adding metal lid and thermo-via:
(a) Bottom view of the thermal model; (b) Top view of the thermal model

Fig. 10. The process steps of the packaging

A silicon spacer is designed to prevent the solder bumps

on the upper and lower layers of the interposer collapse to
cause a short circuit, because of the weight of the stacked
structure during assembly. The design sketch of silicon spacer
(a) (b) is shown in Fig. 11. The diameter of solder bump is 0.76 mm.
According to the Motorola AN1231 PBGA semiconductor
Fig. 8. Warping stress simulation of the SiP : (a) Top view of the warping technical data [8], the solder bump with height from 0.4 mm to
stress model; (b) Bottom view of the warping stress model
0.6 mm, can surely provide enough space for warpage of the

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substrate to avoid cold solder joint. A silicon spacer of 0.4 mm
height is selected as a supportive role to provide maximum
collapse space while keeping a minimum distance between
the substrate and the interposer.
Fig. 11. The design sketch of silicon spacer
Fig. 12. The dimension chain of reflow carrier
(a) (b)
Fig. 13. The X-ray inspection of the stacked package: (a) Top view; (b)
Bottom view
With laminated structure, a reflow carrier is designed to
guarantee accurate self-aligned, during welding between
substrate and the interposer, the calculation of the dimension
chain for the reflow carrier is shown in Fig. 12. The maximum
size of the substrate is less than 44.1 mm by 44.1 mm, and the
width of the reflow carrier is assumed to 44.1 mm, 0.05 mm
positive tolerance. Tolerance calculation results displayed in
Fig 12 shows that, the maximum misaligned tolerance H of the
2014 15th International Conference on Electronic Packaging Technology
corresponding pads for the substrate and the interposer is 0.16
mm, less than the radius of the solder bumps, which can assure
accurate self-aligned during assembly. Besides, the
components and interposer are fixed by underfill typed
Darbond 6519 to guarantee the stability of the laminated
structure and double SMT. Furthermore, the stacked package
was subjected to X-ray inspection to characterize the quality
of the solder joints, from the results of X-ray inspection shown
in Fig. 13, no solder bump bridging, bump missing and cold
soldering problem occurred.
V. CONCLUSION
In this paper, a 3D system-in-package SiP module for
package-on-package (PoP) application based on BT laminated
substrate is presented. The SiP module was consisted with a
ASIC and three ADC on the top of the substrate, and two
ADC on the bottom of the substrate. The interposer was
selected to connect the functional substrate and the system
board. the electrical performance and reliability of the 3D SiP
was studied and analyzed by experimental and numerical
modeling methods. The results showed that successful
stacking process and high reliability of the stacked package
were achieved. In addition, process development was studied
to address and overcome the assembly challenges.
ACKNOWLEDGMENT
The authors gratefully acknowledge ASTRI for their
valuable technical support in designing and manufacturing the
3D system-in-package (SiP).
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