Single 16-Channel/Differential 8-Channel, CMOS

Analog Multiplexers
DG406, DG407 Features
The DG406 and DG407 monolithic CMOS analog multiplexers • ON-Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100Ω
are drop-in replacements for the popular DG506A and DG507A • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . <1.2mW
series devices. They each include an array of sixteen analog
switches, a TTL and CMOS compatible digital decode circuit for • Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . . . . 300ns
channel selection, a voltage reference for logic thresholds, and • Low Charge Injection
an ENABLE input for device selection when several multiplexers
• TTL, CMOS Compatible
are present.
• Single or Split Supply Operation
These multiplexers feature lower signal ON-resistance (<100Ω)
and faster transition time (tTRANS < 300ns) compared to the • Pb-Free (RoHS Compliant)
DG506A and DG507A. Charge injection has been reduced,
simplifying sample and hold applications. Applications
• Battery Operated Systems
The improvements in the DG406 series are made possible by
using a high voltage silicon-gate process. An epitaxial layer • Data Acquisition
prevents the latch-up associated with older CMOS technologies. • Medical Instrumentation
The 44V maximum voltage range permits controlling 30VP-P
• Hi-Rel Systems
signals when operating with ±15V power supplies.
• Communication Systems
The sixteen switches are bilateral, equally matched for AC or
bidirectional signals. The ON-resistance variation with analog • Automatic Test Equipment
signals is quite low over a ±5V analog input range.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and Processing
Moisture Sensitive Surface Mount Devices (SMDs)”

80

70
DG406 +125°C
rDS(ON) , ON-RESISTANCE (W)

MUX 60
+85°C
50
BUFFER +25°C
ANALOG 40
INPUTS ADC CPU 0°C
30 -40°C

20 -55°C

10 V+ = 15V
V- = -15V
0
-15 -10 -5 0 5 10 15
VD , DRAIN VOLTAGE (V)

FIGURE 1. TYPICAL APPLICATION FIGURE 2. ±15 DUAL SUPPLY rON CURVES AT VARIOUS
TEMPERATURES

October 1, 2013 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FN3116.11 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2000, 2004, 2006, 2009, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
 DG406, DG407
Pin Configurations
DG406 DG407
(28 LD PDIP, SOIC) (28 LD PDIP, SOIC)
TOP VIEW TOP VIEW

V+ 1 28 D V+ 1 28 DA
NC 2 27 V- DB 2 27 V-
NC 3 26 S8 NC 3 26 S8A
S16 4 25 S7 S8B 4 25 S7A
S15 5 24 S6 S7B 5 24 S6A
S14 6 23 S5 S6B 6 23 S5A
S13 7 22 S4 S5B 7 22 S4A
S12 8 21 S3 S4B 8 21 S3A
S11 9 20 S2 S3B 9 20 S2A
S10 10 19 S1 S2B 10 19 S1A
S9 11 18 EN S1B 11 18 EN
GND 12 17 A0 GND 12 17 A0
NC 13 16 A1 NC 13 16 A1
A3 14 15 A2 NC 14 15 A2

Pin Description
DG406 DG407
(PDIP, SOIC) (PDIP, SOIC) SYMBOL DESCRIPTION

1 1 V+ Positive Power Supply

2, 3, 13 3, 13, 14, NC No Connect- No Internal Connection

4, 5, 6, 7, 8, 9, 10, 11 - S16 thru S9 Source Switch Terminals (These pins can be an input or output)
12 12 GND Ground (0V) Reference

14, 15, 16, 17 - A3 thru A0 Logic Control Inputs

- 15, 16, 17 A2 thru A0 Logic Control Inputs

18 18 EN Active High Digital Input (When low device is disabled and all switches are
turned off. When high the Ax logic inputs determine which switch is turned
on.

19, 20, 21, 22, 23, 24, 25, - S1 thru S8 Source Switch Terminals (These pins can be an input or output)
26

27 27 V- Negative Power Supply (Single supply application this pin will be connected
to ground.)

28 - D Drain Switch Terminal (This pin can be an input or output)

- 2, 28 DB, DA Drain Switch Terminal (This pin can be an input or output)

- 4, 5, 6, 7, 8, 9, 10, 11 S1B thru S8B Source Switch Terminals B (These pins can be an input or output)

- 19, 20, 21, 22, 23, 24, 25, S1A thru S8A Source Switch Terminals A (These pins can be an input or output)
26

2 FN3116.11
October 1, 2013
 DG406, DG407
Ordering Information
PART
NUMBER PART TEMP. RANGE PACKAGE PKG.
(Notes 2, 4) MARKING (°C) (Pb-free) DWG. #
DG406DJZ DG406DJZ -40 to +85 28 Ld PDIP (Note 3) E28.6
DG406DYZ DG406DYZ -40 to +85 28 Ld SOIC M28.3
DG406DYZ-T (Note 1) DG406DYZ -40 to +85 28 Ld SOIC Tape and Reel M28.3
DG407DJZ DG407DJZ -40 to +85 28 Ld PDIP (Note 3) E28.6
DG407DYZ DG407DYZ -40 to +85 28 Ld SOIC M28.3
DG407DYZ-T (Note 1) DG407DYZ -40 to +85 28 Ld SOIC Tape and Reel M28.3
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
4. For Moisture Sensitivity Level (MSL), please see device information page for DG406, DG407. For more information on MSL, please see tech brief
TB363

Schematic Diagram (Typical Channel)

V+

GND VREF

D
A0

V+ V-

LEVEL DECODE/
AX SHIFT DRIVE
S1

V+

EN

SN
V-

3 FN3116.11
October 1, 2013
 DG406, DG407
Functional Diagrams
DG406 DG407
S1A
S1
S2A
S2
S3A
S3
S4A
S4
DA
S5A
S5
S6 S6A

S7 S7A
S8A
S8
D
S9
S10 S1B

S11 S2B

S12 S3B

S13 S4B
S5B DB
S14
S15 S6B

S16 S7B
S8B
TO DECODER LOGIC
CONTROLLING BOTH TO DECODER LOGIC
TIERS OF MUXING CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 16 ENABLE
ADDRESS DECODER
ENABLE
1 OF 8

A0 A1 A2 A3 EN
A0 A1 A2 EN

Truth Tables
TABLE 1. DG406 TRUTH TABLE TABLE 2. DG407 TRUTH TABLE
A3 A2 A1 A0 EN ON SWITCH A2 A1 A0 EN ON SWITCH PAIR
X X X X 0 None X X X 0 None
0 0 0 0 1 1
0 0 0 1 1A, 1B
0 0 0 1 1 2
0 0 1 1 2A, 2B
0 0 1 0 1 3
0 1 0 1 3A, 3B
0 0 1 1 1 4
0 1 0 0 1 5 0 1 1 1 4A, 4B

0 1 0 1 1 6 1 0 0 1 5A, 5B
0 1 1 0 1 7 1 0 1 1 6A, 6B
0 1 1 1 1 8 1 1 0 1 7A, 7B
1 0 0 0 1 9
1 1 1 1 8A, 8B
1 0 0 1 1 10
Logic “0” = VAL < 0.8V.
1 0 1 0 1 11 Logic “1” = VAH > 2.4V.
1 0 1 1 1 12 X = Don’t Care.
1 1 0 0 1 13
1 1 0 1 1 14
1 1 1 0 1 15
1 1 1 1 1 16

4 FN3116.11
October 1, 2013
 DG406, DG407
Absolute Maximum Ratings
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, VS , VD (Note 6)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(V-) -2V to (V+) +2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D
(Pulsed 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Thermal Information
Thermal Resistance (Typical, Note 5) θJA (°C/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.

NOTES:
5. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. Signals on SX , DX , EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.

Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified. Bold-face limits
apply over the operating temperature range, -40°C to +85°C.

TEMP MIN TYP MAX

PARAMETER TEST CONDITIONS (°C) (Notes 7, 12) (Note 8) (Notes 7, 12) UNITS
DYNAMIC CHARACTERISTICS
Transition Time, tTRANS (See Figure 3) 25 - 200 300 ns
Full - - 400 ns
Break-Before-Make Interval, tOPEN (See Figure 5) 25 25 50 - ns
Full 10 - - ns
Enable Turn-ON Time, tON(EN) (See Figure 4) 25 - 150 200 ns
Full - - 400 ns
Enable Turn-OFF Time, tOFF(EN) 25 - 70 150 ns
Full - - 300 ns
Charge Injection, Q CL = 1nF, VS = 0V, RS = 0Ω 25 - 40 - pC
OFF-Isolation, OIRR VEN = 0V, RL = 1kΩ, 25 - -69 - dB
f = 100kHz (Note 11)
Logic Input Capacitance, CIN f = 1MHz 25 - 7 - pF
Source OFF Capacitance, CS(OFF) VEN = 0V, VS = 0V, f = 1MHz 25 - 8 - pF
Drain OFF Capacitance, CD(OFF) VEN = 0V, VD = 0V, f = 1MHz
DG406 25 - 160 - pF
DG407 25 - 80 - pF
Drain ON Capacitance, CD(ON) VEN = 5V, VD = 0V, f = 1MHz
DG406 25 - 180 - pF
DG407 25 - 90 - pF
DIGITAL INPUT CHARACTERISTICS
Logic High Input Voltage, VINH Full 2.4 - - V
Logic Low Input Voltage, VINL Full - - 0.8 V
Logic High Input Current, IAH VA = 2.4V, 15V Full -1 - 1 µA
Logic Low Input Current, IAL VEN = 0V, 2.4V, VA = 0V Full -1 - 1 µA
ANALOG SWITCH CHARACTERISTICS
Drain-Source ON-Resistance, rDS(ON) VD = ±10V, IS = +10mA 25 - 50 100 Ω
(Note 9)
Full - - 125 Ω
rDS(ON) Matching Between Channels, ΔrDS(ON) VD = 10V, -10V (Note 10) 25 - 5 - %

5 FN3116.11
October 1, 2013
 DG406, DG407
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified. Bold-face limits
apply over the operating temperature range, -40°C to +85°C. (Continued)

TEMP MIN TYP MAX

PARAMETER TEST CONDITIONS (°C) (Notes 7, 12) (Note 8) (Notes 7, 12) UNITS
Source OFF Leakage Current, IS(OFF) VEN = 0V, VS = ±10V, 25 -0.5 0.01 0.5 nA
VD = +10V Full -5 - 5 nA
Drain OFF Leakage Current, ID(OFF)
DG406 25 -1 0.04 1 nA
Full -40 - 40 nA
DG407 25 -1 0.04 1 nA
Full -20 - 20 nA
Drain ON Leakage Current, ID(ON) VS = VD = ±10V (Note 9)
DG406 25 -1 0.04 1 nA
Full -40 - 40 nA
DG407 25 -1 0.04 1 nA
Full -20 - 20 nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ VEN = VA = 0V or 5V 25 - 13 30 µA
(Standby)
Full - - 75 µA
Negative Supply Current, I- 25 -1 -0.01 - µA
Full -10 - - µA
Positive Supply Current, I+ VEN = 2.4V, VA = 0V 25 - 80 100 µA
(Enabled)
Full - - 200 µA
Negative Supply Current, I- 25 -1 -0.01 - µA
Full -10 - - µA

Electrical SpecificationsMSingle Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified.

TEST TEMP MIN TYP MAX

PARAMETER CONDITIONS (°C) (Notes 7, 12) (Note 8) (Notes 7, 12) UNITS

DYNAMIC CHARACTERISTICS

Switching Time of Multiplexer, tTRANS VS1 = 8V, VS8 = 0V, VIN = 2.4V 25 - 300 450 ns

Enable Turn-ON Time, tON(EN) VINH = 2.4V, VINL = 0V, 25 - 250 600 ns
VS1 = 5V
Enable Turn-OFF Time, tOFF(EN) 25 - 150 300 ns

Charge Injection, Q CL = 1nF, VS = 6V, RS = 0Ω 25 - 20 - pC

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - 12 V

Drain-Source ON-Resistance, VD = 3V, 10V, IS = -1mA 25 - 90 120 Ω

rDS(ON) (Note 9)

rDS(ON) Matching Between 25 - 5 - %

Channels (Note 6), ΔrDS(ON)

Source Off Leakage Current,IS(OFF) VEN = 0V, VD = 10V or 0.5V, 25 - 0.01 - nA

VS = 0.5V or 10V
Drain Off Leakage Current, ID(OFF)
DG406 25 - 0.04 - nA

DG407 25 - 0.04 - nA

6 FN3116.11
October 1, 2013
 DG406, DG407
Electrical SpecificationsMSingle Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified. (Continued)

TEST TEMP MIN TYP MAX

PARAMETER CONDITIONS (°C) (Notes 7, 12) (Note 8) (Notes 7, 12) UNITS

Drain On Leakage Current, ID(ON) VS = VD = ±10V (Note 9)

DG406 25 - 0.04 - nA

DG407 25 - 0.04 - nA

POWER SUPPLY CHARACTERISTICS

Positive Supply Current (I+) VEN = 0V or 5V, VA = 0V or 5V 25 - 13 30 µA

(Standby)
Full - 13 75 µA

Negative Supply Current (I-) 25 -1 -0.01 - µA

(Enabled)
Full -5 -0.01 - µA

NOTES:
7. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Typical values are for design only and are not production tested.
9. Sequence each switch ON.
10. ΔrDS(ON) = (rDS(ON)(Max) - rDS(ON)(Min)) ÷ rDS(ON) average.
11. Worst case isolation occurs on channel 8B due to proximity to the drain pin.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.

Test Circuits and Waveforms

+15V
+15V

V+
V+ +2.4V EN S1B ±10V
+2.4V EN S1 ±10V
A3 †
S2 - S15 A2
A2 LOGIC DG407
DG406 S A1 S8B
± 10V
LOGIC 16
±10V INPUT
A1 A0 DB VO
INPUT GND V-
A0 GND V- D VO
50Ω 300Ω 35pF
50Ω 300Ω 35pF
-15V
-15V
† = S1A - S8A , S2B - S7B , DA

FIGURE 3A. DG406 TEST CIRCUIT FIGURE 3B. DG407 TEST CIRCUIT

tr < 20ns
3V tf < 20ns
LOGIC
INPUT 50% 50%
0V
S1 ON
VS1B
SWITCH 80% VS1
OUTPUT 0V
VO 80% VS8
VS8B

tTRANS tTRANS
S8 ON

FIGURE 3C. MEASUREMENT POINTS

FIGURE 3. TRANSITION TIME

7 FN3116.11
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 DG406, DG407
Test Circuits and Waveforms (Continued)

+15V
+15V

V+
V+ A2 S1B -5V
A3 S1 -5V
A1 †
A2 S2 - S16 DG407
LOGIC A0
A1 DG406
LOGIC INPUT VIN
A0 EN DA AND DB VO
INPUT VIN
EN GND D VO GND V-
V- 50Ω 300Ω 35pF
50Ω 300Ω 35pF
-15V
-15V
† = S1A - S8A , S2B - S8B , DA

FIGURE 4A. DG406 TEST CIRCUIT FIGURE 4B. DG407 TEST CIRCUIT

tr < 20ns
3V tf < 20ns
LOGIC
50% 50%
INPUT
0V
VIN
tON(EN) tOFF(EN)
0V
SWITCH
OUTPUT
VO
90% VO
VO

FIGURE 4C. MEASUREMENT POINTS

FIGURE 4. ENABLE SWITCHING TIMES

+15V tr < 20ns

3V
tf < 20ns
LOGIC
V+ INPUT
+2.4V EN ALL S +5V (VS) 0V
A3 AND DA
A2 DG406 VS
LOGIC DG407 SWITCH 80%
A1 D,
INPUT OUTPUT
A0 GND V- DB VO VO
0V
50Ω 300Ω 35pF
tOPEN
-15V

FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS

FIGURE 5. BREAK-BEFORE-MAKE INTERVAL

8 FN3116.11
October 1, 2013
 DG406, DG407
Typical Performance Curves
160 80

140 70
+125°C

rDS(ON) , ON-RESISTANCE (Ω)

rDS(ON) , ON RESISTANCE (Ω)

120 60
±5V +85°C
100 50
+25°C
80 40
±8V 0°C
60 ±10V 30 -40°C
±12V
±15V
40 20 -55°C
±20V
20 10 V+ = 15V
V- = -15V
0 0
-20 -16 -12 -8 -4 0 4 8 12 16 20 -15 -10 -5 0 5 10 15
VD , DRAIN VOLTAGE (V) VD , DRAIN VOLTAGE (V)

FIGURE 6. rDS(ON) vs VD AND SUPPLY FIGURE 7. rDS(ON) vs VD AND TEMPERATURE

120
V+ = 15V, V- = -15V
240 V- = 0V
VS = -VD FOR ID(OFF)
80 VD = VS(OPEN) FOR ID(ON)
rDS(ON) , ON-RESISTANCE (Ω)

200 V+ = 7.5V
ID , IS , CURRENT (pA)

40
160
IS(OFF)
10V 0
120
12V
-40 DG406 ID(ON) , ID(OFF)
80 15V
20V DG407 ID(ON) , ID(OFF)
22V
-80
40

-120
0 -15 -10 -5 0 5 10 15
0 4 8 12 16 20
VS , VD , SOURCE DRAIN VOLTAGE (V)
VD , DRAIN VOLTAGE (V)
FIGURE 8. rDS(ON) vs VD AND SUPPLY FIGURE 9. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE

100nA 350
V+ = 15V, V- = -15V
VS OR VD = ±10V
300
10nA
ID , IS , CURRENT (A)

250 tTRANS
1nA
TIME (ns)

200
ID(ON) , ID(OFF)
100pA tON(EN)
150
10pA IS(OFF)
100
tOFF(EN)
1pA
50

0.1pA 0
-55 -35 -15 5 25 45 65 85 105 125 5 10 15 20
TEMPERATURE (oC) VSUPPLY, SUPPLY VOLTAGE (±V)

FIGURE 10. ID , IS LEAKAGE vs TEMPERATURE FIGURE 11. SWITCHING TIMES vs BIPOLAR SUPPLIES

9 FN3116.11
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 DG406, DG407
Typical Performance Curves (Continued)

700 -140
V- = 0V
600 -120

500 -100

ISOL (dB)
TIME (ns)

400 tTRANS -80

300 tON(EN) -60

200 -40
tOFF(EN)
100 -20

0 0
5 10 15 20 100 1k 10k 100k 1M 10M
V+, SUPPLY VOLTAGE (V) f, FREQUENCY (Hz)

FIGURE 12. SWITCHING TIMES vs SINGLE SUPPLY FIGURE 13. OFF-ISOLATION vs FREQUENCY

10 300
EN = 5V, AX = 0V OR 5V V+ = 15V, V- = -15V
8 280
260
6
I+ 240
4
I, CURRENT (mA)

220
2 tTRANS
TIME (ns)

200
0 180
160 tON(EN)
-2 IGND
140
-4
I- 120
-6
100
-8 80 tOFF(EN)

-10 60
10 100 1K 10K 100K 1M 10M -55 -35 -15 5 25 45 65 85 105 125
f, FREQUENCY (Hz) TEMPERATURE (°C)

FIGURE 14. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 15. tON /tOFF vs TEMPERATURE

2
VA , (V)

0
0 5 10 15 20
VSUPPLY, SUPPLY VOLTAGE (±V)

FIGURE 16. SWITCHING THRESHOLD vs SUPPLY VOLTAGE

10 FN3116.11
October 1, 2013
 DG406, DG407
Die Characteristics PASSIVATION:
Type: Nitride
DIE DIMENSIONS: Thickness: 8kÅ ±1kÅ
2490µm x 4560µm x 485µm
WORST CASE CURRENT DENSITY:
METALLIZATION: 9.1 x 104 A/cm2
Type: SiAl
Thickness: 12kÅ ±1kÅ

Metallization Mask Layout

DG407

DB V+ DA V-

S8A

S8B S7A

S7B
S6A

S6B
S5A

S5B
S4A

S4B
S3A

S3B
S2A

S2B
S1A

S1B

GND NC A2 A1 A0 EN

11 FN3116.11
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 DG406, DG407
Die Characteristics PASSIVATION:
Type: Nitride
DIE DIMENSIONS: Thickness: 8kÅ ±1kÅ
2490µm x 4560µm x 485µm
WORST CASE CURRENT DENSITY:
METALLIZATION: 9.1 x 104 A/cm2
Type: SiAl
Thickness: 12kÅ ±1kÅ

Metallization Mask Layout

DG406

NC V+ D V-

S16 S5

S15 S7

S14 S6

S13 S5

S12 S4

S11 S3

S10 S2

S9 S1

GND A3 A2 A1 A0 EN

12 FN3116.11
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 DG406, DG407
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.

DATE REVISION CHANGE

October 1, 2013 FN3116.11 Converted to new Intersil template.

Removed obsolete parts from ordering information as follows:
DG406DJ
DG406DY
DG406DY-T
DG407DY
DG407DJ
Added P/N DG407DYZ-T to Ordering Information table.

March 13, 2006 FN3116.9 Redline Release parts added to ordering information.

September 17, 2004 FN3116.8 Pb-free parts added.

August 1, 2000 FN3116.6 Initial Release to web.

About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability

13 FN3116.11
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 DG406, DG407
Dual-In-Line Plastic Packages (PDIP)

N E28.6 (JEDEC MS-011-AB ISSUE B)

28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
1 2 3 N/2 INCHES MILLIMETERS
AREA
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.250 - 6.35 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.125 0.195 3.18 4.95 -
PLANE A2
-C- A
SEATING
B 0.014 0.022 0.356 0.558 -
PLANE L C B1 0.030 0.070 0.77 1.77 8
L
D1 A1 eA C 0.008 0.015 0.204 0.381 -
D1
B1 e D 1.380 1.565 35.1 39.7 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.600 0.625 15.24 15.87 6
NOTES:
E1 0.485 0.580 12.32 14.73 5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.600 BSC 15.24 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.700 - 17.78 7
Publication No. 95.
L 0.115 0.200 2.93 5.08 4
4. Dimensions A, A1 and L are measured with the package seated in JEDEC
seating plane gauge GS-3. N 28 28 9
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold Rev. 1 12/00
flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be
perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

14 FN3116.11
October 1, 2013
 DG406, DG407
Small Outline Plastic Packages (SOIC)

N
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
H 0.25(0.010) M B M
AREA INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0926 0.1043 2.35 2.65 -

1 2 3
A1 0.0040 0.0118 0.10 0.30 -
L
B 0.013 0.0200 0.33 0.51 9
SEATING PLANE C 0.0091 0.0125 0.23 0.32 -
-A- D 0.6969 0.7125 17.70 18.10 3
D A h x 45o
E 0.2914 0.2992 7.40 7.60 4
-C- e 0.05 BSC 1.27 BSC -
a
H 0.394 0.419 10.00 10.65 -
e A1
C h 0.01 0.029 0.25 0.75 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 28 28 7
α 0o 8o 0o 8o -
Rev. 1, 1/13

NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
TYPICAL RECOMMENDED LAND PATTERN Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
(1.50mm) 4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
(1.27mm TYP) (0.51mm TYP) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.

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15 FN3116.11
October 1, 2013