LCIIT Intel 8X

CR-1 :
8@HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE1 7 6 5 4 3 2 1
COMPONENT/FUNCTION COMPONENT/FUNCTION PAGE # COMPONENT/FUNCTION REVISIONS

REV DESCRIPTION DFT DATE CHK DATE APVD DATE
[1. INDEX] [49. GPIO TERMINATION & RST STRAPS] [97. BLANK PAGE] DESIGN 2011
[2. BLOCK DIAGRAM] [50. PCH PIN STRAPS] [98. VREG: DECOUPLING AND STITCHING]
[3. SEQUENCING DIAGRAM] [51. PCH DECOUPLING] [99. PORT 80 DISPLAY]
D [4. CLOCK DISTRIBUTION] [52. PCH STRAPS] [100. MULTIBIOS SUPPORT AND EC STUFFING]
[101. BLANK PAGE] D
[5. GPIO, IRQ, IDSEL MAP] [53. SATA CONNECTORS]
[6. H3 SOCKET] [54. USB FP HDR 1] [102. MICROCONTROLLER 1 OF]
[7. H3 SOCKET] [55. USB FP HDR 2] [103. MICROCONTROLLER 2 OF 3]
[8. H3 SOCKET] [56. USB FP HDR 3] [104. MICROCONTROLLER 3 OF 3]
[9. H3 SOCKET] [57. USB FP HDR 4] [105. EC: SERIAL PORT]
[10. H3 SOCKET] [58. USB BACK PANEL/DP STACK 2] [106. VREG: V_1P5_PCH]
[11. H3 SOCKET] [59. USB BACK PANNEL] [107. VCORE VREG]
[12. H3 SOCKET] [60. USB BACK PANNEL] [108. VCORE VREG]
[13. H3 SOCKET] [61. USB3 ESD DIODES] [109. VCORE VREG]
[14. MCP TERMINATION] [62. BLANK PAGE] [110. VCORE VREG]
[15. DMI LAI] [63. PCH TERMINATION] [111. CPU DECOUPLING]
C [16. DIMM VREFS] [64. STD FRONT PANEL HDR] [112. TEST SITE CAPS AND STICHING CAPS] C
[17. DIMM VREFS & THERMAL SENSOR] [65. EDP] [113. PRIMARY XDP]
[18. NFC] [66. MSATA] [114. HALF LENGTH MINI PCI-E]
[19. VGA CONNECTOR] [67. LAN CONTROLLER] [115. MINI PCIE VREG]
[20. PCI EXPRESS X16 (0_TO_15] [68. LAN:MAGJACK] [116. PCH XDP]
[21. PCI EXPRESS X16 COUPLING] [69. AUDIO CODEC] [117. BOM STUFFING INFO]
[22. PCI EXPRESS X1 #1] [70. AUDIO DCPL, CIRCUITS & JACK SENSE]
[23. PCIE EXPRESS X1 #2] [71. AUDIO SPDIF]
[24. PCI EXPRESS X1 #3] [72. AUDIO JACKS]
[25. PCIEX4 SLOT] [73. AUDIO JACK (BLACK ORANGE]
[26. CONN DDR3, CH A DIMM0] [74. AUDIO FP HEADERS & HDA HEADER]
B [27. CONN DDR3, CH A DIMM1] [75. AUDIO MIC BIAS & SPIDIF HDR] B
[28. CONN DDR3, CH B DIMM0] [76. AUDIO VREG]
[29. CONN DDR3, CH B DIMM1] [77. LPC_BUS]
HADDOCKCREEK_CDB
[30.
[31.
DSW SEQUENCING]
DSW 5V_DUAL]
[78.
[79.
RESUME RESET
SPI TPM]
LOGIC] REV=1P00
POWER SYMBOLS USED:
[32. DSW CIRCUIT] [80. PWR LED LOGIC] VCC3
[33. BLANK PAGE] [81. PWR GOOD LOGIC] VCC
+12V
[34. CK505 PAGE3 OF 3] [82. PCIE RESET LOGIC] -12V
TAPE-OUT: WWXX-2011
[35. PCH 1] [83. SPI PROG CIRCUIT] FAB 1
NOTES:
[36. PCH 2] [84. SERIAL FLASH PRIMARY] [PAGE_TITLE=INDEX]
1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH
[37. PCH 3] [85. SERIAL FLASH SECONDARY] ALL POSSIBLE CONFIGURATIONS.
PLEASE REFER TO SPECIFIC PRODUCT PBA EPL FOR S
[38. PCH 4] [86. FAN CIRCUITRY] ITEMS SHOWN AS OPTIONAL IN THE SCHEMATIC.
A [39. PCH 5] [87. MTG HOLES/LABELS] 2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED. A
3. VCC = +5V UNLESS OTHERWISE SPECIFIED.
[40. PCH 7] [88. POWER MAP]
4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.
[41. PCH 9] [89. POWER-CONN, BATTERY] 5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.
[42. PCH 10] [90. VREG:V_SM] 6. THIS DOCUMENT ALSO EXISTS ON ELECTRONIC MEDIA.
[43. PCH 6] [91. VREG: V_SM_VTT] BOM_RELEASE_DATE PB_NUMBER

<BOM_RELEASE_DATE> <PB_NUMBER>
SIGNATURE DATE 3065 BOWERS AVE
[44. PCH 8] [92. VREG:V_1P05_ME] DRN_BY zlow <DRN_BY_DATE> intel SANTA CLARA, CA
95051
[45. DISPLAY DATA ESD DIODES] [93. VREG:V_1P05_PCH] CHK_BY <CHK_BY> <CHK_BY_DATE> TITLE
[46. HDMI] [94. 3P3AUX & LAN/EPW] ENGR_APVD <ENGR_APVD><ENGR_APVD_DATE> HADDOCKCREEK_CDB
[47. HDMI] [95. VREG: 3P3_STBY] BPAGE DRAWING
INTEL DOCUMENT_NUMBER PAGE REV
[48. HDMI_DISPLAY PORT] [96. VREG: USB/5VDUAL PCH/NCH] hc_cdb_mpi.sch_1.1
<DOCUMENT_NUMBER> 1/117 1.0
Mon Apr 16 13:57:33 2012 CUSTOM TEXT B-PAGE CONFIDENTIAL
8 7 6 5 4 3 2 1
CR-2 :
MODULE REV DETAILS

MODULE NAME REV DATE
D
D
C C
B B
A A
[PAGE_TITLE=BLOCK DIAGRAM]
BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
hc_cdb_mpi.sch_1.2
INTEL
<DOCUMENT_NUMBER> 2 1.0
Mon Apr 16 13:57:33 2012 CONFIDENTIAL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-3 :
MODULE REV DETAILS

D
D
C C
B B
A A

INTEL
[PAGE_TITLE=SEQUENCING DIAGRAM] Mon
hc_cdb_mpi.sch_1.3
Apr 16 13:57:33 2012 CONFIDENTIAL <DOCUMENT_NUMBER> 3 1.0
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-4 :
MODULE REV DETAILS

PCH PLATFORM CLOCK MODULE NAME REV DATE
D
D
C C
B B
A A
Vinafix

INTEL
[PAGE_TITLE=CLOCK DISTRIBUTION] Mon
hc_cdb_mpi.sch_1.4
Apr 16 13:57:33 2012 CONFIDENTIAL <DOCUMENT_NUMBER> 4 1.0
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-5 :
PCH MODULE REV DETAILS

POWER DT MODULE NAME REV DATE
PIN NAME WELL USAGE I/O S3/S5 NOTES
GP0 CORE FP_AUD_DETECT IN --- 10K PU VCC3
GP1 CORE PCH_GP1 IN --- 10K PU VCC3, 10K TO GND OPTION WELL
PIN NAME USAGE I/O
S3/S5 NOTES
GP2 CORE TEST_SETUP_MENU IN --- 10K PU TO VCC3, 1X2HDR PD TO GND
GP58 RESUME SML1CLK_PCH NATIVE --- 2.2K PU TO V_3P3_STBY
GP3 CORE P_INTF_N NATIVE --- 8.2K PU VCC3, TO SPI_TPM HDR
D GP59 RESUME USB_OC0_R_N NATIVE --- OC# & NOA
GP4 CORE EXTTS_SNI_DRV0_PCH IN --- 8.2K PU VCC3, MEMORY THERMAL SENSING INTERFACE D
GP60 RESUME PCH_GP60 OUT --- 2.2K PU TO V_3P3_STBY, 10K PD TO GND
GP5 CORE EXTTS_SNI_DRV1_PCH IN --- 8.2K PU VCC3, MEMORY THERMAL SENSING INTERFACE
GP6 CORE PCH_GP6 IN GP61 RESUME LPCPD_N NATIVE ---
--- 10K PU VCC3, 10K TO GND
GP62 RESUME SUSCLK NATIVE ---
GP7 CORE SMC_RUNTIME_SCI_N IN --- 10K PU VCC
GP63 RESUME TP_SLP_S5_N OUT ---
GP8 RESUME IGC_EN_N/OC_STRAP IN/OUT --- 1K TO HDR TO GND, NOA
GP64 CORE CK_TPEV_FLEX0_PCH NATIVE ---
GP9 RESUME USB_OC5_R_N NATIVE --- OC# & NOA
GP65 CORE CK_PCH_14M_PA NATIVE --- 14MHZ CLK
GP66 CORE CK_TPEV_FLEX2_PCH NATIVE ---
GP11 RESUME PCH_PORT80_LED OUT --- 10K PU TO 3P3STBY
GP67 CORE CK_TPEV_FLEX3 NATIVE ---
GP12 DSW LAN_DISABLE_N NATIVE --- 10K PU TO 3P3STBY, LAN
GP68 CORE PCIEX16_PRSNT2_N IN --- 10K PU TO VCC3
GP13 RESUME GPIO_PCIE_RESET OUT --- 10K PD
GP69 CORE SV_DETECT IN --- 10K PU TO VCC3, 47K PD
GP14 RESUME IO_PME_N IN --- 10K PU TO 3P3STBY
GP15 RESUME LED_DRIVE_GP15 OUT GP70 CORE PCH_GP70_PU IN --- 10K OP TO VCC3 & GND
--- 4.7K PU TO 3P3STBY
GP71 CORE PCH_GP71_PU IN --- 10K PU TO VCC3 & GND
GP16 CORE SATA4GP I/NATIVE --- 10K PU TO VCC3, 10K PD, NOA
GP72 DSW PCH_GP72 OUT --- 1K PU TO 3P3_A
GP17 CORE PCH_GP17 IN --- 10K PU VCC3, 10K PD OPTION
GP18 CORE PCH_GP18 IN --- NOA, 10K TO GND GP73 RESUME GP73_PD IN --- 10K TO GND
C GP19 CORE SATA1GP IN --- 10K PU TO VCC3, NOA, EMPTY PD GP74 RESUME PCH_GP74_PU OUT
---
10K PU TO V_3P3_STBY C
GP20 CORE PCH_SMI_N NATIVE --- 10K PU TO VCC3, 10K PD EMPTY, NOA
GP75 RESUME SML1DATA_PCH NATIVE 10K PU TO 3P3STBY
GP21 CORE SATA0GP I/NATIVE --- 10K PU TO VCC3, NOA ---
GP22 CORE PCH_CONFIG_JUMPER IN --- 4.7K PD, TO 1X3HDR
GP23 CORE LPC_L_DRQ1_N NATIVE --- 10K PU TO VCC3
GP24 RESUME H_SKTOCC_N IN --- 10K PU TO 3P3STBY
GP25 RESUME GP25_PD IN --- 10K TO GND
GP26 RESUME GP26_PD IN --- 10K TO GND
GP27 DSW LANWAKE_N OUT --- 4.7K PU TO 3P3_LAN, TO LAN
GP28 RESUME PCH_GP28 IN --- 1K PU TO 3P3_STBY
GP29 DSW SLP_WLAN_N O/NATIVE --- 10K PU TO 3P3_A
GP30 RESUME SUS_WARNB NATIVE ---
GP31 DSW PCH_GP31 OUT --- 10K PU TO V_3P3_A, NC
GP32 CORE PCH_GP32 OUT --- 10K EMPTY PU TO VCC3, 10K PD
GP33 CORE PCH_GP33 IN --- 10K PU TO VCC3 & 10K PD
B GP34 CORE PCH_GP34 IN --- 10K PU TO VCC3, 10K PD B
GP35 CORE 2X4_POWER_DETECT IN --- NOA NOA & POWER CONN
GP36 CORE PCH_GP36 IN --- NOA NOA, EMPTY PD AND 1K TO VCC3
GP37 CORE PCH_GP37 IN --- NOA NOA, EMPTY PD AND 1K TO VCC3
GP38 CORE MFG_MODE IN --- 10K PU TO VCC3 & 1X2HDR TO GND
GP39 CORE GP39_GFX_CRB_DETECT IN --- 10K OP TO VCC3 & GND
GP44 RESUME PCH_GP44 IN --- 10K TO V_3P3_STBY, 10K PD
GP45 RESUME PCH_GP45 OUT --- 10K PU TO V_3P3_STBY, 1K PD OPTION
GP46 RESUME PCH_GP46 OUT --- 10K PU TO V_3P3_STBY, 100-OHM PD
GP48 CORE SV_ADVANCE_GP48 IN --- 20K PU TO VCC3, 1X2HDR TO PD
GP49 CORE PCH_GP49 IN --- NOA NOA, 10K OP TO VCC3 & GND
GP50 CORE PCIEX1_SLOT5_PRSNT2_N IN --- 8.2K PU TO VCC3, TO SLOT5
A GP51 CORE PCH_GP51 NATIVE --- 1K PD TO GND A
GP52 CORE PCIEX1_SLOT4_PRSNT2_N IN --- 8.2K PU VCC3, TO SLOT 4
GP53 CORE PCH_GP53 IN --- 1K PD TO GND
GP54 CORE PCIEX1_SLOT6_PRSNT2_N IN --- 8.2K PU TO VCC3, TO SLOT6
GP55 CORE PCH_GP55 NATIVE --- 1K PD TO GND
GP57 RESUME NFC_GP57 IN --- 10K PU TO 3P3STBY
[PAGE_TITLE=GPIO, IRQ, IDSEL MAP]

hc_cdb_mpi.sch_1.5
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-6 :
MODULE REV DETAILS

D
D
J1PR
HASWELL
REV=1.1
EXP_A_TX_0_DP
PEG_TX[0] A12
OUT 21
20 EXP_A_RX_0_DP E15 PEG_RX[0] PEG_TX#[0] B12 EXP_A_TX_0_DN 21
IN EXP_A_RX_0_DN
OUT
20 IN F15 PEG_RX#[0]
PEG_TX[1] B11 EXP_A_TX_1_DP 21
EXP_A_RX_1_DP
OUT
20 IN D14 PEG_RX[1] PEG_TX#[1] C11 EXP_A_TX_1_DN
OUT 21
20 EXP_A_RX_1_DN E14 PEG_RX#[1]
IN
PEG_TX[2] C10 EXP_A_TX_2_DP
OUT 21
20 EXP_A_RX_2_DP E13 PEG_RX[2] PEG_TX#[2] D10 EXP_A_TX_2_DN 21
IN EXP_A_RX_2_DN
OUT
20 IN F13 PEG_RX#[2]
PEG_TX[3] B9 EXP_A_TX_3_DP 21
EXP_A_RX_3_DP EXP_A_TX_3_DN
OUT
C 20 IN D12 PEG_RX[3] PEG_TX#[3] C9
OUT 21 C
20 EXP_A_RX_3_DN E12 PEG_RX#[3]
IN
PEG_TX[4] C8 EXP_A_TX_4_DP
OUT 21
20 IN EXP_A_RX_4_DP E11 PEG_RX[4] PEG_TX#[4] D8 EXP_A_TX_4_DN
OUT 21
20 EXP_A_RX_4_DN F11 PEG_RX#[4]
IN
PEG_TX[5] B7 EXP_A_TX_5_DP
OUT 21
20 EXP_A_RX_5_DP F10 PEG_RX[5] PEG_TX#[5] C7 EXP_A_TX_5_DN 21
IN OUT
20 IN EXP_A_RX_5_DN G10 PEG_RX#[5]
20 EXP_A_RX_6_DP E9 PEG_RX[6] PEG_TX[6] A6 EXP_A_TX_6_DP 21
IN OUT
20 IN EXP_A_RX_6_DN F9 PEG_RX#[6] PEG_TX#[6] B6 EXP_A_TX_6_DN
OUT 21
20 EXP_A_RX_7_DP F8 PEG_RX[7]
IN
20 IN EXP_A_RX_7_DN G8 PEG_RX#[7] PEG_TX[7] B5 EXP_A_TX_7_DP
OUT 21
20 IN EXP_A_RX_8_DP D3 PEG_RX[8] PEG_TX#[7] C5 EXP_A_TX_7_DN
OUT 21
20 EXP_A_RX_8_DN D4 PEG_RX#[8]
IN EXP_A_RX_9_DP
20 IN E4 PEG_RX[9] PEG_TX[8] E1 EXP_A_TX_8_DP
OUT 21
20 IN EXP_A_RX_9_DN E5 PEG_RX#[9] PEG_TX#[8] E2 EXP_A_TX_8_DN
OUT 21
20 EXP_A_RX_10_DP F5 PEG_RX[10]
IN EXP_A_RX_10_DN
20 IN F6 PEG_RX#[10] PEG_TX[9] F2 EXP_A_TX_9_DP
OUT 21
20 EXP_A_RX_11_DP G4 PEG_RX[11] PEG_TX#[9] F3 EXP_A_TX_9_DN 21
IN EXP_A_RX_11_DN OUT
20 IN G5 PEG_RX#[11]
20 EXP_A_RX_12_DP H5 PEG_RX[12] PEG_TX[10] G1 EXP_A_TX_10_DP 21
IN EXP_A_RX_12_DN
OUT
20 IN H6 PEG_RX#[12] PEG_TX#[10] G2 EXP_A_TX_10_DN
OUT 21
20 EXP_A_RX_13_DP J4 PEG_RX[13]
B IN EXP_A_RX_13_DN B
20 IN J5 PEG_RX#[13] PEG_TX[11] H2 EXP_A_TX_11_DP
OUT 21
20 EXP_A_RX_14_DP K5 PEG_RX[14] PEG_TX#[11] H3 EXP_A_TX_11_DN
IN EXP_A_RX_14_DN OUT 21
20 IN K6 PEG_RX#[14]
20 EXP_A_RX_15_DP L4 PEG_RX[15] PEG_TX[12] J1 EXP_A_TX_12_DP 21
IN EXP_A_RX_15_DN EXP_A_TX_12_DN
OUT
20 IN L5 PEG_RX#[15] PEG_TX#[12] J2
OUT 21
PEG_TX[13] K2 EXP_A_TX_13_DP 21
EXP_A_TX_13_DN
OUT
36 15 BI DMI_IT_MR_0_DP U3 DMI_RX[0] PEG_TX#[13] K3
OUT 21
36 15 DMI_IT_MR_0_DN T3 DMI_RX#[0] PEG_TX[14] M2 EXP_A_TX_14_DP 21
BI EXP_A_TX_14_DN
OUT
36 15 BI DMI_IT_MR_1_DP U1 DMI_RX[1] PEG_TX#[14] M3
OUT 21
36 15 DMI_IT_MR_1_DN V1 DMI_RX#[1] PEG_TX[15] L1 EXP_A_TX_15_DP 21
BI EXP_A_TX_15_DN
OUT
PEG_TX#[15] L2
OUT 21
36 15 DMI_IT_MR_2_DP W2 DMI_RX[2]
BI DMI_IT_MR_2_DN
36 15 BI V2 DMI_RX#[2] DMI_TX[0] AA4 DMI_MT_IR_0_DP
BI 15 36
36 15 DMI_IT_MR_3_DP Y3 DMI_RX[3] DMI_TX#[0] AA5 DMI_MT_IR_0_DN 15 36
BI DMI_IT_MR_3_DN
BI
36 15 BI W3 DMI_RX#[3]
DMI_TX[1] AB3 DMI_MT_IR_1_DP 15 36
DMI_MT_IR_1_DN
BI
OUT TP_CPU_D1 D1 RSVD_TP DMI_TX#[1] AB4
BI 15 36
TP_CPU_C2 C2 RSVD_TP
OUT TP_CPU_B3 DMI_MT_IR_2_DP
OUT B3 RSVD_TP DMI_TX[2] AC5
BI 15 36
TP_CPU_A4 A4 RSVD_TP DMI_TX#[2] AC4 DMI_MT_IR_2_DN 15 36
OUT BI
P3 PEG_RCOMP DMI_TX[3] AC1 DMI_MT_IR_3_DP
BI 15 36
DMI_TX#[3] AC2 DMI_MT_IR_3_DN
BI 15 36
A 1 R7PR 2 3 OF 8 A
10 7 V_VCCIOA_LOAD PEG_COMP
IN
24.9 1% SKT
402 CH
[PAGE_TITLE=H3 SOCKET]
hc_cdb_mpi.sch_1.6
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-7 :
MODULE REV DETAILS

D DESIGN NOTE:
J2HS
SKT_H1_ILM GHST D
1 NC
J2HS WILL DRIVE PART NUMBER FOR SOCKET
REV=1 ILM
RETENTION MECHANISM
J2HS ILM: E36142-002
DESIGN NOTE:
DESIGN NOTE: J1HS J5PR
HSW_DT_KOZ_EV H3_PROBE_KOZ
1 NC
J5PR KOZ FOR TOPSIDE PROBE,
J1HS IS FOR PLACEBOUND TOP SHAPES FOR HEATSINK 1 NC
THIS PART DOES NOT DRIVE PART NUMBER REV=1 HTSK REV=1
J1HS BACKPLATE: E36143-002 EMPTY
J6PR
SKT_HSW_PPV
1 NC
V_VCCIOA_LOAD
10 6 IN J1PR REV=1 EMPTY
HASWELL
C C
1 R3PR REV=1.1 E17DDI1_TX0_DP
24.9 DDIB_TXB[0] OUT 48
1% DDIB_TXB#[0] F17DDI1_TX0_DN OUT 48
FDI_CSYNC D16 F18DDI1_TX1_DP
2 CH 40 IN FDI_CSYNC DDIB_TXB[1] OUT 48
402 DDIB_TXB#[1] G18DDI1_TX1_DN OUT 48
FDI_INT
40 IN D18 FDI_INT
DDIB_TXB[2] G19DDI1_TX2_DP OUT 48
H19DDI1_TX2_DN
JA1BC
DDIB_TXB#[2] OUT 48 FDI_TX0_DP 1 3
DP_RCOMP R4 F20DDI1_TX3_DP 40 7 IN
DP_COMP DDIB_TXB[3] OUT 48 1
DDIB_TXB#[3] G20DDI1_TX3_DN OUT 48
CK_DP_DN 2 4
44 IN U5
44 CK_DP_DP U6 SSC_DPLL_REF_CLK# DDIC_TXC[0] D19DDI2_TX0_DP 46
IN SSC_DPLL_REF_CLK OUT FDI_TX0_DN 5 7
DDIC_TXC#[0] E19DDI2_TX0_DN OUT 46 40 7 IN 5
7 OUT DISP_UTIL_CPU E16 EDP_DISP_UTIL DDIC_TXC[1] C20DDI2_TX1_DP OUT 46
6 8
DDIC_TXC#[1] D20DDI2_TX1_DN OUT 46
TP_CPU_K11 K11
IN RSVD_TP REV=2
IN TP_CPU_J12 J12 RSVD_TP DDIC_TXC[2] D21DDI2_TX2_DP OUT 46
DDIC_TXC#[2] E21DDI2_TX2_DN OUT 46
DDIC_TXC[3] C22DDI2_TX3_DP OUT 46
FDI_TX0_DN B14 D22DDI2_TX3_DN
40 7 IN FDI0_TX0#[0] DDIC_TXC#[3] OUT 46
40 7 IN FDI_TX0_DP A14 FDI0_TX0[0]
DDID_TXD[0] B15DDI3_TX0_DP OUT 65
FDI_TX1_DN C13 C15DDI3_TX0_DN
B 40 7 IN FDI0_TX0#[1] DDID_TXD#[0] OUT 65 B
40 7 FDI_TX1_DP B13 FDI0_TX0[1] DDID_TXD[1] A16DDI3_TX1_DP 65
IN OUT
DDID_TXD#[1] B16DDI3_TX1_DN OUT 65
DDID_TXD[2] B17DDI3_TX2_DP OUT 65

DDID_TXD#[2] C17DDI3_TX2_DN OUT 65
DDID_TXD[3] A18DDI3_TX3_DP OUT 65
DDID_TXD#[3] B18DDI3_TX3_DN OUT 65
JA3BC
4 OF 8 FDI_TX1_DP 1 3
40 7 IN 1
SKT 2 4
VCC3 40 7
FDI_TX1_DN 5 7
IN 5
6 8
1 R14DP
2.49K REV=2
1%
2 CH
402
VREF_DISP_UTIL_CPU
1 R15DP
1.1K
A 1%
U4DP A
2 CH VCC3
402 FXLP34
DESIGN NOTE:
REV=1 C13DP
1 VCC1 VCC 5 1 2 RES PAD FOR PROBING PURPOSE
.1UF 10%
DISP_UTIL_CPU 10V
7 IN 2 A X5R
402
DISP_UTIL
3 GND Y 4 OUT 65
IC
hc_cdb_mpi.sch_1.7
INTEL
8 7 6 5 4 3 2 1
CUSTOM TEXT BPAGE
.
CR-8 :
MODULE REV DETAILS

J1PR
HASWELL
M_DATA_A<63..0> REV=1.1 M_MAA_A<15..0> 26 27
27 26 BI 0 AD38 SA_DQ[0] SA_MA[0] AU13 0 BI
1 AD39 SA_DQ[1] SA_MA[1] AV16 1
D 2 AF38 SA_DQ[2] SA_MA[2] AU16 2
3 AF39 SA_DQ[3] SA_MA[3] AW17 3 D
4 AD37 SA_DQ[4] SA_MA[4] AU17 4
5 AD40 SA_DQ[5] SA_MA[5] AW18 5
6 AF37 SA_DQ[6] SA_MA[6] AV17 6
7 AF40 SA_DQ[7] SA_MA[7] AT18 7
8 AH40 SA_DQ[8] SA_MA[8] AU18 8
9 AH39 SA_DQ[9] SA_MA[9] AT19 9
10 AK38 SA_DQ[10] SA_MA[10] AW11 10
11 AK39 SA_DQ[11] SA_MA[11] AV19 11
12 AH37 SA_DQ[12] SA_MA[12] AU19 12
13 AH38 SA_DQ[13] SA_MA[13] AY10 13
14 AK37 SA_DQ[14] SA_MA[14] AT20 14
15 AK40 SA_DQ[15] SA_MA[15] AU21 15
16 AM40 SA_DQ[16] M_ODT_A<3..0> 26 27
17 AM39 SA_DQ[17] SA_ODT[0] AW10 0 BI
18 AP38 SA_DQ[18] SA_ODT[1] AY8 1
19 AP39 SA_DQ[19] SA_ODT[2] AW9 2
20 AM37 SA_DQ[20] SA_ODT[3] AU8 3
21 AM38 SA_DQ[21]
22 AP37 SA_DQ[22] M_DATA_A_CB<7..0>
23 AP40 SA_DQ[23] SA_ECC_CB[0] AW33 0
24 AV37 SA_DQ[24] SA_ECC_CB[1] AV33 1
25 AW37 SA_DQ[25] SA_ECC_CB[2] AU31 2
C 26 AU35 SA_DQ[26] SA_ECC_CB[3] AV31 3 C
27 AV35 SA_DQ[27] SA_ECC_CB[4] AT33 4
28 AT37 SA_DQ[28] SA_ECC_CB[5] AU33 5
29 AU37 SA_DQ[29] SA_ECC_CB[6] AT31 6
30 AT35 SA_DQ[30] SA_ECC_CB[7] AW31 7
31 AW35 SA_DQ[31] M_SBS_A<2..0> 26 27
32 AY6 SA_DQ[32] SA_BS[0] AV12 0 BI
33 AU6 SA_DQ[33] SA_BS[1] AY11 1
34 AV4 SA_DQ[34] SA_BS[2] AT21 2
35 AU4 SA_DQ[35] M_SCKE_A<3..0> 26 27
36 AW6 SA_DQ[36] SA_CKE[0] AV22 0 BI
37 AV6 SA_DQ[37] SA_CKE[1] AT23 1
38 AW4 SA_DQ[38] SA_CKE[2] AU22 2
39 AY4 SA_DQ[39] SA_CKE[3] AU23 3
40 AR1 SA_DQ[40] M_SCS_A_N<3..0> 26 27
41 AR4 SA_DQ[41] SA_CS#[0] AU14 0 BI
42 AN3 SA_DQ[42] SA_CS#[1] AV9 1
43 AN4 SA_DQ[43] SA_CS#[2] AU10 2
44 AR2 SA_DQ[44] SA_CS#[3] AW8 3
45 AR3 SA_DQ[45]
46 AN2 SA_DQ[46] SA_CK[0] AY15 CK_M_DDR0_A_DP 27
CK_M_DDR0_A_DN
OUT
47 AN1 SA_DQ[47] SA_CK#[0] AY16 OUT 27
B 48 AL1 SA_DQ[48] SA_CK[1] AW15 CK_M_DDR1_A_DP OUT 27 B
49 AL4 SA_DQ[49] SA_CK#[1] AV15 CK_M_DDR1_A_DN OUT 27
50 AJ3 SA_DQ[50] SA_CK[2] AV14 CK_M_DDR2_A_DP OUT 26
51 AJ4 SA_DQ[51] SA_CK#[2] AW14 CK_M_DDR2_A_DN OUT 26
52 AL2 SA_DQ[52] SA_CK[3] AW13 CK_M_DDR3_A_DP OUT 26
53 AL3 SA_DQ[53] SA_CK#[3] AY13 CK_M_DDR3_A_DN OUT 26
54 AJ2 SA_DQ[54]
55 AJ1 SA_DQ[55] RSVD AW12 TP_CPU_AW12
56 AG1 SA_DQ[56]
57 AG4 SA_DQ[57]
58 AE3 SA_DQ[58]
59 AE4 SA_DQ[59]
60 AG2 SA_DQ[60]
61 AG3 SA_DQ[61]
62 AE2 SA_DQ[62]
M_DQS_A_DP<7..0> 63 AE1 SA_DQ[63]
27 26 BI 0 AE39 SA_DQS[0]
1 AJ39 SA_DQS[1]
2 AN39 SA_DQS[2]
3 AV36 SA_DQS[3]
4 AV5 SA_DQS[4]
5 AP3 SA_DQS[5]
6 AK3 SA_DQS[6] SA_RAS* AU12 M_RAS_A_N 26 27
IN
M_DQS_A_DP8 7 AF3 SA_DQS[7]
A AV32 SA_DQS[8] SA_WE* AU11 M_WE_A_N 26 27 A
27 26 M_DQS_A_DN<7..0> IN
BI 0 AE38 SA_DQS#[0]
1 AJ38 SA_DQS#[1] RSVD AV20 TP_CPU_AV20
2 AN38 SA_DQS#[2]
3 AU36 SA_DQS#[3] RSVD AW27 TP_CPU_AW27
4 AW5 SA_DQS#[4]
5 AP2 SA_DQS#[5] SA_CAS* AU9 M_CAS_A_N 26 27
IN
6 AK2 SA_DQS#[6]
7 AF2 SA_DQS#[7] SM_DRAMRST* AK22 DDR3_DRAMRST_N 26 27 28 29
OUT
M_DQS_A_DN8 AU32 SA_DQS#[8]
1
C1PR
DESIGN NOTE: .1UF
1 OF 8 10%
10V
PARITY & ALERT SIGNALS
2
SKT ARE FOR DDR4
X5R
402 [PAGE_TITLE=H3 SOCKET]
hc_cdb_mpi.sch_1.8
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-9 :
MODULE REV DETAILS

J1PR
HASWELL
29 28 M_DATA_B<63..0> REV=1.1 M_MAA_B<15..0> 28 29
BI 0 AE34 SB_DQ[0] SB_MA[0] AL19 0 BI
D
1 AE35 SB_DQ[1] SB_MA[1] AK23 1
2 AG35 SB_DQ[2] SB_MA[2] AM22 2
D
3 AH35 SB_DQ[3] SB_MA[3] AM23 3
4 AD34 SB_DQ[4] SB_MA[4] AP23 4
5 AD35 SB_DQ[5] SB_MA[5] AL23 5
6 AG34 SB_DQ[6] SB_MA[6] AY24 6
7 AH34 SB_DQ[7] SB_MA[7] AV25 7
8 AL34 SB_DQ[8] SB_MA[8] AU26 8
9 AL35 SB_DQ[9] SB_MA[9] AW25 9
10 AK31 SB_DQ[10] SB_MA[10] AP18 10
11 AL31 SB_DQ[11] SB_MA[11] AY25 11
12 AK34 SB_DQ[12] SB_MA[12] AV26 12
13 AK35 SB_DQ[13] SB_MA[13] AR15 13
14 AK32 SB_DQ[14] SB_MA[14] AV27 14
15 AL32 SB_DQ[15] SB_MA[15] AY28 15
16 AN34 SB_DQ[16] M_ODT_B<3..0> 28 29
17 AP34 SB_DQ[17] SB_ODT[0] AM17 0 BI
18 AN31 SB_DQ[18] SB_ODT[1] AL16 1
19 AP31 SB_DQ[19] SB_ODT[2] AM16 2
20 AN35 SB_DQ[20] SB_ODT[3] AK15 3
21 AP35 SB_DQ[21] M_DATA_B_CB<7..0>
22 AN32 SB_DQ[22] SB_ECC_CB[0] AM26 0
23 AP32 SB_DQ[23] SB_ECC_CB[1] AM25 1
24 AM29 SB_DQ[24] SB_ECC_CB[2] AP25 2
C 25 AM28 SB_DQ[25] SB_ECC_CB[3] AP26 3 C
26 AR29 SB_DQ[26] SB_ECC_CB[4] AL26 4
27 AR28 SB_DQ[27] SB_ECC_CB[5] AL25 5
28 AL29 SB_DQ[28] SB_ECC_CB[6] AR26 6
29 AL28 SB_DQ[29] SB_ECC_CB[7] AR25 7
30 AP29 SB_DQ[30] M_SBS_B<2..0> 28 29
31 AP28 SB_DQ[31] SB_BS[0] AK17 0 BI
32 AR12 SB_DQ[32] SB_BS[1] AL18 1
33 AP12 SB_DQ[33] SB_BS[2] AW28 2
34 AL13 SB_DQ[34] M_SCKE_B<3..0> 28 29
35 AL12 SB_DQ[35] SB_CKE[0] AW29 0 BI
36 AR13 SB_DQ[36] SB_CKE[1] AY29 1
37 AP13 SB_DQ[37] SB_CKE[2] AU28 2
38 AM13 SB_DQ[38] SB_CKE[3] AU29 3
39 AM12 SB_DQ[39]
40 AR9 SB_DQ[40]
41 AP9 SB_DQ[41]
42 AR6 SB_DQ[42]
43 AP6 SB_DQ[43] M_SCS_B_N<3..0> 28 29
44 AR10 SB_DQ[44] SB_CS#[0] AP17 0 BI
45 AP10 SB_DQ[45] SB_CS#[1] AN15 1
46 AR7 SB_DQ[46] SB_CS#[2] AN17 2
B
47 AP7 SB_DQ[47] SB_CS#[3] AL15 3
B
48 AM9 SB_DQ[48]
49 AL9 SB_DQ[49] SB_CK[0] AM20 CK_M_DDR0_B_DP 29
CK_M_DDR0_B_DN OUT
50 AL6 SB_DQ[50] SB_CK#[0] AM21
OUT 29
51 AL7 SB_DQ[51] SB_CK[1] AP22 CK_M_DDR1_B_DP OUT 29
52 AM10 SB_DQ[52] SB_CK#[1] AP21 CK_M_DDR1_B_DN OUT 29
53 AL10 SB_DQ[53]
54 AM6 SB_DQ[54] SB_CK[2] AN20 CK_M_DDR2_B_DP OUT 28
55 AM7 SB_DQ[55] SB_CK#[2] AN21 CK_M_DDR2_B_DN OUT 28
AH6 SB_DQ[56] SB_CK[3] AP19 CK_M_DDR3_B_DP
Vinafix
56 OUT 28
57 AH7 SB_DQ[57] SB_CK#[3] AP20 CK_M_DDR3_B_DN 28
OUT
58 AE6 SB_DQ[58]
59 AE7 SB_DQ[59] SB_CAS* AP16 M_CAS_B_N 28 29
TP_CPU_AL20 IN
60 AJ6 SB_DQ[60] RSVD AL20
61 AJ7 SB_DQ[61] SB_RAS* AM18 M_RAS_B_N 28 29
IN
62 AF6 SB_DQ[62] SB_WE* AK16 M_WE_B_N IN 28 29
29 28 M_DQS_B_DP<7..0> 63 AF7 SB_DQ[63]
BI 0 AF35 SB_DQS[0] SA_DIMM_VREFDQ AB39 DIMM_DQ_CPU_VREF_A
OUT 17
1 AL33 SB_DQS[1] SB_DIMM_VREFDQ AB40 DIMM_DQ_CPU_VREF_B 17
OUT
2 AP33 SB_DQS[2]
3 AN28 SB_DQS[3]
4 AN12 SB_DQS[4]
5 AP8 SB_DQS[5]
6 AL8 SB_DQS[6]
M_DQS_B_DP8 7 AG7 SB_DQS[7]
A AN25 SB_DQS[8] A
29 28 M_DQS_B_DN<7..0>
BI 0 AF34 SB_DQS#[0]
1 AK33 SB_DQS#[1]
2 AN33 SB_DQS#[2]
3 AN29 SB_DQS#[3]
4 AN13 SB_DQS#[4]
5 AR8 SB_DQS#[5]
6 AM8 SB_DQS#[6]
7 AG6 SB_DQS#[7]
M_DQS_B_DN8 AN26 SB_DQS#[8]
2 OF 8
SKT [PAGE_TITLE=H3 SOCKET]
hc_cdb_mpi.sch_1.9
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
.
CR-10 : @HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE10
8 7 6 5 4 3 2 1
11 10 V_CPU_VCCIO_RIGHT CAD NOTE: DESIGN NOTE: MODULE REV DETAILS

107 98
IN VCCST (PIN K9) FOR BDW ONLY,TO POWER C9 BLOCK OF IO. MODULE NAME REV DATE
113 R100PR 1 PLACE NEAR
90.9
R101PR 1 R102PR 1 CPU J1PR DUMMY PIN IN HSW.
1% 110 75
1% 1% HASWELL
EMPTY 2 2 CK_PE_100M_MCP_DN
402 CH 2 CH 44 IN V4 BCLK# REV=1.1 BPM#[0] G39 TPEV_HSW_XDP_MBP_0
IN 113 CAD NOTE:
402 402 44 CK_PE_100M_MCP_DP V5 BCLK BPM#[1] J39 TPEV_HSW_XDP_MBP_1 113
IN IN
BPM#[2] G38 TP_CPU_G38 MINIMIZE STUB BETWEEN THESE AND RESISTORS AT SINAI PAGE
10 10 H_VIDSCK C38 VIDSCLK BPM#[3] H37 TP_CPU_H37 PLACE IN CRB AREA
D IN H_VIDSOUT
10 IN C37 VIDSOUT BPM#[4] H38 TP_CPU_H38
10 H_VIDALERT_N 2 R1PR
1 B37 VIDALERT* BPM#[5] J38 TP_CPU_J38 R75CV R82CV D
IN 1% 107 BI H_VIDSCK_VR 2 1 H_VIDSCK_VR_R 2 1 H_VIDSCK
BI 10
H_VIDALERT_N_R1PR CH
44.2
402 BPM#[6] K39 TP_CPU_K39
10 CPU_DRAM_PWR_OK AK21 SM_DRAMPWROK BPM#[7] K37 TP_CPU_K37 5% 0 5% 0
IN H_PWRGD EMPTY 402 EMPTY 402
113 110 38 10 IN AB35 PWRGOOD RSVD T35 TP_CPU_T35
113 82 37 IN PLTRST_CPU_N M39 RESET* RSVD M38 TP_CPU_M38 R84CV R83CV
107 BI H_VIDSOUT_VR 2 1 H_VIDSOUT_VR_R 2 1 H_VIDSOUT
BI 10
R24PR 1 37 H_PM_SYNC_0 P36 PM_SYNC TESTLO_P6 P6 TESTLOW_1 10
100
IN IN 5% 0 5% 0
10 IN H_PECI N37 PECI FC_K9 K9 VCCST
IN 11 EMPTY 402 EMPTY 402
5%
RSVD H15 TP_CPU_H15
EMPTY 2 H_CATERR_N M36 CATERR* RSVD J9 TP_CPU_J9 R86CV R85CV
402 IN H_PROCHOT_R_N TP_CPU_H14
H_VIDALERT_N_VR
2 1 H_VIDALERT_N_VR_R 2 1 H_VIDALERT_N
10 IN K38 PROCHOT* RSVD H14 107 BI BI 10
10 IN H_THERMTRIP_N F37 THERMTRIP* VCC M8 V_CPU_CORE
IN 11 107 108 109 110 111 5% 0 5% 0
77 38 H_SKTOCC_N D38 SKTOCC* RSVD AV2 NC_HSW_AV2 EMPTY 402 EMPTY 402
OUT
RSVD_TP J16 TP_CPU_J16
16 OUT DIMM_CA_CPU_VREF_A AB38 SM_VREF RSVD_TP H16 TP_CPU_H16
113 14 HSW_PCUDEBUG_<15..0> 0
PWR_DEBUG N40 PWR_DEBUG
IN 10 11 113
CAD NOTE:
IN AA37 CFG[0] VSS N39
1 Y38 CFG[1] VSS V7 TP_CPU_V7 PLACE IN CRB AREA
2 AA36 CFG[2] VSS AB6 TP_CPU_AB6
3 W38 CFG[3] RSVD_TP K13 TP_CPU_K13
CAD NOTE: PLACEHOLDER FOR CRB. PLACE R89PR AND R90PR NEXT
4 V39 CFG[4] RSVD_TP J8 TP_CPU_J8
TO EACH OTHER IN CRB AREA.
112 107 106 104 5 U39 CFG[5] SM_RCOMP[0] R1 DDR_RCOMP_0 10
44 41 40 11 10 IN V_1P05_PCH IN FOR CRB, PECI_HDR RENAME TO H_PECI
C 103 98 93 92 51 6 U40 CFG[6] SM_RCOMP[1] P1 DDR_RCOMP_1
IN 10 C
116 113 R360PR 1 7 V38 CFG[7] SM_RCOMP[2] R2 DDR_RCOMP_2
IN 10
1K 8 T40 CFG[8] RSVD AB36 TP_CPU_AB36
5% 9 Y35 CFG[9] RSVD_TP AW2 TP_CPU_AW2 R89PR
EMPTY 2 10 AA34 CFG[10] RSVD_TP AV1 TP_CPU_AV1 H_PECI 2 1 EC_PECI
402 11 V37 CFG[11] RSVD AC8 TP_CPU_AC8
10 BI BI 103
DESIGN NOTE: 5% 0
H_THERMTRIP_N 10
12 Y34 CFG[12] VCOMP_OUT P4 V_VCCIOA_LOAD
OUT 6 7 CH 402
STUFF R360PR FOR BDW IN 13 U38 CFG[13] RSVD U8 TP_CPU_U8
14 W34 CFG[14] RSVD AB33 TP_CPU_AB33 R90PR
DESIGN NOTE: 2 1 PCH_PECI
BI 37
15 V35 CFG[15] RSVD T8 TP_CPU_T8
5% 0
RSVD Y8 TP_CPU_Y8
EMPTY 402
113 14 TPEV_HSW_PCUSTB_0_DP Y36 CFG[17] RSVD M10 TP_CPU_M10 PECI TO PCH OPTION
IN
113 14 IN TPEV_HSW_PCUSTB_0_DN Y37 CFG[16] RSVD L10 TP_CPU_L10
113 14 IN TPEV_HSW_PCUSTB_1_DP V36 CFG[19] RSVD M11 TP_CPU_M11 R274EV
TPEV_HSW_PCUSTB_1_DN H_PWRGD 2 1 TPEV_H_PWRGD
113 14 IN W36 CFG[18] RSVD L12 TP_CPU_L12 113 110 38 10 BI BI
RSVD W8 TP_CPU_W8 5% 0
113 H_TCK D39 TCK RSVD R33 TP_CPU_R33 CH 402
IN H_TDI TP_CPU_P33
113 IN F38 TDI RSVD P33
H_PROCHOT_R_N
R42PR H_PROCHOT_N
113 IN H_TDO F39 TDO VCC_SENSE E40 VCC_SENSE 10 107 10 BI 2 1 BI 10 104 107
OUT
R13PR 113 IN H_TMS E39 TMS 5% 0
113 104
49 38 OUT FP_RST_N 1 2 VSS N33
CAD NOTE:
CH 402
64 50 0 5% 113 IN H_TRST_N E37 TRST* VSS J11
116 H_PRDY_N
B 402 CH
113 IN L39 PRDY* VSS M9 R273EV, R274EV,R42PR
B
113 IN H_PREQ_N L37 PREQ* VSS J7 PLACE AT BRANCH OUT TO REDUCE STUB
116
XDP_DBRESET_N G40 DBR* VSS_SENSE F40 VSS_SENSE 10 107
OUT OUT
TESTLOW_2 N5 TESTLO_N5 RSVD N35 TP_CPU_N35
TP_CPU_K8 K8 RSVD_TP DPLL_REF_CLK# W6 CK_DPNS_DN
IN 44
1 R14PR TP_CPU_J10 J10 RSVD_TP DPLL_REF_CLK W5 CK_DPNS_DP
IN 44
49.9 CFG_RCOMP H40 HSW_CFG_RCOMP 10
1% IN
5 OF 8
2 CH
402
SKT
TESTLOW_1
IN 10
VCC_SENSE
R5CV VSS_SENSE
107 10 BI 2 1 BI 10 107
90 80 38 H_DRAMPWRGD 1 R11PR 2 CPU_DRAM_PWR_OK 10
1 R8PR
1% 49.9
IN OUT 49.9
EMPTY 402
0 5% 1%
402 CH 2 CH
402
113 107 98 11 10 V_CPU_VCCIO_RIGHT
IN
R34PR
10 BI H_THERMTRIP_N 2 1 PCH_THERMTRIP_N
OUT 37 R10PR 1
5% 0 51
A V_1P05_PCH IN 10 11 40 41 44 51 92 93 98 103 104 106 107 CH 402 5% A
112 113 116 CH 2
DDR_RCOMP_0 10 402
IN
DDR_RCOMP_1 IN 10 H_PROCHOT_N
IN 10 104 107
DDR_RCOMP_2 IN 10
HSW_CFG_RCOMP H_PWRGD 10 38 110 113

R2PR 10 IN
1 IN
150
1% 1 R128BV
2 CH 10K
113 11 10 OUT PWR_DEBUG 402 5%
DESIGN NOTE: 2 CH
1 R6PR 1 R46PR 1 R44PR 1 R41PR 1 R40PR
402
10K 100 75 100 49.9
5% 1% 1% 1% 1% DEFENSIVE DESIGN
2 EMPTY CH CH CH CH 50-OHM FOR R40PR (SV REQ)
402
2
402
2
402
2
402
2
402
hc_cdb_mpi.sch_1.10
INTEL
8 7 6 5 4 3 CUSTOM TEXT BPAGE
2 1
.
8 7 6 5 4 3 2 1
V_CPU_CORE
111 110 109 108 107 11 10 IN MODULE REV DETAILS
R301CV J1PR MODULE NAME REV DATE
V_1P05_PCH
IN HASWELL
0 5% R300CV
402 EMPTY
REV=1.1
113
107
10
98
0 5%
V_CPU_VCCIO_RIGHT
402 CH
P8 VCC VCC C31 V_CPU_CORE
OUT IN 10 11 107 108 109 110 111
103
116
113
112
107
106
104 R165CV L40 VCCIO_OUT VCC C33
VCCST 1 2 VCCIO2PCH AB8 RSVD_AB8 VCC L16
10
98
93
92
44
40
11
10
51
41
D IN 0
402 5% VCC L15
1 1 EMPTY
VCC J35 D
C18CV C19CV 111 110 VCC3
.1UF 4.7UF 107 11 10 V_CPU_CORE L31 VCC VCC H33 DESIGN NOTE: VCC3
IN
10% 20% 109 108 L18 VCC VCC H35
10V 6.3V
2 X5R 2 X5R
L17 VCC VCC J21 DEFENSIVE DESIGN EN_FIVR 1 R162CV
402 805 J33 VCC VCC J22 10K
A24 VCC VCC J23 5%
A25 VCC VCC J24 2 EMPTY PWR_DEBUG 10 113
A26 VCC VCC J25 402 OUT
R108PI A27 VCC VCC J26 R110CV
1 2 A28 VCC VCC J27 1 2 Q1MY_PIN2_PIN3
0 1A A29 VCC VCC J28 R163CV 10K 5%

603 CH 113 XDP_PWR_DEBUG 1 2 402 EMPTY
41 OUT V_CPU_VCCIO2PCH A30 VCC VCC J29 IN
51 G33 VCC VCC J30 10K 5% Q5CV
B25 VCC VCC J32 402 EMPTY
MBT3904DUAL 3 6
B27 VCC VCC J34
B29 VCC VCC K19 R111CV 5 2
1 R164CV B31 VCC VCC K21 113 110 107 103 82 81 IN VR_READY 1 2 Q1MY_PIN5
0 10K 5%
5% J31 VCC VCC K23
113 B33 VCC VCC K25 402 EMPTY 1 1
107 2 CH C14CV 4 1 XSTR
104 402 G31 VCC VCC K27 R113CV .1UF
98 B35 VCC VCC K29 0 10%
92 5% 16V
44 C24 VCC VCC K31 R112CV 2 EMPTY
C 40 V_1P05_PCH C25 VCC VCC M13 110 109 108 107 11 10 V_CPU_CORE 1 2 EMPTY 402 C
10 IN C26 VCC VCC K33 111
IN 402
11 10K 5% 2
41
51
C27 VCC VCC K35 402 EMPTY
93
C28 VCC VCC L19
103 C29 VCC VCC L20
106
112
C30 VCC VCC L21
116
C32 VCC VCC L22
C34 VCC VCC L23
C35 VCC VCC L24
D25 VCC VCC L25
D27 VCC VCC L26
D29 VCC VCC L27
D31 VCC VCC L28
DESIGN NOTE: E33 VCC VCC L29
D33 VCC VCC L30
BDW NOT SUPPORT FOR VCCIO2PCH. E31 VCC VCC L32
V_1P05_PCH DIRECT INTO VCCST. D35 VCC VCC L33
E24 VCC VCC M17
E25 VCC VCC M15
E26 VCC VCC M19
E27 VCC VCC M21
E28 VCC VCC M23
E29 VCC VCC M25
B E30 VCC VCC M27 B
E32 VCC VCC M29
E34 VCC VCC M33
F23 VCC
F25 VCC VDDQ AJ12 V_SM IN 16 26 27 28 29 38 90 91 93 111
F27 VCC VDDQ AJ13
F29 VCC VDDQ AJ15
F31 VCC VDDQ AJ17
E35 VCC VDDQ AJ20
F33 VCC VDDQ AJ21
F35 VCC VDDQ AJ24
G22 VCC VDDQ AJ25
G23 VCC VDDQ AJ28
G24 VCC VDDQ AJ29
G25 VCC VDDQ AJ9
G26 VCC VDDQ AT17
G27 VCC VDDQ AT22
G28 VCC VDDQ AU15
G29 VCC VDDQ AU20
G30 VCC VDDQ AU24
G32 VCC VDDQ AV10
G34 VCC VDDQ AV11
G35 VCC VDDQ AV13
H23 VCC VDDQ AV18
A H25 VCC VDDQ AV23 A
H27 VCC VDDQ AV8
H29 VCC VDDQ AW16
H31 VCC VDDQ AY12
L34 VCC VDDQ AY14
VDDQ AY9
6 OF 8
SKT
hc_cdb_mpi.sch_1.11
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

J1PR
HASWELL
REV=1.1
A13 VSS VSS AJ34
D A15 VSS VSS AJ35 AP11 VSS VSS AW32 G12 VSS VSS M4
A17 VSS VSS AJ36 AP14 VSS VSS AW34 G13 VSS VSS M40 D
A23 VSS VSS AJ37 AP15 VSS VSS AW36 G14 VSS VSS M5
A11 VSS VSS AJ40 AP24 VSS VSS AW7 G16 VSS VSS M6
AA3 VSS VSS AJ5 AP27 VSS VSS AY17 H11 VSS VSS M7
AA33 VSS VSS AJ8 AP30 VSS VSS AY23 G17 VSS VSS K15
AA35 VSS VSS AK1 AP36 VSS VSS AY26 G21 VSS VSS K16
AA38 VSS VSS AK10 AP4 VSS VSS AY27 G3 VSS VSS N1
AA6 VSS VSS AK11 AP5 VSS VSS AY30 H13 VSS VSS N2
AA7 VSS VSS AK12 AR11 VSS VSS AY5 H22 VSS VSS N3
AA8 VSS VSS AK13 AR14 VSS VSS AY7 H32 VSS VSS N7
A5 VSS VSS AK14 AR16 VSS VSS B24 G36 VSS VSS N34
AB34 VSS VSS AK18 AR17 VSS VSS B26 G37 VSS VSS N4
AB37 VSS VSS AK19 AR18 VSS VSS B28 G6 VSS VSS N6
AB5 VSS VSS AK24 AR19 VSS VSS B30 G7 VSS VSS K32
AB7 VSS VSS AK25 AR20 VSS VSS B34 G15 VSS VSS P2
AC3 VSS VSS AK26 AR21 VSS VSS B36 H1 VSS VSS P34
AC35 VSS VSS AK29 AR24 VSS VSS C4 H18 VSS VSS P7
AC36 VSS VSS AK30 AR27 VSS VSS C6 H20 VSS VSS N8
AC37 VSS VSS AK36 AR30 VSS VSS C12 H21 VSS VSS R3
AC38 VSS VSS AK4 AR31 VSS VSS C14 H24 VSS VSS L36
C
C
A7 VSS VSS AK9 AR36 VSS VSS C23 H36 VSS VSS R7
AD1 VSS VSS AL11 AR37 VSS VSS C36 H39 VSS VSS T1
AD2 VSS VSS AL14 AR38 VSS VSS B10 H4 VSS VSS T2
AD3 VSS VSS AL17 AR39 VSS VSS B23 H7 VSS VSS T33
AD33 VSS VSS AL21 AR40 VSS VSS C3 H8 VSS VSS M35
AD36 VSS VSS AL22 AR5 VSS VSS D9 H9 VSS VSS T39
AD4 VSS VSS AL24 AT1 VSS VSS D11 J19 VSS VSS T4
AD8 VSS VSS AL37 AT13 VSS VSS D2 K10 VSS VSS R8
AE33 VSS VSS AL38 AT14 VSS VSS D23 K14 VSS VSS U2
AE36 VSS VSS AL39 AT15 VSS VSS D24 J36 VSS VSS U33
AE5 VSS VSS AM1 AT24 VSS VSS D30 K1 VSS VSS U4
AE8 VSS VSS AM11 AT25 VSS VSS D34 K18 VSS VSS U7
AF1 VSS VSS AM14 AT26 VSS VSS D36 K20 VSS VSS P35
AF33 VSS VSS AM15 AT27 VSS VSS D37 K22 VSS VSS V3
B AF36 VSS VSS AM19 AT28 VSS VSS D5 K24 VSS VSS V33 B
AF8 VSS VSS AM27 AT30 VSS VSS E7 K30 VSS VSS V8
AG33 VSS VSS AM3 AT32 VSS VSS E8 K34 VSS VSS W1
AG40 VSS VSS AM34 AT4 VSS VSS E22 L7 VSS VSS W7
AG5 VSS VSS AM35 AT5 VSS VSS E23 L8 VSS
AG8 VSS VSS AM36 AT6 VSS VSS E36 L9 VSS VSS Y33
AH1 VSS VSS AM4 AT7 VSS VSS E38 L11 VSS VSS Y4
AH2 VSS VSS AM5 AT8 VSS VSS B32 L3 VSS VSS Y5
AH3 VSS VSS AN10 AT9 VSS VSS E6 L13 VSS VSS Y6
AH33 VSS VSS AN11 AU2 VSS VSS F1 L14 VSS
AH8 VSS VSS AN19 AU34 VSS VSS F16 M1 VSS VSS_NCTF AU40
AJ11 VSS VSS AN22 AU38 VSS VSS F19 K17 VSS VSS_NCTF AV39
AJ14 VSS VSS AN23 AU5 VSS VSS F21 M12 VSS VSS_NCTF AW38
AJ16 VSS VSS AN24 AU7 VSS VSS F22 M14 VSS VSS_NCTF AY3
AJ18 VSS VSS AN27 AV21 VSS VSS F24 M18 VSS VSS_NCTF B38
A AJ19 VSS VSS AN30 AV28 VSS VSS F26 M16 VSS VSS_NCTF B39 A
AJ22 VSS VSS AN36 AV3 VSS VSS F28 M20 VSS VSS_NCTF C40
AJ23 VSS VSS AN37 AV30 VSS VSS F30 M22 VSS VSS_NCTF D40
AJ26 VSS VSS AN40 AV34 VSS VSS F34 M24 VSS
AJ31 VSS VSS AN7 AW26 VSS VSS D32 M30 VSS
AJ32 VSS VSS AN8 AW3 VSS VSS F7 M32 VSS
AJ33 VSS VSS AN9 AW30 VSS VSS G9 M34 VSS
VSS AP1 VSS G11 M37 VSS
7 OF 8
SKT
hc_cdb_mpi.sch_1.12
INTEL
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MODULE REV DETAILS

D
D
J1PR
HASWELL
REV=1.1 RSVD_TP K12 TP_CPU_K12
RSVD_TP J13 TP_CPU_J13
TP_CPU_AY18
RSVD_TP P37 TP_CPU_P37
AY18 RSVD RSVD_TP N38 TP_CPU_N38
TP_CPU_AW24 AW24 RSVD
TP_CPU_AW23 AW23 RSVD RSVD_TP R36 TP_CPU_R36
TP__CPU_AV29 AV29 RSVD RSVD_TP C39 TP_CPU_C39
TP_CPU_AV24 AV24 RSVD
TP_CPU_AU39 AU39 RSVD VSS U35
TP_CPU_AU27 AU27 RSVD VSS P40
C TP_CPU_AU1 AU1 RSVD C
TP_CPU_AT40 AT40 RSVD VSS R38
TP_CPU_AK20 AK20 RSVD VSS T37
VCCST_PWRGD Y7 FC_Y7 VSS V34
TP_CPU_T34 T34 RSVD
TP_CPU_R34 R34 RSVD VSS R39
TP_CPU_J40 J40 RSVD
TP_CPU_J17
103
38
82
37
PWRGD_3V 1 R31PR 2 J17 RSVD VSS T38
81 77
IN TP_CPU_J15 J15 RSVD VSS U36
116 6.04K 1% 1 TP_CPU_H12 H12 RSVD VSS P39
402 CH
R32PR
2.67K VSS T36
1% VSS R37
CH
402 VSS J14
2 RSVD_TP N36 TP_CPU_N36
8 OF 8
SKT
B B
A A
hc_cdb_mpi.sch_1.13
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MODULE REV DETAILS

ENG FEATURE: NOA STRAPS

DESIGN NOTE:
D
R13UB D
HSW_PCUDEBUG_<15..0>
1 2 0 IN 10 113
1K 5%
402 EMPTY CAD NOTE:
R15UB PLACE AS NEAR AS POSSIBLE TO HSW
1 2 1
1K 5% DESIGN NOTE: DEFENSIVE DESIGN
402 EMPTY
R14UB R34UB
1 2 2
1 2 TPEV_HSW_PCUSTB_0_DP
IN 10 113
1K 5% 1K 5%
402 EMPTY 402 EMPTY
R101UB R35UB
113 OUT
PRIVACY_MSR_EN_N 1 2 3 1 2 TPEV_HSW_PCUSTB_1_DP
IN 10 113
R200UB 1K 5% 1K 5%
402 CH 402 EMPTY
1K 5% R102UB R36UB
402 EMPTY 1 2 4 1 2 TPEV_HSW_PCUSTB_0_DN
IN 10 113
C 1K 5% 1K 5% C
402 EMPTY 402 EMPTY
R17UB
1 2 R37UB
5
1K 5% 1 2 TPEV_HSW_PCUSTB_1_DN
IN 10 113
402 EMPTY 1K 5%
402 EMPTY
R28UB
1 2 6
1K 5%
402 EMPTY
R27UB
1 2 7
1K 5%
402 EMPTY
R29UB
1 2 8
1K 5%
402 EMPTY
R30UB
1 2 9
B B
1K 5%
402 EMPTY
R31UB
1 2 10
1K 5%
402 CH
R32UB
1 2 11
1K 5%
402 EMPTY
R33UB
1 2 12
1K 5%
402 EMPTY
R24UB
18 HSW_STRAP_13 1 2 13
OUT
1K 5%
402 CH
R25UB
1 2 14
A A
1K 5%
402 EMPTY
R26UB
1 2 15
1K 5%
402 EMPTY
[PAGE_TITLE=MCP TERMINATION]
hc_cdb_mpi.sch_1.14
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MODULE REV DETAILS

D
D
J10BC
C LAI_TEK_P6708 C
REV=1
36 6 IN DMI_MT_IR_3_DP 1 C0+ C1+ 4 DMI_MT_IR_2_DN IN 6 36
36 6 IN DMI_MT_IR_3_DN 3 C0- C1- 6 DMI_MT_IR_2_DP IN 6 36
36 6 IN
DMI_MT_IR_0_DN 7 C2+ C3+ 10 DMI_MT_IR_1_DN IN 6 36
36 6 IN DMI_MT_IR_0_DP 9 C2- C3- 12 DMI_MT_IR_1_DP IN 6 36
36 6
DMI_IT_MR_3_DP 13 C4+ C5+ 16 DMI_IT_MR_2_DN 6 36
IN DMI_IT_MR_3_DN IN
36 6 IN 15 C4- C5- 18 DMI_IT_MR_2_DP IN 6 36
36 6 DMI_IT_MR_1_DP 19 C6+ C7+ 22 DMI_IT_MR_0_DP 6 36

IN IN
36 6 IN DMI_IT_MR_1_DN 21 C6- C7- 24 DMI_IT_MR_0_DN IN 6 36
5 GND GND 2
11 GND GND 8
17 GND GND 14
23 GND GND 20
25 GND (G1) (G2) GND 26
OPTION 1 OF 2
B EMPTY B
CAD NOTE:
REMOVE THIS FOOTPRINT FROM THE SECONDARY SOLDERPASTE LAYER
A A
Vinafix [PAGE_TITLE=DMI LAI]

hc_cdb_mpi.sch_1.15
INTEL
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1
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MODULE REV DETAILS

D R69MY
38 29 28 27 26 16 11 IN V_SM 1 2 D
111 93 91 90 1K 1%
1 402 CH
C60MY
.1UF
10%
10V
2 EMPTY DIMM_DQ_VREF_B
402
1 R70MY 2 OUT 17
1K 1% 1
CAD NOTE: 402 CH C5UB
.1UF
PLACE RESISTORS CLOSE TO CH_B DIMMS 10%
16V
ON DIMM_VREF_B 2 X7R
402
V_SM 1 R67MY 2
38 29 28 27 26 16 11 IN
111 93 91 90 1K 1%
1 402 CH
C59MY
.1UF
DIMM_DQ_VREF_A OUT 17
10%
2 10V 1
EMPTY C8UB
C 402
1 R68MY 2 .1UF C
10%
1K 1% 2 16V
402 CH X7R
402
CAD NOTE:
PLACE RESISTORS CLOSE TO CH_A DIMMS
ON DIMM_VREF_A
111 93 91 90 38 29 28 27 26 16 11 V_SM 1 R1UB 2

IN
1K 1%
C88MY 402 CH
1 2
.1UF 10%
10V 1 R2UB 2 DIMM_CA_VREF_A 16 26 27
X5R
V_SM_R2_DIMM_VREF_A
OUT
402 1 R3UB 2 0 5%
402 CH 1
1K 1% C9UB
402 CH .1UF
10%
B BOM NOTE: 16V B
2 X7R
STUFF R404UB & R403UB FOR HSW CPU VREF CONTROL. 402
STUFF ALL R404UB, R403UB, R2UB & R7UB FOR POR.
10
DIMM_CA_CPU_VREF_A 1 R404UB 2 DIMM_CA_VREF_A
16 26 27
IN OUT
0 5%
402 CH
1 R403UB 2 DIMM_CA_VREF_B
16 28 29
OUT
0 5%
1
C1MY 402 CH
.022UF
10%
16V
2 X7R
402
90 38 29 28 27 26 16 11 V_SM 1 R5UB 2
DIMM_CA_CPU_VREF_A_RC 111 93 91
IN
C20MY 1K 1%
1 2 402 CH
1 R13MY
24.9 .1UF 10%
1% 10V V_SM_R2_DIMM_VREF_B
R7UB
2 CH X5R
1 2 DIMM_CA_VREF_B OUT 16 28 29
402 402 0 5%
A 1 R6UB 2
402 CH 1
C10UB A
.1UF
1K 1% 10%
16V
402 CH 2 X7R
402
[PAGE_TITLE=DIMM VREFS]
hc_cdb_mpi.sch_1.16
INTEL
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1
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MODULE REV DETAILS

R2MY
16 DIMM_DQ_VREF_A 1 2
IN DIMM_DQ_CPU_VREF_A DIMM_DQ_R_VREF_A
9 IN 0 5% OUT 26 27
R3MY 402 CH
1 2
2 1% DIMM_DQ_R_VREF_B 28 29
402 CH OUT
D 1 1
16 DIMM_DQ_VREF_B C104MY C106MY D
IN DIMM_DQ_CPU_VREF_B 1 1
9 IN
.1UF C105MY .1UF C107MY
R5MY 10%
16V
.1UF 10%
16V
.1UF
1 2 2 X7R
10%
16V
2 X7R
10%
16V
0 5% R6MY
603 2 X7R 603 2 X7R
402 CH
1 2
603 603
1
C4MY 2 1%
.022UF
10%
402 CH
16V CAD NOTE:
2 X7R
402 CAD NOTE: 2 CAPS FOR DEFENSIVE DESIGN AS VREF
1
DIMM_DQ_CPU_VREF_A_RC C5MY CRITICAL.PLACE DIFFERENT LOCATION IN LAYOUT
.022UF PLACE NEAR DIMM AREA
1 R8MY 10%
24.9 16V
2 X7R
1% 402
CH
BOM NOTE:
2
402 DIMM_DQ_CPU_VREF_B_RC
VOLTAGE DIVIDER OPTION:STUFF R2MY, R5MY; EMPTY R3MY, R6MY
1 R9MY VREF CONTROL FROM CPU: STUFF R3MY, R6MY; EMPTY R2MY, R5MY
24.9
1% STUFF ALL R2MY, R5MY,R3MY, R6MY FOR POR.
2 CH
402
C C
VCC3 VCC3
DESIGN NOTE:
THERMAL SENSOR FOR DIMM
Q2MY
MMBT3904
1 2 XSTR VCC3
R12MY 1 R4MY
1 1.5K
10K 5%
5% U1MY VCC3 1 R7MY
3 2 CH 1.5K 1
CH ADM1032 402 5%
402
2 DDR_THERMP 2 D+ VDD 1 2 CH R11MY
402 10K
DDR_THERMN 5%
3 D-
SMB_CLK_THRM CH
R1MY SCLK 8
BI 65 103 402
103 DDR_THERM_N 1 2 DDR_THERM_N_R 4 THERM* SDATA 7 SMB_DATA_THRM 65 103 2
OUT BI
0 5% ALERT* 6
B 402 B
CH 5 GND R10MY
DDR_THERM_ALERT_N_R 1 2 DDR_THERM_ALERT_N 103
OUT
IC 0 5%
402 CH
R1CV 2
63 35 EXTTS_SNI_DRV0_PCH 1 2 C3MY
OUT .1UF
0 5% 10%
402 EMPTY 10V
1 X5R
402
R76CV
63 35 OUT EXTTS_SNI_DRV1_PCH 1 2
0 5%
402 EMPTY
A A
[PAGE_TITLE=DIMM VREFS & THERMAL SENSOR] BPAGE DRAWING

hc_cdb_mpi.sch_1.17
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
116 115 V_3P3_STBY\G

82 81 80 79 78 77 74 52 51 49 41 36 35 IN
110 106 104 102 98 95 94 93 92 91 83
1
R20PR
VCC3 10K
5%
CH
402
1 2 HSW_STRAP_13 14
OUT
R5PR
1K
5%
CH Q1PR
402 MBT3904DUAL 3 6
2 NFCMODULE
C 1 R21PR 2 5 2 J8DP C
52 IN PCH_GP8 OC_Q1PR_5
KOZ / KOV
10K 5% OC_Q1PR_2
402 CH
4 1 XSTR
EMPTY
V_3P3_EPW
94 92 83 51 41 IN
B 49 38 IN PCH_GP74_PU 1
C1LB J7DP B
0.1UF CONN_1X15_FPC
1 R20DP 20%
0 16V 15
5% 2 Y5V 14
2 EMPTY
402 TP_RSVD_P3 13
R19DP 402 TP_RSVD_P4 12
49 38 NFC_GP57 1 2 NFC_J7DP_11 R34DP 11
IN NFC_J7DP_10
0 5% 1 2 10
402 CH 67 49 38 IN SMLINK0_DATA 0 5% 9
67 49 38 IN SMLINK0_CLK 402 CH 8
7
TP_RSVD_P10 6
TP_RSVP_P11 5
TP_RSVP_P12 4
R33DP 3
1 2 NFC_J7DP_2 2
0 5% 1
402 CH
CONN
A A
[PAGE_TITLE=NFC]
hc_cdb_mpi.sch_1.18
INTEL
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MODULE REV DETAILS

VCC MODULE NAME REV DATE
BOM NOTE: BOM NOTE: C92281-003

EV/MPI (DEFAULT): STUFF FOR OPTIMIZED EMI PERFORMANCE DEFAULT: STUFF FERRITE BEAD <693286-006> FOR <200MHZ BANDWIDTH CUTOFF RT1UB
CRB: STUFF FOR BANDWIDTH OPTIMIZE OPTION: REPLACE WITH 0OHM 603 FOR >200MHZ BANDWIDTH CUTOFF 1 2 VGA_THERM_PN1
43 19 IN VGA_RED M15UB
1 2 THRMSTR M12UB
43 19 IN VGA_GREEN M14UB MULTI 1 2
D 1 1 1.10 MULTI 1
43 19 IN VGA_BLUE 1 2 FB C13UB C4UB C94UB D
M13UB MULTI 0.1UF 0.1UF CH 805 .1UF
1 2 20% 20% 20%
DESIGN NOTE: FB DESIGN NOTE: 16V 16V 25V
MULTI 2 Y5V 2 Y5V 2 Y5V
FERRITE BEAD: 0.5A, 47 OHM FERRITE BEAD: 0.5A, 47 OHM 402 402 603
FB
DESIGN NOTE: 0603 PACKAGE 0603 PACKAGE 693286-006
FB5UB
J4UB
FERRITE BEAD: 0.5A, 47 OHM
693286-006 1 2 VGA_RED_FB1
16
0603 PACKAGE
FB4UB FB VGA_RED_CONN 1
693286-006 1 2 VGA_GREEN_FB1
VGA_THERM_9 9
FB3UB FB VGA_GREEN_CONN 2
1 2 VGA_BLUE_FB1
10
FB VGA_BLUE_CONN 3
TP_VGACONN_11_CORE_R 11
TP_VGACONN_4_CORE 4
12
43 IN VGA_HSYNC_3V 5
43 IN VGA_VSYNC_3V 13
6
1 1 1 14
C89UB BOM NOTE: C93UB C85UB 7
10PF 10PF 10PF 15
5% DEFAULT: STUFF 10PF <A36094-025> FOR BANDWIDTH <200MHZ 5% 5%
8 RCPT
50V OPTION: REPLACE WITH 3.3PF FOR BANDWITH >200MHZ 50V 50V
C 2 COG 2 COG 2 COG C
402 402 402
17
1
C87UB
100PF
1 1 1 5% 1
C90UB BOM NOTE: C81UB C84UB 50V C88UB
22PF 22PF 22PF
2 EMPTY 100PF
DEFAULT: STUFF 22PF <A36095-030> FOR BANDWIDTH <200MHZ 402 5%
5% 5% 5% 50V
2 50V OPTION: REPLACE WITH 3.3PF FOR BANDWITH >200MHZ
2 50V
2 50V 2 EMPTY
COG COG COG 402
402 402 402
1 1 1 DESIGN NOTE:
C92UB BOM NOTE: C82UB C83UB
10PF 10PF 10PF
5% 5% 5% DEFAULT: EMPTY EMI CAPS
DEFAULT: STUFF 10PF <A36094-025> FOR BANDWIDTH <200MHZ
50V 50V 50V
2 COG OPTION: EMPTY FOR BANDWITH >200MHZ 2 COG 2 COG
402 402 402
"COG" "COG" "COG"
A36094-025
B VCC B
1 1 1
CR1UB CR2UB
R84UB R85UB R86UB VCC3 3
GP 3
GP
150 CAD NOTE: 150 150 SOT23S SOT23S
1% 1% 1%
CH PLACE 150 OHM RESISTORS CLOSE TO FILTERS CH CH CR7UB
402 (CAPS / FERRITE-BEADS) 402 402
2 2 2 1 2
1 2 1 2
EMPTY EMPTY
DIO
BAT54C 3
SOT23C
VGA_DDC_5V_R 1
C144UB
1
1 .1UF
RGB ESD PROTECTION R80UB R82UB
10%
10V
2
43 19 IN VGA_RED 2.2K 2.2K EMPTY
402
5% 5%
43 19 IN VGA_GREEN CH CH
402 402
2
43 19 IN VGA_BLUE 2 R83UB 1 VGA_DDCSDA_CONN
VGA_DDCSDA_5V
2
43 IN
VCC3 100 5%
A 402 CH A
CR3UB CR4UB CR5UB DESIGN NOTE:
GP GP GP
3 SOT23S 3 SOT23S 3 SOT23S MAX 0.5 PF 43 VGA_DDCSCL_5V 2 R81UB 1 VGA_DDCSCL_CONN
EMPTY EMPTY EMPTY IN
100 5%
TP_TVS6_2V_PIN4
TP_TVS6_2V_PIN6
1
402 CH 1 1
C80UB C86UB C91UB
.1UF 1 2 1 2 1 2 I31 100PF 100PF
20%
25V
1 3 4 6 CR6UB 5%
50V
5%
50V
EMPTY TVS6_2V 2 EMPTY 2 EMPTY
603 402 402
2
6.2V 2 5
EMPTY [PAGE_TITLE=VGA CONNECTOR]
BOM NOTE: BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
hc_cdb_mpi.sch_1.19
INTEL
UN-STUFF ALL COMPONENTS ON PAGE FOR NON-GRAPHICS SKUS Mon Apr 16 13:57:38 2012 CONFIDENTIAL
2 1
8 7 6 5 4 3 2 1
VCC3 +12V +12V

VCC3 MODULE REV DETAILS
J6UB MODULE NAME REV DATE
SLOT 7 3GIO_X16
REV=2.0
B1 12V PRSNT1* A1 PCIEX16_PRSNT1_N
PCI EXPRESS ATX CONFIG B2 A2
12V 12V
16-PORT 114 81 66 38 25 24 23 22 SMB_CLK_RESUME
B3 12V 12V A3 1
BI B4 GND GND A4
R10UB
D B5 SMCLK JTAG2 A5 TP_3G16_JTAG2 0 VCC3
114 81 66 38 25 24 23 22 SMB_DATA_RESUME B6 SMDAT JTAG3 A6 TP_3G16_JTAG3 5% D
BI B7 A7 TP_3G16_JTAG4
GND JTAG4 CH C98UB
B8 A8 TP_3G16_JTAG5 402 1 2
3.3V JTAG5 2
TP_3G16_JTAG1 B9 JTAG1 3.3V A9
V_3P3_PCIVAUX B10 A10 .1UF 20%
94 25 24 23 22 20 IN 3.3VAUX 3.3V 25V
114 66 49 38 25 24 23 22 WAKE_N B11 WAKE* PWRGD A11 PLTRST_PEG_SLOTS_N 82 Y5V
OUT IN 603
KEY +12V
TP_3G16_RSVD_B12 B12 RSVD GND A12
B13 A13 CK_PE_100M_16PORT_DP C97UB
GND REFCLK+ IN 44 1 2
21 IN EXP_A_TX_0_C_DP B14 HSOP0 REFCLK- A14 CK_PE_100M_16PORT_DN IN 44
21 IN EXP_A_TX_0_C_DN B15 HSON0 GND A15 .1UF 20%
B16 GND HSIP0 A16 EXP_A_RX_0_DP OUT 6 25V
PCIEX16_PRSNT2_N B17 A17 EXP_A_RX_0_DN Y5V
49 37 OUT PRSNT2* HSIN0 OUT 6 603
B18 GND GND A18
94 25 24 23 22 20 IN V_3P3_PCIVAUX
21 IN EXP_A_TX_1_C_DP B19 HSOP1 RSVD A19 TP_3G16RSVD_A19

21 IN EXP_A_TX_1_C_DN B20 HSON1 GND A20
B21 A21 EXP_A_RX_1_DP C96UB
GND HSIP1 OUT 6 1 2
B22 GND HSIN1 A22 EXP_A_RX_1_DN OUT 6
21 IN EXP_A_TX_2_C_DP B23 HSOP2 GND A23 .1UF 20%
21 IN EXP_A_TX_2_C_DN B24 HSON2 GND A24 25V
C B25 A25 EXP_A_RX_2_DP Y5V C
GND HSIP2 OUT 6 603
21 IN EXP_A_TX_3_C_DP B27 HSOP3 GND A27
21 EXP_A_TX_3_C_DN B28 HSON3 GND A28
IN B29 A29 EXP_A_RX_3_DP DESIGN NOTE:
GND HSIP3 OUT 6
TP_3G18_RSVD_B30 B30 RSVD HSIN3 A30 EXP_A_RX_3_DN OUT 6 ALWAYS STUFF C99UB & C95UB
TP_3G16_RSVD_B31 B31 PRSNT2* GND A31
B32 A32 TP_3G16_RSVD_A32 EVEN IF J6UB IS EMPTY
GND RSVD
FOR X1 DECOUPLING
EXP_A_TX_4_C_DP B33 A33 TP_3G16_RSVD_A33 +12V VCC3
21 IN EXP_A_TX_4_C_DN HSOP4 RSVD
21 IN B34 HSON4 GND A34 C99UB C95UB
B35 A35 EXP_A_RX_4_DP 470.0UF 100UF
GND HSIP4 OUT 6 1 2 1 2
21 EXP_A_TX_5_C_DP B37 HSOP5 GND A37
IN B38 A38
20% 16V 20.0% 25V
21 IN EXP_A_TX_5_C_DN HSON5 GND ALUM ELEC
B39 GND HSIP5 A39 EXP_A_RX_5_DP OUT 6 RDL RDL
IN EXP_A_TX_6_C_DN B42 A42
21 IN HSON6 GND
B43 GND HSIP6 A43 EXP_A_RX_6_DP OUT 6
B 21 EXP_A_TX_7_C_DP B45 HSOP7 GND A45 B
IN B46 A46
21 IN EXP_A_TX_7_C_DN HSON7 GND
TP_EXP_PRSNT_N B48 PRSNT2* HSIN7 A48 EXP_A_RX_7_DN OUT 6 +12V
B49 GND GND A49
C53BU CAD NOTE:

EXP_A_TX_8_C_DP B50 A50 TP_3G16_RSVD_A50 1 2
21 IN HSOP8 RSVD
21 IN EXP_A_TX_8_C_DN B51 HSON8 GND A51
B52 A52 EXP_A_RX_8_DP 0.1UF 20% PLACE NEAR J6UB
GND HSIP8 OUT 6 16V
B53 GND HSIN8 A53 EXP_A_RX_8_DN OUT 6 Y5V
EXP_A_TX_9_C_DP B54 A54 402
21 IN EXP_A_TX_9_C_DN
HSOP9 GND
21 B55 HSON9 GND A55
IN B56 A56 EXP_A_RX_9_DP
GND HSIP9 OUT 6
21 IN HSON10 GND
21 IN HSON11 GND
A 21 EXP_A_TX_12_C_DN B67 HSON12 GND A67 A
GND HSIP12 OUT 6
21 IN HSON13 GND
IN B75 A75
21 IN EXP_A_TX_14_C_DN HSON14 GND
21 EXP_A_TX_15_C_DN B79 HSON15 GND A79
GND HSIP15 OUT 6
TP_3G16_RSVD_B80 B81 PRSNT2* HSIN15 A81 EXP_A_RX_15_DN OUT 6
TP_16PRSNT_B82 B82 A82 [PAGE_TITLE=PCI EXPRESS X16 (0_TO_15]
RSVD 1 OF 1 GND
CONN hc_cdb_mpi.sch_1.20
INTEL
2 1
BW_ATX_CORE
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BW_ATX_CORE 1.06.00 5-5-06
D
EXP_A_TX_0_C_DN 20
D
C103UB C102UB OUT
6 IN EXP_A_TX_0_DN 1 2 1 2 EXP_A_TX_0_C_DP OUT 20
6 IN EXP_A_TX_0_DP .22UF 10% .22UF 10%
10V402 X5R 10V402 X5R
C101UB
6 IN EXP_A_TX_1_DN 1 2
C100UB EXP_A_TX_1_C_DN OUT 20
6 IN EXP_A_TX_1_DP .22UF 10% 1 2 EXP_A_TX_1_C_DP OUT 20
10V402 X5R .22UF 10%
10V402 X5R C109UB
10V402 X5R .22UF 10%
C107UB 10V402 X5R
6 EXP_A_TX_3_DN 1 2
C106UB
EXP_A_TX_3_C_DN 20
IN EXP_A_TX_3_DP OUT
C 6 IN .22UF 10% 1 2 EXP_A_TX_3_C_DP OUT 20
C
10V402 X5R .22UF 10%
10V402 X5R
C105UB
10V402 X5R .22UF 10%
C116UB 10V402 X5R
10V402 X5R .22UF 10%
10V402 X5R C114UB
10V402 X5R .22UF 10%
C112UB 10V402 X5R
10V402 X5R .22UF 10%
10V402 X5R
B B
EXP_A_TX_8_DN 1
C104UB
2 EXP_A_TX_8_C_DN OUT 20
6 IN C110UB
10V402 X5R .22UF 10%
C122UB 10V402 X5R
10V402 X5R .22UF 10%
10V402 X5R
EXP_A_TX_10_DN 1
C120UB
6 IN C119UB
10V402 X5R .22UF 10%
C118UB 10V402 X5R
C131UB
EXP_A_TX_11_C_DN OUT 20
10V402 X5R .22UF 10%
10V402 X5R
EXP_A_TX_12_DN 1
C130UB
6 IN C129UB
10V402 X5R .22UF 10%
C128UB 10V402 X5R
6 IN EXP_A_TX_13_DP .22UF 10% 1 2
EXP_A_TX_13_C_DP
10V402 OUT 20
A X5R .22UF 10% A
10V402 X5R
EXP_A_TX_14_DN 1
C126UB
6 IN C125UB
10V402 X5R .22UF 10%
10V402 X5R
EXP_A_TX_15_DN 1
C124UB
6 IN C123UB
10V402 X5R .22UF 10%
10V402 X5R
[PAGE_TITLE=PCI EXPRESS X16 COUPLING]

hc_cdb_mpi.sch_1.21
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

ATX EXPANSION SLOT 4

PCI EXPRESS +12V
D 1-PORT
D
VCC3
C2BU
V_3P3_PCIVAUX 1 2
94 25 24 23 22 20 IN +12V
.1UF 20%
25V
Y5V VCC3 1 1 1
603 J4BU C190LB C191LB C192LB
.1UF .1UF .1UF
3GIO_X1 20% 20% 20%
REV=2.0 2
25V
2
25V
2
25V
Y5V Y5V Y5V
B1 12V PRSNT1* A1 PCIEX1_SLOT6_PRSNT1_N 603 603 603
B2 12V 12V A2
B3 12V 12V A3
114 81 66 38 25 24 23 20 BI SMB_CLK_RESUME B4 A4 1
GND GND
B5 SMCLK JTAG2 A5 TP_PCIE_JTAG2_2
SMB_DATA_RESUME B6 A6 TP_PCIE_JTAG3_2
R103UB
114 81 66 38 25 24 23 20 BI SMDAT JTAG3 0
+12V
B7 GND JTAG4 A7 TP_PCIE_JTAG4_2 5%
B8 3.3V JTAG5 A8 TP_PCIE_JTAG5_2 CH
VCC3 TP_PCIE_JTAG1_BP_2 B9 A9 402
JTAG1 3.3V 2
94 25 24 23 22 20 V_3P3_PCIVAUX B10 3.3VAUX 3.3V A10
IN WAKE_N B11 A11 PLTRST_PCIE_SLOTS_N
114 66 49 38 25 24 23 20 OUT WAKE* PWRGD IN 23
25
24
82
C KEY
1
C60LB
1
C61LB C
TP_PCIE_RSVD_B12_2 B12 A12 .1UF .1UF
RSVD GND 20% 20%
B13 GND REFCLK+ A13 CK_1PORT_S6_DP 44 25V 25V
HSO8_R_C_DP B14 A14 CK_1PORT_S6_DN
IN 2 Y5V 2 Y5V
22 IN HSO8_R_C_DN HSOP0 REFCLK- IN 44 603 603
22 B15 HSON0 GND A15
IN B16 A16 HSI8_R_DP
GND HSIP0 HSI8_R_DN OUT 22
63 35 PCIEX1_SLOT4_PRSNT2_N B17 PRSNT2* HSIN0 A17 22
OUT B18 A18 OUT
GND 1 OF 1 GND
CONN CAD NOTE:
PLACE NEAR SLOT +12V

C19LB
470.0UF
1 2
20% 16V
R34CV HSI8_R_DP ALUM
36 25 HSI8_DP 1 2 22 RDL
IN OUT
0 5%
402 CH
R35CV HSI8_R_DN
36 25 HSI8_DN 1 2 22
B IN OUT 94 25 24 23 22 20 V_3P3_PCIVAUX B
0 5% IN
402 CH
R36CV HSO8_R_DP 1
36 25 HSO8_DP 1 2 22 C97LB
IN OUT CAD NOTE: .1UF
0 5% 20%
402 CH 25V
R37CV PLACE NEAR SLOT 2 EMPTY
36 25 HSO8_DN 1 2 HSO8_R_DN 22
603
IN OUT
0 5%
402 CH
C21BU
HSO8_R_C_DN 22
HSO8_R_DN 1 2 1
C3BU
2
OUT
22 IN HSO8_R_C_DP OUT 22
22 IN HSO8_R_DP
.1UF 10% .1UF 10%
10V 10V
X5R X5R
402 402
A CAD NOTE: A
DESIGN NOTE:
PLACE C21BU & C3BU NEAR J4BU OVERLAP RES WITH X4 PCIE (R46CV ETC)
Vinafix
[PAGE_TITLE=PCI EXPRESS X1 #1]
hc_cdb_mpi.sch_1.22
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

ATX EXPANSION SLOT 5

D
D
VCC3
C9BU
1 2
.1UF 20%
25V
Y5V
603
+12V
C10BU
1 2
.1UF 20%
25V
Y5V
603
+12V 94 25 24 23 22 20 IN V_3P3_PCIVAUX
C J17BU +12V VCC3 C

C11BU
3GIO_X1 1 2
1.0
B1 12V PRSNT1* A1 PCIEX1_SLOT5_PRSNT1_N .1UF 20%
B2 12V 12V A2 25V
EMPTY
B3 A3 1
114 81 66 38 25 24 22 20 SMB_CLK_RESUME 12V 12V 603
BI B4 GND GND A4 R105BU +12V
B5 A5 TP_3G16_2_JTAG2 0 C12BU
SMCLK JTAG2 5% 470.0UF
114 81 66 38 25 24 22 20 BI SMB_DATA_RESUME B6 SMDAT JTAG3 A6 TP_3G16_2_JTAG3
B7 A7 TP_3G16_2_JTAG4 CH 1 2
GND JTAG4 402
B8 3.3V JTAG5 A8 TP_3G16_2_JTAG5
2
VCC3 TP_3G16_2_JTAG1 B9 A9 20% 16V
JTAG1 3.3V ALUM
94 25 24 23 22 20 IN V_3P3_PCIVAUX B10 3.3VAUX 3.3V A10 RDL
114 66 49 38 25 24 22 20 OUT WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N IN 22 24 25 82 VCC3
CAD NOTE: C13BU
KEY 1
100UF
2
PLACE AC CAPS NEAR X1 CONN
TP_3G16_2_RSVD_B12 B12 RSVD GND A12
C4BU B13 GND REFCLK+ A13 CK_1PORT_S7_DP
IN 44
HSO7_R_DP C1BU 1 2 HSO7_R_C_DP B14 A14 CK_1PORT_S7_DN 20.0% 25V
23 IN HSOP0 REFCLK- IN 44
ELEC
23 IN HSO7_R_DN 1 2 HSO7_R_C_DN B15 HSON0 GND A15 RDL
.1UF 10% B16 A16 HSI7_R_DP
.1UF 10% 10V X5R GND HSIP0 OUT 23
10V 35 402 OUT PCIEX1_SLOT5_PRSNT2_N B17 PRSNT2* HSIN0 A17 HSI7_R_DN
OUT 23
B X5R 63 B18 A18 B
402 GND 1 OF 1 GND
CONN
HSI7_DP R38CV
36 25 1 2 HSI7_R_DP 23
IN OUT
0 5%
402 CH DESIGN NOTE:
HSI7_DN R39CV
36 25 1 2 HSI7_R_DN 23
A IN OUT OVERLAP RES WITH X4 PCIE (R48CV ETC) A
0 5%
402 CH
HSO7_DP R40CV
36 25 1 2 HSO7_R_DP 23
IN OUT
0 5%
402 CH
R41CV
36 25
HSO7_DN 1 2 HSO7_R_DN 23
IN OUT
0 5%
402 CH
[PAGE_TITLE=PCIE EXPRESS X1 #2]
hc_cdb_mpi.sch_1.23
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

VCC3
ATX EXPANSION SLOT 6 1

C231BU
2 VCC3 VCC3 +12V
D CAD NOTE: .1UF 20% C233BU C234BU C235BU
25V 1 2 1 2 1 2 D
Y5V
PCI EXPRESS 1-PORT 603 .1UF 20% .1UF 20% .1UF 20%
25V 25V 25V
C232BU Y5V Y5V Y5V
1 2 603 603 603
.1UF 20%
25V
Y5V
603
+12V
J13BU +12V VCC3

3GIO_X1
1.0 94 25 24 23 22 20 V_3P3_PCIVAUX
IN
B1 12V PRSNT1* A1 PCIEX1_SLOT4_PRSNT1_N
B2 12V 12V A2 C236BU
B3 A3 1 1 2
114 81 66 38 25 23 22 20 SMB_CLK_RESUME 12V 12V
BI B4 GND GND A4 R107BU
B5 A5 .1UF 20%
SMCLK JTAG2 TP_PCIE_JTAG2_1 0 25V
C SMB_DATA_RESUME B6 A6 TP_PCIE_JTAG3_1 5% Y5V C
114 81 66 38 25 23 22 20 BI SMDAT JTAG3 603
B7 GND JTAG4 A7 TP_PCIE_JTAG4_1 CH
B8 A8 TP_PCIE_JTAG5_1 402
VCC3 3.3V JTAG5 2
TP_PCIE_JTAG1_BP_1 B9 JTAG1 3.3V A9
94 25 24 23 22 20 IN V_3P3_PCIVAUX B10 3.3VAUX 3.3V A10
114 66 49 38 25 23 22 20 OUT WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N IN 22 23 25 82
CAD NOTE:
KEY
PLACE AC CAPS NEAR X1 CONN TP_PCIE_RSVD_B12_1 B12 RSVD GND A12
C52LB B13 GND REFCLK+ A13 CK_1PORT_S5_DP IN 44
HSO6_R_DP C50LB 1 2 HSO6_R_C_DP B14 A14 CK_1PORT_S5_DN
24 IN 1 2 HSOP0 REFCLK- IN 44
24 IN HSO6_R_DN HSO6_R_C_DN B15 HSON0 GND A15
.1UF 10% B16 A16 HSI6_R_DP
.1UF 10% 10V X5R GND HSIP0 HSI6_R_DN OUT 24
10V 35 402 OUT PCIEX1_SLOT6_PRSNT2_N B17 PRSNT2* HSIN0 A17 OUT 24
X5R 63 B18 A18
402 GND 1 OF 1 GND
CONN
1
C304BU
.1UF
CAD NOTE: 20%
25V
2 EMPTY
PLACE AT SLOT 4 603
B B
HSI6_DP R42CV
36 25 1 2 HSI6_R_DP 24
IN OUT CAD NOTE:
0 5%
402 CH
HSI6_DN R43CV OVERLAP RES WITH
36 25 1 2 HSI6_R_DN 24 R50CV ETC (PCIEX4)
IN OUT
0 5%
402 CH
HSO6_DP R44CV
36 25 1 2 HSO6_R_DP 24
IN OUT
0 5%
402 CH
A R45CV A
36 25
HSO6_DN 1 2 HSO6_R_DN 24
IN OUT
0 5%
402 CH
[PAGE_TITLE=PCI EXPRESS X1 #3]

hc_cdb_mpi.sch_1.24
INTEL
2 1
8 7 6 5 4 3 2 1
+12V MODULE REV DETAILS

+12V +12V
ATX EXPANSION SLOT 2 94 25 24 23 22 20 IN
V_3P3_PCIVAUX MODULE NAME REV DATE
C1CV PCI EXPRESS

C4CV VCC3 +12V J1CV
470.0UF
1 2 1 2 4-PORT VCC3
3GIO_X4 C5CV
1 2
20% 16V .1UF 20% REV=2.0
25V
ALUM Y5V B1 A1 .1UF 20%
RDL 603 12V PRSNT1* 25V
D B2 12V 12V A2 Y5V
SMB_CLK_RESUME B3 12V 12V A3 603 D
114 81 66 38 24 23 22 20 BI B4 A4
GND GND
B5 SMCLK JTAG2 A5 TP_PCIE_JTAG2_4
SMB_DATA_RESUME
114 81 66 38 24 23 22 20 B6 SMDAT JTAG3 A6 TP_PCIE_JTAG3_4
BI B7 A7
VCC3 GND JTAG4 TP_PCIE_JTAG4_4
C2CV B8 3.3V JTAG5 A8 TP_PCIE_JTAG5_4

100UF TP_PCIEX4_JTAG1_BP_1 B9 JTAG1 3.3V A9
1 2 V_3P3_PCIVAUX B10 A10
94 25 24 23 22 20 IN 3.3VAUX 3.3V
114 66 49 38 24 23 22 20 WAKE_N B11 WAKE* PWRGD A11 PLTRST_PCIE_SLOTS_N 22 23 24 82
20.0% 25V OUT IN
ELEC
RDL
KEY
VCC3 TP_PCIEX4_RSVD_B12_1
B12 A12
RSVD GND CK_PCIE_X4_DP
B13 GND REFCLK+ A13 44
C3CV EXP_B_TX_3_C_DP B14 A14 IN
1 2 25 IN HSOP0 REFCLK- CK_PCIE_X4_DN IN 44
25 EXP_B_TX_3_C_DN B15 HSON0 GND A15
.1UF 20% IN B16 A16 EXP_B_RX_3_DP
25V GND HSIP0 OUT 25
Y5V TP_PCIEX4_PRSNT_B16_1 B17 PRSNT2* HSIN0 A17 EXP_B_RX_3_DN 25
603 B18 A18 OUT
VCC3 GND GND
C15CV TP_PCIEX4_RSVD_A19_3
1 2 25 IN EXP_B_TX_2_C_DP B19 HSOP1 RSVD A19
25 IN EXP_B_TX_2_C_DN B20 HSON1 GND A20
C
.1UF 20% B21 GND HSIP1 A21 EXP_B_RX_2_DP OUT 25 C
25V B22 A22 EXP_B_RX_2_DN
Y5V GND HSIN1 OUT 25
603 25 IN EXP_B_TX_1_C_DP B23 HSOP2 GND A23
25 IN EXP_B_TX_1_C_DN B24 HSON2 GND A24
J3CV B25 GND HSIP2 A25 EXP_B_RX_1_DP OUT 25
PCIE_RM
B26 GND HSIN2 A26 EXP_B_RX_1_DN OUT 25
25 IN EXP_B_TX_0_C_DP B27 HSOP3 GND A27
25 EXP_B_TX_0_C_DN B28 HSON3 GND A28
1 GND
IN B29 A29 EXP_B_RX_0_DP
2 TP_PCIEX4_RSVD_B30_2 GND HSIP3 OUT 25
GND B30 RSVD HSIN3 A30 EXP_B_RX_0_DN OUT 25
B31 PRSNT2* GND A31
REV=1.0
B32 GND A32 TP_PCIEX4_RSVD_A32_4
CONN 1 OF 1 RSVD
CONN
36 22 HSI8_DP 1 R46CV 2 EXP_B_RX_0_DP

25
IN OUT
0 5%
402 EMPTY
HSO8_DP R52CV EXP_B_TX_0_R_DP
HSI8_DN 1 R47CV 2 EXP_B_RX_0_DN 36 22 IN 1 2 OUT 25
36 22 IN OUT 25
0 5%
B 0 5% 402 EMPTY B
402 EMPTY
HSO8_DN
R53CV EXP_B_TX_0_R_DN
36 22 IN 1 2 OUT 25
36 23
HSI7_DP 1 R48CV 2 EXP_B_RX_1_DP 25
0 5%
IN OUT 402 EMPTY
0 5%
402 EMPTY EXP_B_TX_0_R_DP 1
C6CV
2 EXP_B_TX_0_C_DP HSO7_DP R54CV
25 IN OUT 25 36 23 IN 1 2 EXP_B_TX_1_R_DP
OUT 25
.1UF 10% 0 5%
10V402 X5R
HSI7_DN 1 R49CV 2 EXP_B_RX_1_DN 402 EMPTY
36 23 IN OUT 25
C7CV R55CV EXP_B_TX_1_R_DN
0 5% EXP_B_TX_0_R_DN 1 2 EXP_B_TX_0_C_DN HSO7_DN 1 2
25 25 36 23 IN OUT 25
402 EMPTY IN OUT 0 5%
.1UF 10%
10V402 X5R 402 EMPTY
36 24
HSI6_DP 1 R50CV 2 EXP_B_RX_2_DP 25
IN OUT R56CV
0 5% EXP_B_TX_1_R_DP C8CV HSO6_DP EXP_B_TX_2_R_DP
402 EMPTY 1 2 EXP_B_TX_1_C_DP 36 24 IN 1 2 OUT 25
25 IN OUT 25
.1UF 10% 0 5%
10V402 402 EMPTY
36 24 HSI6_DN 1 R51CV 2 EXP_B_RX_2_DN 25
X5R
R57CV
IN OUT HSO6_DN 1 2 EXP_B_TX_2_R_DN
0 5% C9CV 36 24 IN OUT 25
402 EMPTY EXP_B_TX_1_R_DN 1 2 EXP_B_TX_1_C_DN
25 IN OUT 25 0 5%
.1UF 10% 402 EMPTY
1 R133CV 2 HSI5_R_R_DP
114
10V402 X5R
OUT R138CV
0 5% C10CV HSO5_R_R_DP
A 402 EMPTY 25
EXP_B_TX_2_R_DP 1 2 EXP_B_TX_2_C_DP 25
1 2 OUT 114 A
IN OUT 0 5%
.1UF 10%
36
TPEV_HSI5_DP 1 R131CV 2 EXP_B_RX_3_DP 25 10V402 X5R R140CV 402 EMPTY
IN OUT 36
TPEV_HSO5_DP
1 2 EXP_B_TX_3_R_DP
25
0 5% IN OUT
402 CH C11CV 0 5%
EXP_B_TX_2_R_DN 1 2 EXP_B_TX_2_C_DN 402 CH
25 IN OUT 25
1 R132CV 2 .1UF 10% R137CV EXP_B_TX_3_R_DN
36 TPEV_HSI5_DN EXP_B_RX_3_DN 10V402 36 TPEV_HSO5_DN 1 2
IN OUT 25 X5R IN OUT 25
0 5% 0 5%
402 CH C12CV R139CV 402 CH
HSO5_R_R_DN
25 EXP_B_TX_3_R_DP 1 2 EXP_B_TX_3_C_DP 25 1 2
IN OUT OUT 114
1 R134CV 2 HSI5_R_R_DN
114 .1UF 10%
OUT 0 5%
10V402 X5R 402 EMPTY
0 5%
402 EMPTY
C13CV
DESIGN NOTE:
25 IN
EXP_B_TX_3_R_DN 1 2 EXP_B_TX_3_C_DN
OUT 25 [PAGE_TITLE=PCIEX4 SLOT]
.1UF 10%
10V402 X5R BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
OVERLAP RES WITH X1 PCIE (R34CV, R38CV, R42CV ETC) INTEL
hc_cdb_mpi.sch_1.25
2 1
A
B
C
D
27
27
27
27
8
8
8
8
8
8
8
8
90
27
29
93
16
27
IN
IN
IN
8
11
91
38
26
28
BI
111
IN
IN
IN
IN
CR-26
BI
:
IN
8
8
M_CAS_A_N
M_WE_A_N
M_RAS_A_N
V_SM
1
1
1
J1MY
1.00UF
1.00UF
1.00UF
DDR3_SODIMM_SM
402
402
402
402
6.3V
6.3V
6.3V
10V
X5R
X5R
X5R
X5R
REV=1
C87MY
C30MY
C29MY
C28MY
113 194
1
63
M_MAA_A<15..0>
.1UF 10%
WE* DQ63
20%
20%
20%
2
2
2
110 RAS* DQ62 192 62
CK_M_DDR3_A_DP
CK_M_DDR2_A_DP
CK_M_DDR3_A_DN
CK_M_DDR2_A_DN
115 CAS* DQ61 182 61
180 60
M_DATA_A<63..0>
DQ60
15 78 A15/BA3 DQ59 193 59
14 80 A14 DQ58 191 58
13 119 A13 DQ57 183 57
12 83 A12/BC* DQ56 181 56
11 84 A11 DQ55 176 55
2
2
2
2
2
.1UF
.1UF
.1UF
107 174 54
.1UF
.1UF
10V
10
10V
10V
A10/AP DQ54
10V
10V
PLACE
85 166
7
@HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE26
9 A9 DQ53 53
7
8 89 A8/A7 DQ52 164 52
C18MY
C63MY
C64MY
C62MY
C61MY
86 177
402
51
402
402
7
1
A7/A8 DQ51
402
402
X5R
1
1
X5R
X5R
10%
CAD NOTE:
10%
10%
X5R
X5R
10%
10%
6 90 A6/A5 DQ50 175 50
5 91 A5/A6 DQ49 165 49
4 92 A4/A3 DQ48 163 48
3 95 A3/A4 DQ47 160 47
2 96 A2 DQ46 158 46
1 97 A1 DQ45 148 45
29
27
0 98 A0 DQ44 146 44
AT CHA DIMM0
DQ43 159 43
91
28
26
101 CK0 DQ42 157 42
103 CK0* DQ41 149 41
102 147
IN
CK1 DQ40 40
104 CK1* DQ39 142 39
DQ38 140 38
2 114 S0* DQ37 132 37
3 121 S1* DQ36 130 36
DQ35 143 35
73 141 34
DESIGN NOTE:
2 CKE0 DQ34
74 131
6
3 CKE1 DQ33 33
6
CH A V_SM_VTT
DQ32 129 32
2 79 BA2 DQ31 70 31
V_SM_VTT
1 108 BA1/BA0 DQ30 68 30
0 109 BA0/BA1 DQ29 58 29
2
DQ28 56 28
197 SA0 DQ27 69 27
10V
201 67 26
10%
X5R
SA1 DQ26
1206
4.7UF
DQ25 59 25
C54MY
200 57 24
DECOUPLING
SDA DQ24
202 SCL DQ23 52 23
126 VREF_CA DQ22 50 22
2
1 VREF_DQ DQ21 42 21
199 40 20
CAPS
VDDSPD DQ20
53
402
19
16V
Y5V
DQ19
20%
187 51
0.1UF
DM7 DQ18 18
170 41 17
C53MY
DM6 DQ17
153 DM5 DQ16 39 16
PRELIMINARY
136 DM4 DQ15 36 15

63 DM3 DQ14 34 14
46 24
5
DM2 DQ13 13
CHANNEL A DIMM0
5
28 DM1 DQ12 22 12
11 DM0 DQ11 35 11
402
16V
Y5V
20%
DQ10 33 10
0.1UF
7 186 DQS7* DQ9 23 9
CAD NOTE:
7 188 21 8
C125MY
DQS7 DQ8
6 169 DQS6* DQ7 18 7
6 171 DQS6 DQ6 16 6
5 152 DQS5* DQ5 6 5
402
16V
Y5V
154 4
20%
5 4
CAD NOTE:
DQS5 DQ4
0.1UF
DO NOT PUNCH VIA.

4 135 DQS4* DQ3 17 3
GENERAL NOTE:
4 137 DQS4 DQ2 15 2
C126MY
3 62 DQS3* DQ1 7 1
3 64 DQS3 DQ0 5 0
2 45 DQS2*
2 47 DQS2 ODT0 116 2
PLACE BETWEEN CHA & CHB.

1 27 120
VCC3
DQS1* ODT1 3
1 29 DQS1
0 10 DQS0* RST* 30
0 12 DQS0
4
4
1 OF 2
CONN
J1MY
DDR3_SODIMM_SM
REV=1
M_ODT_A<3..2>
2 GND VDD 75
DDR3_DRAMRST_N
3 GND VDD 76
M_SBS_A<2..0>
8 81
M_SCKE_A<3..2>
GND VDD
M_SCS_A_N<3..2>
M_DQS_A_DP<7..0>
SMB_CLK_MAIN
9 82
M_DQS_A_DN<7..0>
GND VDD
SMB_DATA_MAIN
DIMM_CA_VREF_A
DIMM_DQ_R_VREF_A
13 GND VDD 87
14 GND VDD 88
19 GND VDD 93
20 GND VDD 94
IN
25 99
BI
BI
BI
BI
BI
BI
BI
GND VDD
IN
IN
BI
26 GND VDD 100

8
3
31 105
3
GND VDD
8
8
8
8
32 106
27
GND VDD
hc_cdb_mpi.sch_1.26
Mon Apr 16 13:57:40
37 111
8 27
27
GND VDD
27
16 27
17 27
27 28
27 28
28
38 GND VDD 112

43 GND VDD 117
BPAGE DRAWING
29
29
29
44 GND VDD 118

2012
48 GND VDD 123

77
77
49 GND VDD 124

54
81
81
GND
55 GND VTT 203
60 GND VTT 204
113
113
61 GND
65 GND
116
116
66 GND
71 GND
72 GND
127 GND
128 GND
ALWAYS POPULATE THE FURTHEST DIMM FROM CPU FIRST
133 GND
134 GND
2
138
2
GND
139
CUSTOM TEXT BPAGE
GND
PRELIMINARY
144 GND
INTEL
145
V_SM
GND
V_SM_VTT
150 GND
CONFIDENTIAL
151 GND
155 GND
[PAGE_TITLE=CONN
156 GND
Vinafix
161 GND
IN
IN
162 GND
167 GND
168 GND
111
172 198
MODULE NAME
GND THERM_EVENT*
26 27
11 16
173 GND
178 GND NC 77
28
26
DDR3,
179 GND NC 122

184 GND NC_TEST 125
29
27
DIMM:
PLACE DIMM 0 FOR EACH CHANNEL AS THE FURTHEST DIMM FROM THE CPU
185 GND
189 205
91
28
GND (PEG) MTG

190 206
SPD=SERIAL
REV
GND (PEG) MTG

DOCUMENT_NUMBER
<DOCUMENT_NUMBER>
29
195 207
1
GND (PAD) MTG

1
196 GND (PAD) MTG 208

38
NC
NC
2 OF 2
DESIGN NOTE:
CH A SPD READ/WR:
CH A BANK 1
26
90
TPEV_DRAM_A_1_EXTTS_N
PRESENCE
MODULE REV DETAILS
CH A SMB ADDRESS 000
CONN
PAGE
0*A1,
91
NC_DIMM0_CHA_206
NC_DIMM0_CHA_205
NC_DIMM1_CHA_125
DATE
93
DETECT
1.0
0*A0
OUT
CH A DIMM0]
REV
A
B
C
D
93
28
A
B
C
D
91
27
90
26
26
26
26
26
26
8
8
8
8
8
111
8
8
8
8
16 11
38 29
IN
IN
IN
BI
BI
IN
IN
IN
IN
CR-27
IN
:
8
8
M_CAS_A_N
M_WE_A_N
M_RAS_A_N
V_SM
1
1
1
1
J2MY
1.00UF
1.00UF
1.00UF
1.00UF
DDR3_SODIMM_SM
402
402
402
402
6.3V
6.3V
6.3V
6.3V
X5R
X5R
X5R
X5R
C9MY
C8MY
C7MY
C10MY
REV=1
20%
20%
20%
20%
113 194 63
2
2
2
2
M_MAA_A<15..0>
WE* DQ63
M_DATA_A<63..0>
110 RAS* DQ62 192 62
CK_M_DDR1_A_DP
CK_M_DDR0_A_DP
CK_M_DDR1_A_DN
CK_M_DDR0_A_DN
115 CAS* DQ61 182 61
DQ60 180 60
15 78 A15/BA3 DQ59 193 59
14 80 A14 DQ58 191 58
13 119 A13 DQ57 183 57
12 83 A12/BC* DQ56 181 56
11 84 A11 DQ55 176 55
10 107 A10/AP DQ54 174 54
9 85 A9 DQ53 166 53
7
89 164
7
8 A8/A7 DQ52 52
7 86 A7/A8 DQ51 177 51
2
2
2
90 175
2
50
.1UF
6
.1UF
A6/A5 DQ50
.1UF
.1UF
.1UF
10V
10V
10V
10V
10V
5 91 165 49
PLACE
A5/A6 DQ49
4 92 A4/A3 DQ48 163 48
C79MY
C77MY
C76MY
95 160
C78MY
C75MY
3 A3/A4 DQ47 47
402
402
402
1
402
1
402
1
X5R
1
1
X5R
10%
X5R
10%
X5R
X5R
10%
10%
10%
96 158 46
CAD NOTE:
2 A2 DQ46
1 97 A1 DQ45 148 45
0 98 A0 DQ44 146 44
DQ43 159 43
101 CK0 DQ42 157 42
103 CK0* DQ41 149 41
102 CK1 DQ40 147 40
AT CHA DIMM1
104 CK1* DQ39 142 39
DQ38 140 38
0 114 S0* DQ37 132 37
1 121 S1* DQ36 130 36
DQ35 143 35
0 73 CKE0 DQ34 141 34
11
91
93
90
29
27
26
28
38
16
74 131 33
111
1 CKE1 DQ33
6
129
6
DQ32 32
79 70
IN
2 BA2 DQ31 31
1 108 BA1/BA0 DQ30 68 30
0 109 BA0/BA1 DQ29 58 29
DQ28 56 28
197 SA0 DQ27 69 27
201 SA1 DQ26 67 26
DQ25 59 25
V_SM
200 SDA DQ24 57 24
202 SCL DQ23 52 23
126 VREF_CA DQ22 50 22
199 VDDSPD DQ20 40 20
53
1
19
2
DQ19
187 DM7 DQ18 51 18
170 DM6 DQ17 41 17
805
X5R
20%
153 39 16
6.3V
DM5 DQ16
PRELIMINARY
136 DM4 DQ15 36 15
C6MY
63 DM3 DQ14 34 14
22.000UF
46 DM2 DQ13 24 13
5
28 22
5
DM1 DQ12 12
CHANNEL A DIMM1
11 35
1
11
2
DM0 DQ11
DQ10 33 10
7 186 DQS7* DQ9 23 9
805
X5R
20%
7 188 21 8
6.3V
DQS7 DQ8
6 169 DQS6* DQ7 18 7
C17MY
6 171 DQS6 DQ6 16 6
22.000UF
5 152 DQS5* DQ5 6 5
5 154 DQS5 DQ4 4 4
135 17
1
4 3
2
DQS4* DQ3
4 137 DQS4 DQ2 15 2
3 62 DQS3* DQ1 7 1
805
X5R
20%
3 64 5 0
6.3V
DQS3 DQ0
2 45 DQS2*
C19MY
2 47 DQS2 ODT0 116 0
22.000UF
1 27 120
VCC3
DQS1* ODT1 1
1 29 DQS1
10 30
1
0
2
DQS0* RST*
0 12 DQS0
CAD NOTE:
4
805
1 OF 2
X5R
20%
4
6.3V
CONN
C21MY
22.000UF
1
2
J2MY
805
X5R DDR3_SODIMM_SM
20%
6.3V
REV=1
M_ODT_A<1..0>
2 GND VDD 75
C22MY
DDR3_DRAMRST_N
22.000UF
3 GND VDD 76
M_SBS_A<2..0>
8 81
M_SCKE_A<1..0>
GND VDD
M_SCS_A_N<1..0>
M_DQS_A_DP<7..0>
SMB_CLK_MAIN
9 82
M_DQS_A_DN<7..0>
SMB_DATA_MAIN
GND VDD
DIMM_DQ_R_VREF_A
DIMM_CA_VREF_A
13 GND VDD 87
14 GND VDD 88
19 GND VDD 93
20 GND VDD 94
IN
25 99
BI
BI
BI
BI
BI
BI
BI
GND VDD
IN
IN
BI
26 GND VDD 100

8
31 105
3
GND VDD
8
8
8
8
3
8
32 106
26
GND VDD
hc_cdb_mpi.sch_1.27
37 111
8 26
26
GND VDD
Mon Apr 16 13:57:41
26
16 26
17 26
26 28
26 28
28
38 GND VDD 112

43 GND VDD 117
29
29
29
BPAGE DRAWING
44 GND VDD 118

48 GND VDD 123
77
77
2012
49 GND VDD 124

54
81
81
GND
91
55 GND VTT 203

60 GND VTT 204
113
113
29
61 GND
65
28
GND
116
116
66 GND
71
27
GND
72 GND
26
127 GND
[PAGE_TITLE=CONN
128 GND
133 GND
IN
134 GND
138
2
GND
2
139 GND
PRELIMINARY
CUSTOM TEXT BPAGE
144 GND
INTEL
145
V_SM
GND
V_SM_VTT
150 GND
DDR3,
151
CONFIDENTIAL
GND
155
V_SM_VTT
GND
1
156 GND
161 GND
IN
IN
162
10V
GND
10%
X5R
1206
167
4.7UF
GND
168
C51MY
GND
111
172 GND THERM_EVENT* 198

MODULE NAME
26 27
11 16
173 GND
178 GND NC 77
28
26
179 GND NC 122

184 125
1
GND NC_TEST
29
27
185 GND
189 205
91
28
GND (PEG) MTG

CH A DIMM1]
402
DIMM:
16V
Y5V
190 206
20%
GND (PEG) MTG

REV
0.1UF
DOCUMENT_NUMBER
<DOCUMENT_NUMBER>
29

1
C52MY
SPD=SERIAL
196 208
1
GND (PAD) MTG

38
NC
NC
NC
NC
2 OF 2
90
27
CONN
DESIGN NOTE:
TPEV_DRAM_A_0_EXTTS_N
MODULE REV DETAILS
CH A SPD READ/WR:
PAGE
CH A BANK 2
91
NC_DIMM0_CHA_125
PRESENCE
93
DATE
0*A3,
1.0
OUT
REV
DETECT
0*A2
A
B
C
D
A
B
C
D
90
27
111
29
29
38
26
29
29
29
9
9
9
9
9
29
93
16
9
9
9
9
11
91
28
IN
IN
IN
BI
BI
IN
IN
IN
IN
CR-28
IN
:
8
8
M_CAS_B_N
M_WE_B_N
M_RAS_B_N
V_SM
1
1
1
1
J3MY
1.00UF
1.00UF
1.00UF
1.00UF
DDR3_SODIMM_SM
402
402
402
402
6.3V
6.3V
6.3V
6.3V
X5R
X5R
X5R
X5R
REV=1
C34MY
C33MY
C32MY
C16MY
113 194 63
M_MAA_B<15..0>
WE* DQ63
20%
20%
20%
20%
2
2
2
2
110 192
M_DATA_B<63..0>
RAS* DQ62 62
CK_M_DDR3_B_DP
CK_M_DDR2_B_DP
CK_M_DDR3_B_DN
CK_M_DDR2_B_DN
115 CAS* DQ61 182 61
DQ60 180 60
15 78 A15/BA3 DQ59 193 59
14 80 A14 DQ58 191 58
13 119 A13 DQ57 183 57
12 83 A12/BC* DQ56 181 56
11 84 A11 DQ55 176 55
10 107 A10/AP DQ54 174 54
9 85 A9 DQ53 166 53
7
89 164
7
8 A8/A7 DQ52 52
2
2
2
2
86 177
.1UF
51
.1UF
7
.1UF
A7/A8 DQ51
.1UF
.1UF
10V
10V
10V
10V
10V
6 90 A6/A5 DQ50 175 50
PLACE
5 91 A5/A6 DQ49 165 49
C15MY
C12MY
C13MY
C11MY
C14MY
4 92 163 48
402
A4/A3 DQ48
402
402
1
402
1
402
1
X5R
1
1
X5R
10%
X5R
10%
X5R
10%
X5R
10%
10%
3 95 A3/A4 DQ47 160 47
CAD NOTE:
2 96 A2 DQ46 158 46
1 97 A1 DQ45 148 45
0 98 A0 DQ44 146 44
DQ43 159 43
101 CK0 DQ42 157 42
103 CK0* DQ41 149 41
102 147 40
AT CHB DIMM0
CK1 DQ40
104 CK1* DQ39 142 39
DQ38 140 38
2 114 S0* DQ37 132 37
3 121 S1* DQ36 130 36
DQ35 143 35
2 73 CKE0 DQ34 141 34
3 74 CKE1 DQ33 131 33
6
129
6
DQ32 32
2 79 BA2 DQ31 70 31
1 108 BA1/BA0 DQ30 68 30
0 109 BA0/BA1 DQ29 58 29
DQ28 56 28
197 SA0 DQ27 69 27
201 SA1 DQ26 67 26
DQ25 59 25
200 SDA DQ24 57 24
202 SCL DQ23 52 23
126 VREF_CA DQ22 50 22
199 VDDSPD DQ20 40 20
DQ19 53 19
187 DM7 DQ18 51 18
170 DM6 DQ17 41 17
153 39
91
DM5 DQ16 16
PRELIMINARY
136 DM4 DQ15 36 15
29
63 DM3 DQ14 34 14
46 DM2 DQ13 24 13
5
28
CHANNEL B DIMM0
28 22
5
DM1 DQ12 12
11 DM0 DQ11 35 11
27
DQ10 33 10
7 186 23 9
26
DQS7* DQ9
7 188 DQS7 DQ8 21 8
6 169 DQS6* DQ7 18 7
IN
6 171 DQS6 DQ6 16 6
5 152 DQS5* DQ5 6 5
5 154 DQS5 DQ4 4 4
4 135 DQS4* DQ3 17 3
4 137 DQS4 DQ2 15 2
3 62 7 1
DESIGN NOTE:
DQS3* DQ1
3 64 5 0
GENERAL NOTE:
DQS3 DQ0
45
CH B V_SM_VTT
2 DQS2*
2 47 DQS2 ODT0 116 2
2
V_SM_VTT
1 27 120
VCC3
DQS1* ODT1 3
1 29 DQS1
0 10 30
10V
10%
DQS0* RST*
X5R
1206
4.7UF
0 12 DQS0
C45MY
4
1 OF 2
4
CONN
DECOUPLING
1
2
CAD NOTE:
402
16V
Y5V
20%
0.1UF
CAPS
J3MY
C46MY
DDR3_SODIMM_SM
REV=1
M_ODT_B<3..2>
2 GND VDD 75
DDR3_DRAMRST_N
3 GND VDD 76
M_SBS_B<2..0>
8 81
M_SCKE_B<3..2>
GND VDD
M_SCS_B_N<3..2>
M_DQS_B_DP<7..0>
SMB_CLK_MAIN
9 82
M_DQS_B_DN<7..0>
SMB_DATA_MAIN
GND VDD
DIMM_CA_VREF_B
DIMM_DQ_R_VREF_B
13 GND VDD 87
14 GND VDD 88
19 GND VDD 93
20 GND VDD 94
IN
25 99
BI
BI
BI
BI
BI
BI
BI
GND VDD
IN
IN
BI
26 GND VDD 100

8
31 105
3
GND VDD
9
9
9
9
3
9
32 106
26
GND VDD
hc_cdb_mpi.sch_1.28
37 111
9 29
29
GND VDD
Mon Apr 16 13:57:41
29
16 29
17 29
26 27
26 27
27
38 GND VDD 112

43 GND VDD 117
29
29
29
BPAGE DRAWING
44 GND VDD 118

48 GND VDD 123
77
77
2012
49 GND VDD 124

54
81
81
GND
55 GND VTT 203
60 GND VTT 204
113
113
61 GND
65 GND
116
116
66 GND
71 GND
72 GND
127 GND
128 GND
133 GND
134 GND
138
2
GND
2
139 GND
PRELIMINARY
CUSTOM TEXT BPAGE
144 GND
INTEL
145
V_SM
GND
V_SM_VTT
150 GND
[PAGE_TITLE=CONN
151
CONFIDENTIAL
GND
155 GND
156 GND
161 GND
IN
IN
162 GND
167 GND
168 GND
111
172 GND THERM_EVENT* 198

MODULE NAME
26 27
11 16
DDR3,
173 GND
ALWAYS POPULATE THE FURTHEST DIMM FROM CPU FIRST
178 GND NC 77
28
26
179 GND NC 122

184 GND NC_TEST 125
29
27
DIMM:
185 GND
189 205
91
28
GND (PEG) MTG

190 206
SPD=SERIAL
GND (PEG) MTG

REV
DOCUMENT_NUMBER
<DOCUMENT_NUMBER>
29

1
196 208
1
GND (PAD) MTG

38
NC
NC
NC
NC
2 OF 2
DESIGN NOTE:
CH A SPD READ/WR:
CH A BANK 1
90
28
PRESENCE
CONN
TPEV_DRAM_B_1_EXTTS_N
MODULE REV DETAILS
PAGE
0*A1,
91
NC_DIMM1_CHB_125
CH B DIMM0]
93
DATE
DETECT
0*A0
1.0
OUT
REV
A
B
C
D
A
B
C
D
91
29
26
28
28
28
28
9
28
90
16
28
9
9
9
9
9
9
9
9
11
93
27
38
BI
111
IN
IN
IN
BI
IN
IN
IN
IN
CR-29
IN
:
8
8
M_WE_B_N
V_SM
1
1
1
1
M_CAS_B_N
M_RAS_B_N
1.00UF
1.00UF
1.00UF
1.00UF
J4MY
402
402
402
402
6.3V
6.3V
6.3V
6.3V
X5R
X5R
X5R
X5R
DDR3_SODIMM_SM
C27MY
C26MY
C25MY
C24MY
20%
20%
20%
20%
2
2
2
2
REV=1
M_DATA_B<63..0>
113 194 63
M_MAA_B<15..0>
WE* DQ63
110 RAS* DQ62 192 62
CK_M_DDR1_B_DP
CK_M_DDR0_B_DP
CK_M_DDR1_B_DN
CK_M_DDR0_B_DN
115 CAS* DQ61 182 61
DQ60 180 60
15 78 A15/BA3 DQ59 193 59
14 80 A14 DQ58 191 58
13 119 A13 DQ57 183 57
12 83 A12/BC* DQ56 181 56
11 84 A11 DQ55 176 55
10 107 A10/AP DQ54 174 54
85 166
7
9 A9 DQ53 53
7
8 89 A8/A7 DQ52 164 52

7 86 A7/A8 DQ51 177 51
90 175 50
2
6
2
A6/A5 DQ50
.1UF
.1UF
.1UF
.1UF
.1UF
10V
10V
10V
10V
10V
5 91 A5/A6 DQ49 165 49
PLACE
4 92 A4/A3 DQ48 163 48
3 95 160 47
C94MY
C91MY
A3/A4 DQ47
C92MY
C90MY
C93MY
402
402
402
1
402
1
402
1
96 158
X5R
1
1
X5R
46
10%
X5R
10%
2
X5R
X5R
10%
A2 DQ46
10%
10%
CAD NOTE:
1 97 A1 DQ45 148 45
0 98 A0 DQ44 146 44
DQ43 159 43
101 CK0 DQ42 157 42
103 CK0* DQ41 149 41
102 CK1 DQ40 147 40
104 CK1* DQ39 142 39
AT CHB DIMM1
DQ38 140 38
0 114 S0* DQ37 132 37
1 121 S1* DQ36 130 36
DQ35 143 35
0 73 CKE0 DQ34 141 34
74 131
6
1 CKE1 DQ33 33
6
DQ32 129 32
2 79 BA2 DQ31 70 31
1 108 BA1/BA0 DQ30 68 30
0 109 BA0/BA1 DQ29 58 29
DQ28 56 28
197 SA0 DQ27 69 27
201 SA1 DQ26 67 26
DQ25 59 25
200 SDA DQ24 57 24
202 SCL DQ23 52 23
126 VREF_CA DQ22 50 22
199 VDDSPD DQ20 40 20
DQ19 53 19
187 DM7 DQ18 51 18
170 DM6 DQ17 41 17
91
153 DM5 DQ16 39 16
PRELIMINARY
136 36 15
29
DM4 DQ15
CHANNEL B DIMM1
63 DM3 DQ14 34 14
46 24
28
5
DM2 DQ13 13
5
28 DM1 DQ12 22 12
27
11 DM0 DQ11 35 11
DQ10 33 10
26
7 186 DQS7* DQ9 23 9
7 188 DQS7 DQ8 21 8
169 18
IN
6 DQS6* DQ7 7
6 171 DQS6 DQ6 16 6
5 152 DQS5* DQ5 6 5
5 154 DQS5 DQ4 4 4
135 17
DESIGN NOTE:
4 DQS4* DQ3 3
4 137 DQS4 DQ2 15 2
CH B V_SM_VTT
3 62 DQS3* DQ1 7 1
3 64 DQS3 DQ0 5 0
V_SM_VTT
2
2 45 DQS2*
2 47 DQS2 ODT0 116 0
10V
27 120
10%
X5R
1
VCC3
DQS1* ODT1 1
1206
4.7UF
1 29 DQS1
C39MY
0 10 DQS0* RST* 30
0 12 DQS0
4
DECOUPLING
4
1 OF 2
CONN
1
2
CAD NOTE:
CAPS
402
16V
Y5V
20%
0.1UF
J4MY
C40MY
DDR3_SODIMM_SM
REV=1
M_ODT_B<1..0>
2 GND VDD 75
DDR3_DRAMRST_N
3 GND VDD 76
M_SBS_B<2..0>
8 81
M_SCKE_B<1..0>
GND VDD
M_SCS_B_N<1..0>
M_DQS_B_DP<7..0>
SMB_CLK_MAIN
9 82
M_DQS_B_DN<7..0>
GND VDD
SMB_DATA_MAIN
DIMM_CA_VREF_B
DIMM_DQ_R_VREF_B
13 GND VDD 87
14 GND VDD 88
19 GND VDD 93
20 GND VDD 94
IN
25 99
BI
BI
BI
BI
BI
BI
BI
GND VDD
IN
IN
BI
26 GND VDD 100

8
3
31 105
3
GND VDD
9
9
9
9
32 106
26
GND VDD
hc_cdb_mpi.sch_1.29
Mon Apr 16 13:57:42
37 111
9 28
28
GND VDD
28
16 28
17 28
26 27
26 27
27
38 GND VDD 112

43 GND VDD 117
BPAGE DRAWING
28
28
28
44 GND VDD 118

2012
48 GND VDD 123

77
77
49 GND VDD 124

54
81
81
GND
55 GND VTT 203
60 GND VTT 204
113
113
61 GND
65 GND
116
116
66 GND
71 GND
72 GND
127 GND
128 GND
DIMM:
133 GND
134 GND
2
SPD=SERIAL
138
2
GND
139
CUSTOM TEXT BPAGE
GND
PRELIMINARY
144 GND
INTEL
145
V_SM
GND
DESIGN NOTE:
CH B SPD READ/WR:
V_SM_VTT
CH B BANK 2
150 GND
CONFIDENTIAL
PRESENCE
151
CH B SMB ADDRESS 011
GND
[PAGE_TITLE=CONN
155
0*A7,
GND
156 GND
161
DETECT
GND
IN
IN
0*A6
162 GND
167 GND
168 GND
111
172 198
MODULE NAME
GND THERM_EVENT*
26 27
11 16
173 GND
DDR3,
178 GND NC 77
28
26
179 GND NC 122

184 GND NC_TEST 125
29
27
185 GND
189 205
91
28
GND (PEG) MTG

190 206
REV
GND (PEG) MTG

DOCUMENT_NUMBER
<DOCUMENT_NUMBER>
29
195 207
1
GND (PAD) MTG

1

38
NC
NC
NC
NC
2 OF 2
TPEV_DRAM_B_0_EXTTS_N
29
90
MODULE REV DETAILS
CONN
PAGE
91
NC_DIMM0_CHB_125
DATE
93
CH B DIMM1]
1.0
OUT
REV
A
B
C
D
8 7 6 5 4 3 2 1
MODULE REV DETAILS

V_3P3_A
94 89 82 81 78 77 67 49 41 32 IN
102 100 95
1 1 1
R27BV R31BV R39BV
22K
0 5% 22K
5% 5%
CH CH
402 402 CH
2 402
D 2 2 2 R59BV 1 SLP_SUS_FET
Q11BV_P4
XSTR IN 30 32 95 103 D
4 1 0 5%
402 EMPTY
30 SLP_SUSB_AMP 1 R2BV 2 Q11BV_P5 Q11BV_P2
R40BV
IN
15K 5% 5 2 10K 5%
402 EMPTY 402 CH
MBT3906DUAL 3 6 2 R53BV 1 SLP_SUS_FET2
32 95 103
Q11BV OUT
Q11BV_P6
0 5% BOM NOTE:
402 CH
STUFF R53BV,R2BV, EMPTY R59BV
1 1 1
C9BV C11BV FOR USING SLP_SUS_FET2 CIRCUIT
1UF 2.2UF R48BV
10% 20%
16V 16V 10K
2 X5R 2 EMPTY 5%
603 805 CH Q14BV_P6
402
2
Q14BV_P3
Q14BV
MBT3904DUAL 3 6
C SLP_SUS_N
2 R49BV 1 Q14BV_P5 5 2 Q14BV_P2 PCH_RSMRST_N C
104 78 38 32 30 IN 2 R55BV 1
30 38 78 103 116
22K 5% 1 IN
402 CH 1 10K 5%
R51BV 4 1 XSTR 402 CH
15K R52BV
5% 4.7K
5%
CH
402 EMPTY
2 402
2
V_5P0_A
98 96 95 94 89 78 77 44 32 31 IN
112
1 1 1
1 1 R250BV
R233BV R242BV 22K R251BV
R237BV 0 5% 22K
22K 5% 5%
5% 22K CH CH
5% 402 402 CH
CH 402
402 CH
2 2 2
B 2 402 B
2 Q44BV_P4_R242BV
XSTR
SLP_SUSB_AMP 4 1
30 OUT
2 R239BV 1 Q44BV_P5_R239BV Q44BV_P2_R249BV
R249BV
10K 5% 5 2 10K 5%
Q43BV_P3_R233BV
1 402 CH 402 CH
Q43BV MBT3906DUAL 3 6 2 R269BV 1 SLP_SUS_FET
30 32 95 103
MBT3904DUAL 3 6 R238BV Q44BV OUT
0 5%
SLP_SUS_N 1M Q44BV_P6_R248BV
402 CH
38 32 30
2 R232BV 1 5 2 5%
104 78
IN Q43BV_P5_R232BV EMPTY
22K 5% 402 1 1
2
402 CH
XSTR 2 C148BV C146BV R248BV BOM NOTE:
1 4 1 1 1UF 2.2UF 15K
10% 20%
16V 16V 5% FOR LPT FAST BOOT EXP,
R234BV R236BV 2 X5R 2 EMPTY
15K 1M 603 805
CH C148BV CHANGE TO 1UF (C51601-001)
402 Q45BV_P6_R269BV
5% 5%
R248BV CHANGE TO 15K (A93549-024)
1
CH EMPTY
402 402
2 2
Q45BV_P3_R249BV
Q45BV
MBT3904DUAL 3 6
A PCH_RSMRST_N A
2 R235BV 1 Q45BV_P5_R240BV 5 2 Q45BV_P2_R241BV 2 R244BV 1
30 38 78 103 116
IN
22K 5% 1 10K 5%
402 CH 1 402 CH
R240BV 4 1 XSTR
15K R241BV
5% 4.7K
CH 5%
402 EMPTY
2 402
2
[PAGE_TITLE= DSW SEQUENCING]

hc_cdb_mpi.sch_1.30
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

V_5P0_A 2 MODULE NAME REV DATE
112 98 96 95 94 89 78 77 44 32 31 30 IN 1 BOM NOTE: R258BV
R256BV 22K
22K STUFF R268BV FOR USB WAKE S4/S5 5%
2 5% CH
CH 402
R254BV 402 1
22K 2 VREG_5VDUAL_PCH
D 2 5% Q47BV_P1_R268BV
2 R268BV 1
OUT 96 100
R247BV CH
XSTR 4 1 D
402 0 5%
22K 1 402 CH
5%
CH Q46BV_P6_R255BV 2 R255BV 1 Q47BV_P2_R257BV R257BV
402 Q47BV_P5_R255BV 5 2
1 10K 5% 10K 5%
Q46BV_P3_R247BV 402 CH 402 CH
MBT3906DUAL 3 6
Q47BV
1
Q47BV_P3_R267BV
Q46BV R253BV
MBT3904DUAL 3 6 1M Q47BV_P6_R262BV
5% 1
SUS_WARNB
103 96 38 31
2 R245BV 1 Q46BV_P5_R246BV 5 2 EMPTY
IN 402 R267BV
22K 5% 1 2 1K
402 EMPTY 1 5%
4 1 XSTR R252BV CH
2 R80BV 1 R246BV 1M 402
15K 5% 2
22K 5% 5% EMPTY
402 CH
EMPTY 402
402 2
2
112
C 104
1 1 C
98
C128BV 1
96
10UF C129BV R262BV
90 1UF 47K
66 3 10% 10%
Q48BV_P1_R261BV 16V 5%
59
1 Q48BV 2 X5R 2 16V
CH
57 MMBT3904 805 EMPTY
55 1 R63BV 2 603 402
31 IN 5VDUAL XSTR 2
54 R261BV 1 1 2
2
56 22K 5% C130BV C132BV
58 402 CH 10K 2.2UF 1UF
60 5% 10% 10%
84 6.3V 16V
SUS_PWR_ACK 2 R260BV 1 CH 2 EMPTY 2 X5R
104 96 38 IN 402 603 603
10K 5% Q49BV_P3_R258BV
402 EMPTY
1
3 Q49BV
Q49BV_P5_R263BV
2 R263BV 1 5
22K 5%
402 EMPTY
1 BOM NOTE: 4 Q49BV_P4_Q49BV_P6
B SUS_WARN_DELAY_N 2 R81BV 1 B
31 IN R264BV MBT3904DUAL
22K 5% 15K STUFF R265BV AND EMPTY R270BV FOR USB WAKE FROM S4/S5
402 CH 5% STUFF R270BV AND EMPTY R265BV FOR USB WAKE FROM S3 ONLY
BOM NOTE: CH
402 6
FOR USING 5VDUAL AS INPUT: 2
CHANGE R261BV TO 10K RES 100 96 94 80 77 BACKFEED_CUT_N
2 R265BV 1 Q49BV_P2 2
IN
EMPTY R260BV & R253BV, STUFF R63BV 22K 5%
402 CH
1
100 96 94 80 LATCHED_BACKFEED_CUT 2 R270BV 1 1
98 96 95 94 89 78 77 44 32 31 30
V_5P0_A IN R266BV
112
IN 22K 5% 4.7K
1 R87BV 402 EMPTY 5% XSTR
1K EMPTY
5% 402
1 R84BV 2 CH 2
4.7K 402 SUS_WARN_DELAY_N
5% 31
3 OUT
2 CH
R85BV
402 Q36BV
Q28BV_PIN3 1 2 Q36BV_PIN5 5
3 XSTR
10K 5% 3904DUAL
112 104 98 R82BV 402 CH
58 57 56 55 54 31
5VDUAL 1 2 Q28BV_PIN5 5 Q28BV 4
96 90 84 66 60 59
IN XSTR
1K 5%
A 402 CH 3904DUAL A
4
1 R88BV
2K
5%
Q28BV_PIN6_PIN4
BOM NOTE:
2 CH
402
FOR CORSAIR POWER SUPPLY FIX:
STUFF R80BV, R81BV, R65BV, R82BV, R83BV.
EMPTY R245BV, R263BV, R66BV
6
R83BV
103 96 38 31
SUS_WARNB 1 2 Q28BV_PIN2 2 Q28BV
IN XSTR
10K
402
5%
CH
1
3904DUAL
[PAGE_TITLE= DSW 5V_DUAL]
FOR CORSAIR POWER DELAY USED BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
hc_cdb_mpi.sch_1.31
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE:
D COST REDUCTION DSW.
112 98 96 95 94 89 78 77 44 31 30
V_5P0_A D
IN
GENERAL NOTE:
THIS CIRCUITRY ONLY APPEAR IN SCHEMATIC AND NOT LAYOUT
THIS WILL BE USED IN FUTURE.
C43BV
2.2UF
R96BV 10%
2.1K 16V
1% X5R
603
CH
402
R97BV SLP_SUS_FET 30 95 103

OUT
10K 1%
3 402 EMPTY
104 78 38 32 30 SLP_SUS_N R98BV 5 Q41BV
C IN XSTR C
4.7K 5%
402 EMPTY 3904DUAL
M6BV
MULTI
603 X5R
100 95 94 89 82 81 78 77 67 49 41 30
V_3P3_A
102
IN
B B
C46BV
2.2UF
R105BV 10%
2.1K 16V
1% X5R
603
CH
402
R114BV SLP_SUS_FET2 30 95 103

OUT
10K 1%
402 EMPTY
6
104 78 38 32 30 SLP_SUS_N R107BV 2 Q41BV

IN XSTR
4.7K 5%
402 EMPTY 3904DUAL
M5BV
A A
MULTI
603 X5R
[PAGE_TITLE=DSW CIRCUIT]
hc_cdb_mpi.sch_1.32
INTEL
Tue Apr 17 09:29:50 2012 CONFIDENTIAL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
C C
B B
A A
[PAGE_TITLE=BLANK PAGE]
hc_cdb_mpi.sch_1.33
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
C C
B B
A A
[PAGE_TITLE= CK505 PAGE3 OF 3]

hc_cdb_mpi.sch_1.34
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

U1LPT
LPT_PCH_DT
D REV 1.1 D
82 81 80 79 78 77 74 52 51 49
116
41
115
36 18 V_3P3_STBY\G 1 R39LB 2 P_PME_N AA31 PME#
110 106 104 102 98 95 94 93 92 91 83
IN
10K 5% 44 IN CK_PCH_33M_FB AM22 CLKIN_33MHZLOOPBACK PLTRST# AA37 PLTRST_N
OUT 66 67 77 79 82 103 114
402 EMPTY
GPIO35 / NMI# M40 2X4_POWER_DETECT
IN 89 116
TP_PCH_A2 A2 TP1 GPIO50 AH26 PCIEX1_SLOT5_PRSNT2_N 23 63
TP_PCH_A3 IN
A3 TP2 GPIO51 AU31 PCH_GP51
OUT 52
TP_PCH_B2 B2 TP4 GPIO52 AJ26 PCIEX1_SLOT4_PRSNT2_N 22 63
TP_PCH_B1 IN
B1 TP3 GPIO53 AV31 PCH_GP53
IN 52
TD_IREF C3 TD_IREF GPIO54 AW33 PCIEX1_SLOT6_PRSNT2_N 24 63
IN
DESIGN NOTE: GPIO55 R30 PCH_GP55
BI 52
1 R139LB
TP THE PCH PINS A2 8.2K 63 IN P_INTA_N AU29 PIRQA#
AND A3 ON CRB 1% 63 IN P_INTB_N AU27 PIRQB#
2 CH 63 IN P_INTC_N AW28 PIRQC#
402 63 P_INTD_N AV27 PIRQD#
IN
50 IN TEST_SETUP_MENU AR30 PIRQE# / GPIO2
79 63 IN P_INTF_N AV29 PIRQF# / GPIO3
63 17 IN EXTTS_SNI_DRV0_PCH AV28 PIRQG# / GPIO4
63 17 IN EXTTS_SNI_DRV1_PCH AT27 PIRQH# / GPIO5
C C
. AIO KOZ SYMBOL

PCI 1 OF 10
DESIGN NOTE:
IC
B TO INCLUDE THE MPI TYPE 0 B
DESIGN NOTE:
TOP SIDE PROBE REV 0.5
LPTDTMPI01
J4MPI
KOZ / KOV
1
C46655-001
J1LB EMPTY
ICH6_HSK DESIGN NOTE:
1 NC_1 NC_2 2
ADD BACK SD VER SYMBOL IN CRB.
4 NC_4 NC_3 3 SD VER STILL HAVE THERMAL KOZ
BUT WILL NOT BE USE IN CRB.
EMPTY
NOTE:
NO PHYSICAL PINS
A ON ALLEGRO MODEL A
J3LB J2LB
2P_ANCHOR_CLIP 2P_ANCHOR_CLIP
1 P1 1 P1
2 P2 2 P2
EMPTY EMPTY
A13494-008 A13494-008
[PAGE_TITLE= PCH 1]
hc_cdb_mpi.sch_1.35
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

USB PORT HSW LPT LOCATION OC PROTECTION MODULE NAME REV DATE
0 PORT 0 J19BU-USB2/3 FRONT PANEL OC0B_GP59

1 PORT 1 J19BU-USB2/3 FRONT PANEL OC0B_GP59
U1LPT
2 PORT 2 J10BU-USB2/3 BACK PANEL OC1B_GP40
LPT_PCH_DT
3 PORT 3 J10BU-USB2/3 BACK PANEL OC1B_GP40
D REV 1.1
4 PORT 4 J9BU-USB2/3 FRONT PANEL OC2B_GP41 15 6 IN DMI_MT_IR_0_DN L24 DMI_RXN0 USB2N0 AV10 USB_P0_DN BI 56
15 6 DMI_MT_IR_0_DP K24 DMI_RXP0 USB2P0 AU10 USB_P0_DP 56
D
5 PORT 5 J9BU-USB2/3 FRONT PANEL OC2B_GP41 IN BI
15 6 OUT DMI_IT_MR_0_DN C20 DMI_TXN0 USB2N1 AV11 USB_P1_DN BI 56
6 PORT 6 J22BU-USB2 FRONT PANEL OC3B_GP42 15 6 OUT DMI_IT_MR_0_DP B20 DMI_TXP0 USB2P1 AW11 USB_P1_DP BI 56
15 6 IN DMI_MT_IR_1_DN G24 DMI_RXN1 USB2N2 AN14 USB_P2_DN BI 58
7 PORT 7 J22BU-USB2 FRONT PANEL OC3B_GP42
15 6 IN DMI_MT_IR_1_DP H24 DMI_RXP1 USB2P2 AP14 USB_P2_DP BI 58
8 PORT 8 J12LB-USB2 BACK PANEL OC4B_GP43 15 6 OUT DMI_IT_MR_1_DN D21 DMI_TXN1 USB2N3 AJ16 USB_P3_DN BI 58
DMI
15 6 OUT DMI_IT_MR_1_DP B21 DMI_TXP1 USB2P3 AK16 USB_P3_DP BI 58
9 PORT 9 J12LB-USB2 BACK PANEL OC4B_GP43
15 6 IN DMI_MT_IR_2_DN F26 DMI_RXN2 USB2N4 AU15 USB_P4_DN BI 57
10 PORT 10 J11BU-USB2 BACK PANEL OC5B_GP9 15 6 IN DMI_MT_IR_2_DP G26 DMI_RXP2 USB2P4 AV15 USB_P4_DP BI 57
15 6 OUT DMI_IT_MR_2_DN B22 DMI_TXN2 USB2N5 AU12 USB_P5_DN BI 57
11 PORT 11 J11BU-USB2 BACK PANEL OC5B_GP9
15 6 OUT DMI_IT_MR_2_DP C22 DMI_TXP2 USB2P5 AT12 USB_P5_DP BI 57
12 PORT 12 J8BU-USB2 FRONT PANEL OC6B_GP10 15 6 IN DMI_MT_IR_3_DN K26 DMI_RXN3 USB2N6 AV14 USB_P6_DN BI 55
15 6 IN DMI_MT_IR_3_DP L26 DMI_RXP3 USB2P6 AW14 USB_P6_DP BI 55
13 PORT 13 J8BU-USB2 FRONT PANEL OC6B_GP10
15 6 OUT DMI_IT_MR_3_DN A24 DMI_TXN3 USB2N7 AU17 USB_P7_DN BI 55
15 6 OUT DMI_IT_MR_3_DP B24 DMI_TXP3 USB2P7 AT17 USB_P7_DP BI 55
R9LB USB2N8 AW16 USB_P8_DN BI 60
USB
R199LB 1 2 DMICOMP B19 DMI_RCOMP USB2P8 AV16 USB_P8_DP BI 60
115 114 106 66 51 44 41 40 37 V_1P5_PCH 1 2 7.5K 1% CH 402 PCIECOMP C13 PCIE_RCOMP USB2N9 AN16 USB_P9_DN BI 60
IN
7.5K 1% CH 402 USB2P9 AP16 USB_P9_DP BI 60
44 IN CK_100M_DMI_PCH_DN G22 CLKIN_DMI_N USB2N10 AJ18 USB_P10_DN BI 59
44 IN CK_100M_DMI_PCH_DP F22 CLKIN_DMI_P USB2P10 AK18 USB_P10_DP BI 59
USB2N11 AP18 USB_P11_DN BI 59
C 61 IN USB3_RX3_DN L14 PERN1 / USB3RN3 USB2P11 AN18 USB_P11_DP BI 59 C
61 IN USB3_RX3_DP K14 PERP1 / USB3RP3 USB2N12 AW18 USB_P12_DN BI 54
58 OUT USB3_TX3_DN B12 PETN1 / USB3TN3 USB2P12 AV18 USB_P12_DP BI 54
58 OUT USB3_TX3_DP B11 PETP1 / USB3TP3 USB2N13 AP20 USB_P13_DN BI 66
61 IN USB3_RX4_DN F14 PERN2 / USB3RN4 USB2P13 AN20 USB_P13_DP BI 66
61 IN USB3_RX4_DP G14 PERP2 / USB3RP4 USB_OC0_R_N
58 OUT USB3_TX4_DN D11 PETN2 / USB3TN4 OC0# / GPIO59 AE40
BI 36 116
58 USB3_TX4_DP C11 PETP2 / USB3TP4 OC1# / GPIO40 AF37 USB_OC1_R_N 36 116
OUT USB_OC2_R_N BI
67 IN HSI3_DN F11 PERN3 OC2# / GPIO41 AD39
BI 36 116
67 HSI3_DP H11 PERP3 OC3# / GPIO42 AD40 USB_OC3_R_N 36 116
IN USB_OC4_R_N BI
67 OUT HSO3_DN B9 PETN3 OC4# / GPIO43 AF39
BI 36 116
PCI-E
HSO3_DP USB_OC5_R_N
67 OUT A9 PETP3 OC5# / GPIO9 AC41
BI 36 116
114 HSI4_WLAN_DN J11 PERN4 OC6# / GPIO10 AF40 USB_OC6_R_N 36 116
IN IO_PME_N BI
114 IN HSI4_WLAN_DP L11 PERP4 OC7# / GPIO14 AG40
BI 36 49 116
114 OUT HSO4_WLAN_DN B8 PETN4
114 OUT HSO4_WLAN_DP C8 PETP4 USBRBIAS# AV20
25 IN TPEV_HSI5_DN G9 PERN5 USBRBIAS AU20 USBRBIAS_PCH BI 36
25 IN TPEV_HSI5_DP F9 PERP5
25 OUT TPEV_HSO5_DN B7 PETN5 CLKIN_DOT96_N AP11 CK_96M_DREF_DN BI 44
25 OUT TPEV_HSO5_DP A7 PETP5 CLKIN_DOT96_P AM11 CK_96M_DREF_DP BI 44
25 24 IN HSI6_DN F7 PERN6
25 24 IN HSI6_DP H7 PERP6
25 24 OUT HSO6_DN E1 PETN6
B 25 24 HSO6_DP D2 PETP6 B
OUT
25 23 IN HSI7_DN K6 PERN7
25 23 IN HSI7_DP K8 PERP7
25 23 OUT HSO7_DN G3 PETN7
25 23 OUT HSO7_DP G5 PETP7
25 22 IN HSI8_DN J2 PERN8
25 22 IN HSI8_DP J3 PERP8
25 22 OUT HSO8_DN H2 PETN8
USB_OC_FRONT1_N R12LB
USB_OC6_R_N 25 22 OUT HSO8_DP H1 PETP8
54 1 2 36 116
IN OUT
0 5% R4LB
55 IN USB_OC_FRONT2_N 402 CH
1 2 USB_OC3_R_N
OUT 36 116 2 OF 10
0 5%
R6LB 402 CH
IC
USB_OC_FRONT3_N 1 2 USB_OC0_R_N
56 IN OUT 36 116
0 5%
402 CH R10LB
57 USB_OC_FRONT4_N 1 2 USB_OC2_R_N 36 116
IN OUT
0 5%
402 CH USBRBIAS_PCH 36
OUT
1 R63LB 2
CAD NOTE: 402 22.6 1% CH
A USBRBIAS (R63LB): TIE TRACES TOGETHER CLOSE TO PINS, A

WITH LENGTH NO LONGER THAN 1 INCHE TO RESISTOR
R7LB
60 USB_OC_BACK0_N 1 2 USB_OC4_R_N 36 116
IN OUT
0 5%
R5LB 402 CH
58 IN USB_OC_BACK1_N 1 2 USB_OC1_R_N
OUT 36 116 R510EV
IO_PME_N 1 2 V_3P3_STBY\G
0 5%
116 49 36 OUT IN 18 35 41 49 51 52 74 77 78 79 80 81 82 83
CH 10K 5% 91 92 93 94 95 98 102 104 106 110 115 116
402
USB_OC_BACK2_N R1LB 402 CH
1 2 USB_OC5_R_N
59 IN OUT 36 116
0 5%
402 CH
[PAGE_TITLE=PCH 2] BPAGE DRAWING

hc_cdb_mpi.sch_1.36
Mon Apr 16 13:57:45 2012
INTEL
CONFIDENTIAL
DOCUMENT_NUMBER
<DOCUMENT_NUMBER>
PAGE
36
REV
1.0

2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
MPWROK STUFF R12UB FOR AMT

R12UB VCC3
92 PCH_MEPWROK 1 2
IN
0 5%
D 402 CH PCH_MEPWROK_R OUT 37 R248LB
103 79 77 37 SER_IRQ 1 2 D
OUT
10K
CH
5%
402
R11UB R249LB
PWRGD_3V 1 2 1 2
81 77 38 13 IN 104 77 37 OUT A20GATE
116 103 82
0 5% BOM NOTE: 10K 5%
402 EMPTY 402 CH
CAD NOTE: STUFF R11UB FOR NON AMT

R250LB
OVERLAP PADS ON R11UB, R12UB 100 77 37 KBRST_N 1 2
OUT
10K 5%
402 CH
U1LPT
SATA3COMP_PCH
LPT_PCH_DT OUT 37
114
REV 1.1 SATAHDR_RX0_DN R3LB 51 66
C 114 OUT CLINK_CLK_WLAN U36 CL_CLK SATA_RXN0 B28
IN 53 1 2 V_1P5_PCH 36 40 C
114 CLINK_DATA_WLAN U35 CL_DATA SATA_RXP0 A28 SATAHDR_RX0_DP
53 IN 41 44
OUT SATAHDR_TX0_DN IN CAD NOTE: 7.5K 1% 106
114 OUT CLINK_RST_WLAN_N U34 CL_RST# SATA_TXN0 F31
SATAHDR_TX0_DP OUT 53 402 CH 115
SATA_TXP0 H31
SATAHDR_RX1_DN OUT 53 SATA3COMP_PCH (R3LB): TIE TRACES TOGETHER CLOSE TO PINS,
CLINK
37 PCH_MEPWROK_R AA32 APWROK SATA_RXN1 D30 53
IN SATAHDR_RX1_DP IN WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR
SATA_RXP1 C30
SATAHDR_TX1_DN IN 53
SATA_TXN1 B34
SATAHDR_TX1_DP OUT 53
SATA_TXP1 C34
OUT 53
SATAHDR_RX2_DN
SATA_RXN2 A31
SATAHDR_RX2_DP IN 53
TP_PWM0 AL31 PWM0 SATA_RXP2 B31
TP_PWM1 AM31 PWM1 SATA_TXN2 B35
TP_PWM2 AP31 PWM2 SATA_TXP2 D35
OUT 53
TP_PWM3 AV30 PWM3 FAN SATA_RXN3 B32 SATAHDR_RX3_DN
SATA_RXP3 C32
SATA_TXN3 G33
52 IN PCH_GP17 AP28 TACH0 / GPIO17 SATA_TXP3 F33
OUT 53
52 PCH_GP1 AT31 TACH1 / GPIO1
IN SATAHDR_RX4_DN
52 IN PCH_GP6 AM28 TACH2 / GPIO6 SATA_RXN4 / PERN1 A26
104 49 SMC_RUNTIME_SCI_N AV34 TACH3 / GPIO7 SATA_RXP4 / PERP1 B26 66
IN SATAHDR_TX4_DN IN
49 20 IN PCIEX16_PRSNT2_N AT30 TACH4 / GPIO68 SATA_TXN4 / PETN1 L28
52 IN SV_DETECT AV35 TACH5 / GPIO69 SATA_TXP4 / PETP1 K28
SATAHDR_RX5_DN OUT 66
SATA_RXN5 / PERN2 C27
IN 53
B M128LB SATA_RXP5 / PERP2 B27 SATAHDR_RX5_DP
53 B
1 2 SATAHDR_TX5_DN IN
SATA_TXN5 / PETN2 G28
OUT 53
MULTI SST_CTL_R AJ31 SST SATA_TXP5 / PETP2 F28 SATAHDR_TX5_DP
53
CK_SATA_PCH_DN OUT
402 EMPTY CLKIN_SATA_N H35
CK_SATA_PCH_DP IN 44
50 PCH_CONFIG_JUMPER L38 SCLOCK / GPIO22 CLKIN_SATA_P H36 44
IN IN
50 IN MFG_MODE H41 SLOAD / GPIO38 PCH_SATA_LED_N
50 IN GP39_GFX_CRB_DETECT R31 SDATAOUT0 / GPIO39 SATALED# J39
OUT 49 80
SATA3COMP_PCH
50 IN SV_ADVANCE_GP48 L40 SDATAOUT1 / GPIO48 SATA_RCOMP D33
IN 37
GPIO
SATA0GP
SATA0GP / GPIO21 M37
SATA1GP IN 49 116
CAD NOTE: SATA1GP / GPIO19 J40
PCH_GP36 IN 49 52 116
SATA2GP / GPIO36 H40
OUT 52 116
PUT M128LB AWAY FROM SATA3GP / GPIO37 N41 PCH_GP37
IN 52 116
MPI KOZ FOR PROBING ACCESS SATA4GP / GPIO16 M39 SATA4GP
IN 49 66 116
SATA5GP / GPIO49 N40 PCH_GP49
IN 52 116
L_BKLTCTL
EDP_BKLTCTL AP2
L_BKLTEN OUT 65
EDP_BKLTEN AT2
L_VDDEN OUT 65
EDP_VDDEN AP1
OUT 65
A A
CAD NOTE:
HOST
A20GATE
TP14 N30
KBRST_N IN 37 77 104 PLACE 1 INCH FROM PCH
RCIN# K36
IN 37 77 100
SERIRQ G39 SER_IRQ
PCH_THERMTRIP_N OUT 37 77 79 103
THRMTRIP# C40
PCH_PECI IN 10
PECI G40
H_PM_SYNC_0 IN 10
PMSYNCH F40
PLTRST_CPU_N OUT 10
PLTRST_PROC# F41
OUT 10 82 113
3 OF 10 1
C230LB
IC 47PF
5%
[PAGE_TITLE=PCH 3] DESIGN NOTE:
C230LB EMPTY PAD PLACEHOLDER

2 50V
EMPTY
402 BPAGE DRAWING
hc_cdb_mpi.sch_1.37
INTEL DOCUMENT_NUMBER
<DOCUMENT_NUMBER>
PAGE
37
REV
1.0
2 1
8 7 6 5 4 3 2 1
R161BV
MODULE REV DETAILS
96 38 31 IN SUS_WARNB 1 2 SUS_PWR_ACK OUT 31 38 96 104 MODULE NAME REV DATE
103
VCC3 VCC3 0 5%
402 EMPTY
1 R195BV BOM NOTE:
CAD NOTE: 1K
1 5% EMPTY R161BV FOR USB WAKE S4/S5
PLACE AT PCH 1 2 EMPTY DESIGN NOTE:
R270LB 402 DESIGN NOTE: VCC3
DESIGN NOTE: 10K R15LB GPIO_PCIE_RESET DEFAULT LOW. ACTIVE HIGH
D 5% 10K STUFF R161BV FOR NON-DEEP SX THE SAME GPIO CANNOT BE USED IF THE HDA INTERFACE IS 1.5V
DO NOT STUFF CIRCUIT. INTERNAL PULL-UP EXIST IN PCH. EMPTY
5% D
402 EMPTY 1 R22LB
2 402 10K
2 U1LPT 5%
LPT_PCH_DT 2 EMPTY
402
LPC_L_DRQ1_N
I270 REV 1.1
77 IN L_DRQ1_N AK26 LDRQ1# / GPIO23 BMBUSY# / GPIO0 G38 FP_AUD_DETECT 49 74
0 PCH_GP32 IN
AN24 LAD0 GPIO32 N32
1 AP26 LAD1 DOCKEN# / GPIO33 AV26 PCH_GP33 49
L_AD<3..0> 2 PCH_GP34 IN
103 77 IN AJ24 LAD2 GPIO34 N34
IN 52
3 AN26 LAD3
CAD NOTE: 77 L_DRQ_N AK22 LDRQ0# GPIO8 AC40 IGC_EN_N 52 116
103 IN L_FRAME_N
R144LB
L_FRAME_N_R LAN_DISABLE_N IN
PLACE 0 OHM SERIES STRAPS CLOSE TO PCH
77 OUT 1 2 AP24 LFRAME# LAN_PHY_PWR_CTRL / GPIO12 AL40
OUT 67
402 0 5% CH HDA_DOCK_RST# / GPIO13 AN22 GPIO_PCIE_RESET 82
R158LB AUD_LINK_BCLK_R LED_DRIVE_GP15
OUT
38
SPI_MOSI 1 2 SPI_MOSI_PRI_SEC_FLSH 83 84
38 OUT AV23 HDA_BCLK GPIO15 AC32
OUT 52 80
IN OUT 38 OUT
AUD_LINK_RST_R_N AU24 HDA_RST# GPIO24 AE34 H_SKTOCC_N
IN 10 77 1 R281LB
0 5% 74 AUD_LINK_SDI0 AT26 HDA_SDI0 GPIO28 V41 PCH_GP28 49 10K
402 CH IN SLP_WLAN_N OUT 5%
R159LB 74 IN
AUD_LINK_SDI1_R AV22 HDA_SDI1 SLP_WLAN# / GPIO29 AL39
OUT 49 115
2 EMPTY
SPI_CLK 70 AUD_LINK_SDI2_R AT22 HDA_SDI2 PCIECLKRQ0# / GPIO73 W34 GP73_PD 38
38 IN 1 2 SPI_CLK_PRI_SEC_FLSH
OUT 83 84 IN AUD_LINK_SDI3_R PCH_GP18 OUT 402
74 IN AW23 HDA_SDI3 PCIECLKRQ1# / GPIO18 P39
OUT 38 116
0 5% 38 AUD_LINK_SDO_R AU22 HDA_SDO PCIECLKRQ2# / GPIO20 / SMI# P37 PCH_SMI_N 49 116
402 CH OUT AUD_LINK_SYNC_R GP25_PD OUT
R201LB
38 OUT AV24 HDA_SYNC PCIECLKRQ3# / GPIO25 AA39
OUT 38
SPI_CS0_N PCIECLKRQ4# / GPIO26 W35 GP26_PD 38
C 38 IN 1 2 SPI_CS0_ISOLATE_N
OUT 83 84 SPI_MOSI PCH_GP44 OUT C
38 OUT P40 SPI_MOSI / IO0 PCIECLKRQ5# / GPIO44 AA36
OUT 49 52
0 5% 84 83 SPI_MISO R36 SPI_MISO / IO1 PCIECLKRQ6# / GPIO45 W32 PCH_GP45 49 91
402 CH IN SPI_CS0_N PCH_GP46 OUT
38 OUT R38 SPI_CS0# PCIECLKRQ7# / GPIO46 AA40
OUT 52 91
38 SPI_CLK U39 SPI_CLK
R202LB DESIGN NOTE: OUT SPI_CS1_N NFC_GP57
SPI_CS1_N 1 2 SPI_CS1_ISOLATE_N 38 OUT R35 SPI_CS1# GPIO57 AC36
IN 18 49
38 IN OUT 83 84 SPI_CS2_N PCH_SYSPWROK
R144LB DIRECT 79 OUT R40 SPI_CS2# SYS_PWROK W31
IN 81 82 100 113
0 5% CONNECT AT CRB 79 SPI_IO2 U40 SPI_IO2 RI# AE36 PCH_RI_PU 49
402 CH BI SPI_IO3 WAKE_N IN
79 BI U37 SPI_IO3 WAKE# AK34
IN 20 22 23 24 25 49 66 114
DESIGN NOTE: SLP_A# AN37 PCH_SLP_M_N 77 92 94 103 115
SLP_LAN_N OUT
SLP_LAN# AU36
OUT 94 103
66MHZ SPI TOPOLOGY, 15OHM SERIES R NOT REQUIRED, 0-OHM PLACEHOLDERS FOR DEFENSIVE DESIGN.
TP21 AC35 TP_SLP_S0_N
DESIGN NOTE:
SLP_S3# AK40 SLP_S3_PCH_N 49
CAD NOTE: SLP_S4_N OUT NFC_GP57 TO BE USE IN AIO FOR NFC
50 PCH_RTCX1 AN40 RTCX1 SLP_S4# AT35
OUT 77 90 104
PLACE 0 OHM SERIES RESISTOR CLOSE TO PCH IN PCH_RTCX2 SLP_S5# / GPIO63 AA35 TP_SLP_S5_N
50 OUT AN39 RTCX2 SUS_STAT# / GPIO61 AD37 LPCPD_N 103
77
114 81 R64LB SMB_CLK_RESUME_R 50 49 PCH_RTCRST_PULLUP AR38 RTCRST# OUT DESIGN NOTE:
23 22 20 SMB_CLK_RESUME 1 2 38 IN PCH_SRTCRSTB_PULLUP SUSCLK / GPIO62 W36 SUSCLK
OUT 52
BI BI 50 49 IN AR39 SRTCRST# AJ40 PCH_GP72
66 25 24 C4LB 0 5% 50 PCH_INTRUDER_HDR_N AR41 INTRUDER# GPIO72 OUT 104 49 DRAMPWRGD TO BE CHANGED RES VALUE FOR HSW A0/LPT A0
2 1 402 CH IN PWRGD_3V SUSACK# AJ37 SUS_PWR_ACK
IN 31 38 90
116 103 82 81 77 37 13 IN AT40 PWROK SUSWARN# / SUSPWRNACK / GPIO30 AG41 PCH_SUS_WARNB 38 96 28
1.00UF 20% 116 103 78 30 IN
PCH_RSMRST_N AM40 RSMRST# OUT R308LB 26
6.3V 402 PCH_INTVRMEN AV36 INTVRMEN DRAMPWROK AE38 H_DRAMPWRGD
1 2 V_SM 11
EMPTY R65LB
52 IN GPIO27 AU34 LANWAKE_N 67 IN
66 25 SMB_DATA_RESUME 78 IN
PCH_DPWROK AV38 DPWROK PCH_GP31 IN 1.8K 5% 16
22 20 BI 1 2 SMB_DATA_RESUME_R BI 38 DSWODVREN ACPRESENT / GPIO31 AM36
OUT 49 402 27
B 24 23 52 IN AM41 DSWVRMEN SLP_SUS# AK38 SLP_SUS_N 30
32
38
78
104
CH 29 B
114 81 2
C5LB
1
0 5%
DESIGN NOTE: SW_ON_N OUT 113
10 80 90
91
402 CH PWRBTN# AK41
IN 50 64 OUT 93
100 111
C4LB & C5LB 0402 PLACEHOLDER 64 49 PCH_PORT80_LED AG31 SMBALERT# / GPIO11 SYS_RESET# N36 FP_RST_N 116
49
50
64
10
113
104
1.00UF 20% OUT OUT
6.3V 402 CAP FOR RC TUNE. DEFAULT EMPTY 38 SMB_CLK_RESUME_R AG36 SMBCLK SPKR R32 SPKR 38 50
EMPTY OUT SMB_DATA_RESUME_R OUT 70 1 R23LB BOM NOTE:
38 BI AG32 SMBDATA 3.3K
91 49 PCH_GP60 AG35 SML0ALERT# / GPIO60 PROCPWRGD D40 H_PWRGD 10 110 113 5%
VCC3 OUT SMLINK0_CLK OUT HSW A0: CHANGE R23LB TO
67 49 18 OUT AE32 SML0CLK 2 CH 4.7KOHM AND R308LB TO 3.3KOHM
67 49 18 BI
SMLINK0_DATA AE35 SML0DATA 402 BOM NOTE:
49 18 PCH_GP74_PU AJ39 SML1ALERT# / PCHHOT# / GPIO74
1 OUT SML1CLK_PCH DEFAULT:SPECIFIC FOR HSW X0 + LPT A0
104 49 OUT AK36 SML1CLK / GPIO58
R17LB 104 49 SML1DATA_PCH AK33 SML1DATA / GPIO75
BOM NOTE: BI
1K
5% STUFF TO ENABLE NO-REBOOT OPTION AT
JTAG(SUS)
POWER-UP (CONFIGURATION STRAPPING). TP20 W37 PCH_JTAG_RST_R
OUT 116
EMPTY JTAG_TCK Y40 PCH_JTAG_TCK_FILTER
116
402 OUT R501LB
2 JTAG_TDI W39 PCH_JTAG_TDI
IN 116
JTAG_TDO Y38 PCH_JTAG_TDO
116
1 2
OUT
4 OF 10 JTAG_TMS W40 PCH_JTAG_TMS
OUT 116 10K 5%
70 R13LB VCC 402 EMPTY
38 IN SPKR 1 2 DBG_SPKR OUT 38
50 0 5% R136LB IC
BOM NOTE: 402 CH 38 PCH_SUS_WARNB 1 2 SUS_WARNB 31 38 96 103
IN OUT
STUFF R13LB FOR CRB 0 5%
3 Q1LB 402 CH
AUD_LINK_BCLK_R
R104LB
A 38 DBG_SPKR 1 R18LB 2 CORE_SPKR_R
1 R137LB 38 IN 1 2 AUD_LINK_BCLK_R104LB OUT 49 74 A
IN MMBT3904 LS1LB 104 78 38 32 30 IN
SLP_SUS_N 1 2 15 5%
1K 5% XSTR XDCR 402 CH
402 CH 1 C65LB 2 402
0 5%
EMPTY
116 38 PCH_GP18
1000PF
10%
SPKR_OUT 1 + R132LB
CAD NOTE:
IN 50V AUD_LINK_SYNC_R AUD_LINK_SYNC_R132LB
38 IN
GP25_PD 2 EMPTY 2 AT-08 38 IN 1 2
OUT 49 74
PLACE R104LB NEAR TO PCH WITHIN 500MILS
38 IN
GP26_PD 603 1 IN 15 5%
38 GP73_PD "X7R" 402 CH 38 AUD_LINK_SDO_R 1 R122LB 2 AUD_LINK_SDO_R122LB 49 52 74
IN R16LB IN OUT
47 CAD NOTE: 15 5%
1 R32LB 1 R40LB 1 R58LB 1 R19LB 5% 402 CH
PLACE R132LB NEAR TO PCH WITHIN 2500MILS
10K 10K 10K 10K EMPTY CAD NOTE:
5% 5% 5% 5%
2 402
38 AUD_LINK_RST_R_N 1 R133LB 2 AUD_LINK_RST_R133LB_N
49 74
2 CH 2 CH 2 CH 2 CH IN OUT PLACE R122LB WITHIN 2500MILS FROM PCH
402 402 402 402 15 5%

CAD NOTE: 402 CH
[PAGE_TITLE=PCH 4]
PLACE R133LB WITHIN 2500MILS FROM PCH
hc_cdb_mpi.sch_1.38
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D U1LPT
LPT_PCH_DT D
REV 1.1
AT1 VSS TP19 U11 TP_PCH_U11
AT41 VSS TP18 U10 TP_PCH_U10
AU1 VSS TP23 AJ14 TP_PCH_AJ14
AV1 VSS TP24 AK14 TP_PCH_AK14
AV2 VSS TP9 K34 TP_PCH_K34
AV40 VSS TP8 K33 TP_PCH_K33
AV41 VSS TP22 AH24 TP_PCH_AH24
AW2 VSS
AW40 VSS TP11 L16 TP_PCH_L16
B40 VSS TP6 K16 TP_PCH_K16
B41 VSS TP25 AM34
C41 VSS
D1 VSS
D41 VSS
TP17 R12 TP_PCH_R12
TP13 N12 TP_PCH_N12
TP12 L22 TP_PCH_L22
TP7 K22 TP_PCH_K22
C C
TP16 R4 NC_PCH_R4
TP5 K5 NC_PCH_K5
TP15 P5 NC_PCH_P5
TP10 L5 NC_PCH_L5
VSS AC31
VSS AF3
VSS AV21
10 OF 10
IC
B B
A A
[PAGE_TITLE=PCH 5]
hc_cdb_mpi.sch_1.39
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

116 M20UB R39UB

106 104 103 V_1P05_PCH 1 2 V_1P05_XCK_DCB_R V_1P05_XCK_DCB_FB_R
51 44 41 11 10 1 2 41
98 93 92
IN MULTI OUT
113 112 107 0 5%
CH 805 402 CH
1
1
A93552-002 C30UB C17UB
D 10UF
20%
1UF
6.3V
10%
6.3V D
BOM NOTE: 2 EMPTY 2 X5R
603 402
DEFAULT (M20UB): 10 UH (721891-026)
OPTION: MULTI SITE TO USE 0 OHM (A93552-002)
C C
U1LPT
LPT_PCH_DT
REV 1.1
USB3 FDILINK
56 IN USB3_RX1_DN F20 USB3RN1 FDI_RXN0 N1 FDI_TX0_DN IN 7
56 IN USB3_RX1_DP G20 USB3RP1 FDI_RXP0 N2 FDI_TX0_DP IN 7
56 OUT USB3_TX1_DN B18 USB3TN1 FDI_RXN1 P2 FDI_TX1_DN IN 7
56 OUT USB3_TX1_DP C18 USB3TP1 FDI_RXP1 P3 FDI_TX1_DP IN 7
56 IN USB3_RX2_DN G18 USB3RN2 FDI_CSYNC L2 FDI_CSYNC OUT 7

56 IN USB3_RX2_DP H18 USB3RP2
56 OUT USB3_TX2_DN B15 USB3TN2 FDI_INT L3 FDI_INT OUT 7
56 OUT USB3_TX2_DP B16 USB3TP2
B FDI_RCOMP K2 B
57 USB3_RX5_DN K20 USB3RN5 114
IN 66
57 IN USB3_RX5_DP L20 USB3RP5 44
57 USB3_TX5_DN D15 USB3TN5 R195LB 40
OUT USB3_TX5_DP FDI_RCOMP 1 2 V_1P5_PCH
IN 36
57 OUT C15 USB3TP5 37
7.5K 1% 41
USB3_RX6_DN 402 CH 51
57 IN L18 USB3RN6 106
BOM NOTE: 57 IN USB3_RX6_DP K18 USB3RP6 115
57 OUT USB3_TX6_DN B14 USB3TN6
STUFF M19UB AND REMOVE M1UB FOR 57 OUT USB3_TX6_DP A14 USB3TP6
NON-IGD MODE
V_1P5_PCH
115 114 106 66 51 44 41 40 37 36 IN M19UB PCH_GP70_PU
1 2
49 IN AK28 TACH6 / GPIO70
MULTI 49 IN PCH_GP71_PU AT34 TACH7 / GPIO71
BOM NOTE: 6 OF 10
693286-015 FB
DEFAULT:M22UB 1 OHM 0402 5% (IPN:A93549-043)
OPTION: M22UB 600 OHM FB (A51464-006) IC
VCC3
M22UB
A93549-043
DESIGN NOTE: V_1P5_DAC_FB 1 2 V_1P5_DAC_FB_R 41
M1UB OUT
VCC3
MULTI
1 DEFAULT: DAC POWER SUPPLY 1 2
MULTI CH 402
R16UB
A 1K 693286-015 EMPTY A
5% BOM NOTE: M32UB CAD NOTE:
U1UB
CH RT9179 1 2 PLACE NEAR PCH
2
402
1 IN OUT 5
V_RT9179_DAC_FB
M1UB STUFFED WITH FERRITE BEAD MULTI A36096-045
V_RT9179_EN_P3 3 X7R VCC3 VCC3
2
EN
4 1 R18UB 402
GND ADJ U1UB_PIN4
27.4K 2
1 2 1% C2UB BOM NOTE:
C3UB C1UB 4.7UF
1UF IC 2 CH 20% 1 C62UB
.1UF 20% 402 6.3V M32UB STUFFED WITH 0.01UF CAP
10% 6.3V 1 BOM NOTE: 1
2 16V 1 X5R
X5R
805
0.1UF
20%
C35UB
EMPTY 603 1 R19UB CHANGE R18UB TO 27.4KOHM (IPN: A36092-265) 16V
4.7UF
603 100K 2 Y5V
20%
2
1%
CH
402 2
10V
Y5V
805
[PAGE_TITLE=PCH 7]
402 DESIGN NOTE:
BOBCAT CPT VCCA_DAC USE 3.3V ON INTERPOSER

INTERPOSER LPT VCCADAC PIN IS NC. BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
hc_cdb_mpi.sch_1.40
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
U1LPT
LPT_PCH_DT DESIGN NOTE: DEFENSIVE DESIGN FOR MODPHY BANDGAP REFERENCE
MODULE REV DETAILS
REV 1.1
AA19 VCC DMI_IREF A19 V_1P5_PCH IN 36 37 40 41 44 51 66 106
AA20 VCC FDI_IREF N11 C135LB 114 115
AB16 VCC ICLK_IREF N10 1 2
AB17 VCC PCIE_IREF B13
103 98 93 92 51 44 41 40 11 10 IN
V_1P05_PCH AB19 VCC SATA_IREF A33 .1UF 10%
10V
116 113 112 107 106 104 EMPTY
D AB20 VCC 402
AD16 VCC VCCVRM B37 D
V17 VCC VCCVRM A38
V19 VCC VCCVRM K1 R273LB 106 114 115
V20 VCC VCCVRM B39 1 2 V_1P5_PCH 36 37 40 41
IN 44 51 66
V22 VCC VCCVRM A39 0 5%
V23 VCC VCCVRM A40 402 CH
V25 VCC VCCVRM T14
W17 VCC VCCVRM C2
W19 VCC VCCVRM C1
114 115 R103LB
W23 VCC VCCVRM B4 V_1P5_PCH 36 37 40 41 44 106 114 115
IN 51 66 106 1 2 V_1P5_PCH
IN 36 37 40 41
W25 VCC VCCVRM A4 44 51 66
VCCADAC1_5 AF2 V_1P5_DAC_FB_R 40
0 5%
IN 402 CH
AC12 VCCIO
VCCADACBG3_3 AE1
40 V_1P05_XCK_DCB_FB_R AB1 VCC VCC3_3 B6
IN V_3P3_BG
U12 VCCCLK VCC3_3 AW21
IN 51 115 R272LB 106 114 115
V14 VCCCLK 1 2 V_1P5_PCH 36 37 40 41
IN 44 51 66
W14 VCCCLK VCCCLK3_3 AM7 0 5%
AB2 VCCCLK VCCCLK3_3 AM9 402 CH
AA16 VCCCLK VCCCLK3_3 AP5
W16 VCCCLK VCCCLK3_3 AP7 VCC3
VCCCLK VCCCLK3_3 R118CV 66 106 114
116 V_1P05_PCH T16 AR4
1 2 V_1P5_PCH
IN 36 37 40
C 98 93 92 51 44 41 40 11 10 IN V16 VCCCLK VCCCLK3_3 AT5 41 44 51 C
113 112 107 106 104 103 VCCCLK3_3 AV4 0 5% C46LB2 115
P14 VCCIO VCCCLK3_3 AW4
402 CH 1
P16 VCCIO VCCCLK3_3 AW9 .1UF 10%
P17 VCCIO VCCCLK3_3 AG12 10V
P22 VCCIO VCCCLK3_3 AK11 VCC3 X5R
402
P23 VCCIO VCCCLK3_3 AV3
P25 VCCIO VCCCLK3_3 AW3
P26 VCCIO
P28 VCCIO VCC3_3 U30
R274LB 115
T19 VCCIO VCC3_3 W30 1 2 V_1P5_PCH 36 37 40 41 44
T20 VCCIO IN 51 66 106 114
0 5%
AF19 VCCIO VCC3_3 AF26
402 CH
AF20 VCCIO
AF22 VCCIO VCC3_3 AG1
AF23 VCCIO
AP22 VCCUSBPLL VCCSPI R41 V_3P3_EPW 18 51 83 92 94
IN
M14 VCCIO 110 115 116
VCCSUSHDA AW26 V_3P3_STBY\G 18 35 36 49 51 52 74 77 78 79 80 81
V_1P05_ME IN 82 83 91 92 93 94 95 98 102 104 106
112 92 51 IN AA23 VCCASW 1
AA25 VCCASW VCCSUS3_3 AM33 1
C950LB C10LB
AA26 VCCASW VCCSUS3_3 AN33 .1UF
.1UF 10%
AB22 VCCASW 10% 16V
B AB23 VCCASW VCCSUS3_3 AH18 16V 2 X7R B
2 X7R 402
AB25 VCCASW VCCSUS3_3 AH20 402
AB26 VCCASW VCCSUS3_3 AH22
AD17 VCCASW VCCSUS3_3 AJ20
AD19 VCCASW VCCSUS3_3 AK20 DESIGN NOTE:
AD20 VCCASW VCCSUS3_3 P20
R23PI AND R22PI ARE PLACEHOLDER FOR PI ONLY
AD22 VCCASW VCCSUS3_3 AP35
AD23 VCCASW
W26 VCCASW VCCDSW3_3 AV39 V_3P3_A 30 32 49 67 77 78 81 82 89 94
IN 95 100 102
AD25 VCCASW VCCDSW3_3 AW38
AF25 VCCASW VCCDSW3_3 AW39
1
VCCRTC AP33 V_3P0_BAT_VREG
IN 50 51 52 79 89 103 C7LB
.1UF
10%
V_PROC_IO C39 V_CPU_VCCIO2PCH 11 51 16V
IN 2 X7R
R76LB C13LB 402
DCPSUSBYP AU40 V_1P05_DSW_INT_R 1 2 V_1P05_DSW_INT 1 2
DCPSUSBYP AU41 5.11 1% 1UF 10%
402 CH 6.3V X5R
402
DCPSUS2 AJ22 TP_V_1P05_USBSUS_INT
C758LB
DCPRTC AW35 V_1P5_RTC_INT 1 2 CAD NOTE:
C755LB .1UF 10% PLACE DCPL CAPS NEAR PCH
DCPSST AH28 V_1P5_STBY_INT 1 2
16V
X7R
A DCPSUS1 AE30 TP_PCH_AE30 .1UF 10%
16V
402 A
X7R
DCPSUS3 P19 TP_PCH_P19 402
8 OF 10
MATERIAL=IC
BPAGE DRAWING
[PAGE_TITLE=PCH 9]
hc_cdb_mpi.sch_1.41
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D U1LPT
D
LPT_PCH_DT
D9 VSS REV 1.1 VSS A12 U4 VSS VSS AN28
E12 VSS VSS A16 U8 VSS VSS AP4
E3 VSS VSS A21 V26 VSS VSS AP9
E31 VSS VSS A35 V28 VSS VSS AR11
E35 VSS VSS AA10 V38 VSS VSS AR35
E38 VSS VSS AA11 V40 VSS VSS AR37
E4 VSS VSS AA12 W12 VSS VSS AT11
F18 VSS VSS AA22 W28 VSS VSS AT15
F38 VSS VSS AA5 Y1 VSS VSS AT21
G2 VSS VSS AA8 Y41 VSS VSS AT23
H14 VSS VSS AB14 D12 VSS VSS AT24
H22 VSS VSS AC30 D16 VSS VSS AT33
C H28 VSS VSS AC38 D19 VSS VSS AT38 C
H38 VSS VSS AD14 D24 VSS VSS AU3
H4 VSS VSS AD26 D25 VSS VSS AU39
H6 VSS VSS AD28 D26 VSS VSS AV12
H8 VSS VSS AE12 D27 VSS VSS AV17
H9 VSS VSS AE31 D28 VSS VSS AV33
J31 VSS VSS AE4 D31 VSS VSS AW30
J37 VSS VSS AE41 D32 VSS VSS AW7
J5 VSS VSS AE8 VSS B25
K31 VSS VSS AF14 VSS B3
L37 VSS VSS AF28 VSS B38
L41 VSS VSS AG2 VSS C25
M16 VSS VSS AG30 VSS C37
M18 VSS VSS AG34 VSS C6
M20 VSS VSS AG38 VSS D34
M22 VSS VSS AG8 VSS D37
M24 VSS VSS AH14 VSS D4
M26 VSS VSS AH16 VSS D6
B
M28 VSS VSS AJ1 VSS D7
B
N31 VSS VSS AJ28 VSS D8
N35 VSS VSS AK24
N38 VSS VSS AK37
N4 VSS VSS AK9
N8 VSS VSS AL11
R1 VSS VSS AL37
R10 VSS VSS AL5
R34 VSS VSS AM14
R8 VSS VSS AM16
T17 VSS VSS AM18
T22 VSS VSS AM20
T23 VSS VSS AM24
T25 VSS VSS AM26
T26 VSS VSS AM35
T28 VSS VSS AM38
U1 VSS VSS AM4
U31 VSS VSS AM6
U32 VSS VSS AM8
9 OF 10
IC
A A
[PAGE_TITLE=PCH 10]
hc_cdb_mpi.sch_1.42
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

VCC3
DESIGN NOTE:
NOTE: HPD[2:0] ARE 3.3V TOLERANT
D U1LPT PORT D DETECTION STRAP: 1 R50UB 1 R480EV
LPT_PCH_DT DDPD_CTRL_DATA 2.2K 2.2K D
5% 5%
REV 1.1 2 CH 2 EMPTY
402 402
DDSP_1_HPD0 43 DDPD_CTRL_DATA
48 IN AJ2 DDPB_HPD VGA_HSYNC AH3 VGA_HSYNC
OUT 43 OUT
46 DDSP_2_HPD1 AH5 DDPC_HPD VGA_VSYNC AH2 VGA_VSYNC 43
IN DDSP_3_HPD2 OUT
65 IN AJ4 DDPD_HPD 43 DDPD_CTRL_CLK
VGA_RED AC2 VGA_RED
OUT 19 43 OUT
48 DDSP_1_AUX_DN AK6 DDPB_AUXN VGA_GREEN AE2 VGA_GREEN 19 43
BI DDSP_1_AUX_DP VGA_BLUE
OUT
48 BI AK8 DDPB_AUXP VGA_BLUE AC3
OUT 19 43
TP_DDSP_2_AUX_DN AG7 DDPC_AUXN
TP_DDSP_2_AUX_DP DESIGN NOTE:
AG6 DDPC_AUXP VGA_IRTN AG4
65 DDSP_3_AUX_DN AG11 DDPD_AUXN VGA_DDC_DATA AL3 VGA_PCH_DDCSDA 43
BI DDSP_3_AUX_DP VGA_PCH_DDCSCL
BI DEFENSIVE DESIGN: PU OF DDPD_CTRL_CLK
65 BI AG10 DDPD_AUXP VGA_DDC_CLK AL2
BI 43
DAC_IREF AF5 VGA_DACREFSET 43
OUT
DDPC_CTRLCLK AN3 DDPC_CTRL_CLK
BI 46
DDPC_CTRLDATA AM2 DDPC_CTRL_DATA
BI 46
DDPB_CTRLCLK AM1 DDPB_CTRL_CLK
BI 48
DDPB_CTRLDATA AJ5 DDPB_CTRL_DATA
BI 48
DDPD_CTRLCLK AN4 DDPD_CTRL_CLK
BI 43
DDPD_CTRLDATA AN2 DDPD_CTRL_DATA
BI 43
VCC3
C C
Q3LB
1 FET
5 OF 10
IC 43 IN VGA_PCH_DDCSDA 2 3 VGA_DDCSDA_5V OUT 19
1 C6UB
470PF
VCC3 10%
2 50V
EMPTY
603
Q2LB
1 FET
43 IN VGA_PCH_DDCSCL 2 3 VGA_DDCSCL_5V OUT 19
1
C7UB
470PF
10%
50V
2 EMPTY
B 603
B
DACREFSET & RGB PCH-SIDE TERMINATION

VGA_DACREFSET CAD NOTE:
43 OUT
PLACE DACREFSET RES (R44UB) CLOSE VCC3 VCC3
43 19
VGA_RED TO PCH: <500 MILS TO PCH BALL
IN
43 19
VGA_GREEN CAD NOTE: HSYNC/VSYNC SLEW RATE & EMI CONTROL DDC PCH SIDE 1
IN 1
VGA_BLUE TERMINATION R42UB
43 19 IN HSYNC/VSYNC; LOCATE SERIES RESISTOR STRAPS (R52UB, R51UB) WITHIN 750 MILS OF PCH 2.2K R43UB
5% 2.2K
5%
1 R45EV 1 R48EV 1 R60EV 1 R44UB CH
CH
CAD NOTE: 150 150 150 649 BOM NOTE: 402
1% 1% 1%
2 402
1% 2
PLACE VGA RGB RESISTORS CLOSE
2 CH 2 CH 2 CH 2 CH UN-STUFF SERIES RES (R52UB, R51UB) FOR NON-GRAPHICS SKUS VGA_PCH_DDCSDA
TO PCH: <250 MILS TO PCH BALLS
402 402 402 402 R52UB 43 IN
BOM NOTE: VGA_VSYNC 1 2 VGA_VSYNC_3V
BOM NOTE: 43 IN OUT 19
VGA RGB RESISTORS (R54UB-R56UB): REPLACE 150 OHM WITH 33 5% 43 IN VGA_PCH_DDCSCL
DACREFSET RESISTOR (R44UB): MAINTAIN 649OHM FOR BOTH CPT AND LPT
0 OHM (A93549-001) FOR NON-GRAPHICS SKUS 402 CH
WITH 0 OHM FOR NON-GRAPHICS SKUS
R51UB
VGA_HSYNC 2 VGA_HSYNC_3V
A 43 IN 1
OUT 19 CAD NOTE: A
33 5% M25UB M26UB
402 CH 1 2 1 2 DDC_DATA/DDC_CLK; LOCATE PULL-UPS
MULTI MULTI ANYWHERE ON ROUTE OF TRACE
402 EMPTY 402 EMPTY
BOM NOTE:
BOM NOTE:
STUFF 0 OHM RES (M25UB, M26UB) FOR NON-GRAPHICS SKUS
STUFF R42UB, R43UB FOR
DESIGN NOTE:
GRAPHICS/NON-GRAPHICS SKUS
MULTI-SITES TO BE USED FOR SLEW RATE/EMI CAPS ON GRAPHIC SKUS
BPAGE DRAWING
[PAGE_TITLE=PCH 6]
hc_cdb_mpi.sch_1.43
2 1
8 7 6 5 4 3 2 1
U1LPT
MODULE REV DETAILS
LPT_PCH_DT
REV 1.1 CLKIN_GND_N G16 CK_100M_CPHY_PCH_IN_DN 44
IN
CLKIN_GND_P F16 CK_100M_CPHY_PCH_IN_DP
IN 44
D CLKOUT_DMI_N R2 CK_PE_100M_MCP_DN
OUT 10
TP_PCH_AV5 AV5 CLKOUT_33MHZ0 CLKOUT_DMI_P T2 CK_PE_100M_MCP_DP 10
OUT D
R148CK
77 OUT CK_P_33M_PCI1 AV7 CLKOUT_33MHZ1 CLKOUT_DP_N T3 CK_DP_DN OUT 7 44 CK_P_33M_PCI2 1 2 CK_PCH_33M_FB 35
CLKOUT_DP_P T5 CK_DP_DP 7
IN OUT
OUT 22 5%
44 OUT CK_P_33M_PCI2 AU2 CLKOUT_33MHZ2 402 CH
CLKOUT_DPNS_N W2 CK_DPNS_DN OUT 10
TP_PCH_AN9 AN9 CLKOUT_33MHZ3 CLKOUT_DPNS_P U2 CK_DPNS_DP OUT 10 R12CK
44 IN CK_P_33M_PCI4 1 2 CK_P_33M_EC
OUT 103
44 CK_P_33M_PCI4 AU5 CLKOUT_33MHZ4 CLKOUT_ITPXDP_N U6 CK_XDP_BCLK_DN 113 22 5%
OUT OUT CH
CLKOUT_ITPXDP_P U7 CK_XDP_BCLK_DP OUT 113 402
TP_PCH_AV8 CLKOUT_PEG_A_N AA3 CK_PE_100M_16PORT_DN

OUT 20
AV8 CLKOUTFLEX0 / GPIO64 CLKOUT_PEG_A_P AA2 CK_PE_100M_16PORT_DP
OUT 20
44 OUT CK_PCH_14M_PA AT9 CLKOUTFLEX1 / GPIO65
TP_PCH_AV9 AV9 CLKOUTFLEX2 / GPIO66 CLKOUT_PEG_B_N AE6 CK_TPEV_CK_PEGB_DN
TP_PCH_AU8 AU8 CLKOUTFLEX3 / GPIO67 CLKOUT_PEG_B_P AE7 CK_TPEV_CK_PEGB_DP
CLKOUT_PCIE_N0 AE10 CK_1PORT_S7_DN OUT 23

44 IN XCLK_RBIAS R11 DIFFCLK_BIASREF CLKOUT_PCIE_P0 AE11 CK_1PORT_S7_DP OUT 23
44 IN CK_14M_PCH AR7 REFCLK14IN CLKOUT_PCIE_N1 AC6 CK_WLAN_100M_DN OUT 114

CLKOUT_PCIE_P1 AC7 CK_WLAN_100M_DP OUT 114
C CLKOUT_PCIE_N2 AC11 CK_GLAN_DN OUT 67 C

CLKOUT_PCIE_P2 AC10 CK_GLAN_DP OUT 67
CLKOUT_PCIE_N3 W11 CK_MSATA_100M_DN

OUT 66
CLKOUT_PCIE_P3 W10 CK_MSATA_100M_DP
OUT 66
CLKOUT_PCIE_N4 Y4 TP_PCH_Y4
TP_PCH_Y2 R117LB
CLKOUT_PCIE_P4 Y2
CK_PCH_14M_PA CK_PCH_14M_LPC
44 1 2 77
IN OUT
CLKOUT_PCIE_N5 W7 CK_PCIE_X4_DN
OUT 25 22 5%
CLKOUT_PCIE_P5 W6 CK_PCIE_X4_DP 25 402 CH
OUT
CLKOUT_PCIE_N6 AA7 CK_1PORT_S6_DN OUT 22
CLKOUT_PCIE_P6 AA6 CK_1PORT_S6_DP OUT 22
44 IN XTAL_25M_PCH_IN N7 XTAL25_IN
CLKOUT_PCIE_N7 R6 CK_1PORT_S5_DN OUT 24
44 OUT XTAL_25M_PCH_OUT N6 XTAL25_OUT CLKOUT_PCIE_P7 R7 CK_1PORT_S5_DP OUT 24
7 OF 10 V_1P5_PCH
R27CK
115 114 106 66 51 41 40 37 36 IN 1 2 XCLK_RBIAS OUT 44
IC 7.5K 1%
402 CH
B DESIGN NOTE:
B
ALWAYS STUFF CK_100M_DMI_PCH_DN
CK_SATA_PCH_DN CK_96M_DREF_DN
37 OUT 36 OUT 36 OUT
XTAL_25M_PCH_OUT CK_100M_DMI_PCH_DP
IN 44 CK_SATA_PCH_DP CK_96M_DREF_DP
37 OUT 36 OUT 36 OUT
XTAL_25M_PCH_IN OUT 44
1 R63CK 2
1M 1% DESIGN NOTE:
603 CH 1 R7CK 1 R5CK 1 R4CK 1 R3CK 1 R2CK 1 R1CK
10K 10K 10K 10K 10K 10K
WHEN USING 25MHZ EXTERNAL REFERENCE FROM SINAI CMV: 5% 5% 5% 5% 5% 5%
REMOVE R63CK, Y5LB, C56LB 2 CH 2 CH 2 CH 2 CH 2 CH 2 CH
CK_14M_PCH
Y5LB REPLACE C37LB WITH 50OHM RES 0402 PACKAGE 402 402 402 402 402 402
25.000MHZ 44 OUT
1 2
1 R8CK
1 SM 1
10K
XTAL 5%
C56LB C37LB
27PF 27PF 2 CH
5% 5% 402
50V 50V CK_100M_CPHY_PCH_IN_DN
2 COG 2 COG 44 OUT
402 402
CK_100M_CPHY_PCH_IN_DP
A 44 OUT A
V_5P0_A C172BU 1 R13CK 1 R31CK

112 98 96 95 94 89 78 77 32 31 30 1 2 V_1P05_PCH 10 11 40 41 51 92 93 98 103 10K 10K
IN OUT 104 106 107 112 113 116 5% 5%
.1UF 10% 2 CH 2 CH
10V 402 402
X5R
402
DESIGN NOTE:
STITCHING CAPS FOR CK_PE_16PORT_PCH_DP
BPAGE DRAWING
[PAGE_TITLE=PCH 8]
hc_cdb_mpi.sch_1.44
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE:
DISPLAY CONTROL LINE ESD DIODES.
5.0V 5.0V 5.0V

CR3DP CR5DP CR6DP
D TVS5V_UTR TVS5V_UTR TVS5V_UTR
48 45 DPC_TX1_DN 1 OUT 10 DPC_TX1_DN 45 48
D
48 45 BI DPC_HPD_SINK 1 OUT 10 DPC_HPD_SINK
BI 45 48 BI BI 47 45 BI
HDMID_BP_TX1_DP 1 OUT 10 HDMID_BP_TX1_DP
BI 45 47
48 45 DPC_TX1_DP 2 OUT 9 DPC_TX1_DP 45 48

2 OUT 9 BI BI 47 45 BI
HDMID_BP_TX1_DN 2 OUT 9 HDMID_BP_TX1_DN
BI 45 47
DPC_AUX_DN DPC_AUX_DN 48 45 DPC_TX0_DN 4 OUT 7 DPC_TX0_DN 45 48

48 45 BI 4 OUT 7
BI 45 48 BI BI 47 45 BI
HDMID_BP_TX2_DP 4 OUT 7 HDMID_BP_TX2_DP
BI 45 47
DPC_AUX_DP DPC_AUX_DP 48 45 DPC_TX0_DP 5 OUT 6 DPC_TX0_DP 45 48

48 45 BI 5 OUT 6
BI 45 48 BI BI 47 45 BI
HDMID_BP_TX2_DN 5 OUT 6 HDMID_BP_TX2_DN
BI 45 47
GND 3
GND 3 GND 3
REV=1 REV=1 EMPTY REV=1

EMPTY EMPTY
C C
5.0V 5.0V
CR4DP CR7DP 5.0V
TVS5V_UTR TVS5V_UTR CR8DP
B 47 46 45 HDMID_HPD_SINK 1 OUT 10 HDMID_HPD_SINK 45 46 47 48 45 DPC_TX2_DP 1 OUT 10 DPC_TX2_DP
45 48
TVS5V_UTR B
BI BI BI BI HDMID_BP_TX0_DN 1 10 HDMID_BP_TX0_DN
47 45 BI OUT BI 45 47
2 OUT 9 48 45 DPC_TX2_DN 2 OUT 9 DPC_TX2_DN 45 48

BI BI HDMID_BP_TX0_DP 2 9 HDMID_BP_TX0_DP
47 45 BI OUT BI 45 47
HDMID_SDA
47 46 45 4 OUT 7 HDMID_SDA 45 46 47 48 45 DPC_TX3_DP 4 OUT 7 DPC_TX3_DP 45 48
BI BI BI BI HDMID_BP_CLK_DN 4 7 HDMID_BP_CLK_DN
47 45 BI OUT BI 45 47
47 46 45 HDMID_SCL 5 OUT 6 HDMID_SCL 45 46 47 48 45 DPC_TX3_DN 5 OUT 6 DPC_TX3_DN 45 48

BI BI BI BI HDMID_BP_CLK_DP 5 6 HDMID_BP_CLK_DP
47 45 BI OUT BI 45 47
GND 3 GND 3
GND 3
REV=1 EMPTY REV=1 EMPTY

REV=1 EMPTY
A A
CAD NOTE:
PLACE ESD DIODES NEAR BACK PANEL CONNECTORS
[PAGE_TITLE=DISPLAY DATA ESD DIODES]

hc_cdb_mpi.sch_1.45
INTEL
2 1
8 7 6 5 4 3 2 1
U3DP MODULE REV DETAILS

VCC3 VCC3 PS8171
HDMID_LS_OE_N
REV=1
46 IN 25 OE*
1 R18HD 1 R20HD DDSP_D_TX_C_3_DP 48 13 HDMID_CLK_DP
4.7K
46 IN IN_D4+ OUT_D4+ OUT 46 47
0 DDSP_D_TX_C_3_DN 47 14 HDMID_CLK_DN
5% 5% 46 IN IN_D4- OUT_D4- OUT 46 47
D 2 CH 2 EMPTY HDMID_EMI0 DDSP_D_TX_C_2_DP 45 16 HDMID_TX0_DP
402 HDMID_EMI1 46 402 46 IN IN_D3+ OUT_D3+ OUT 46 47
D
IN IN 46 46 DDSP_D_TX_C_2_DN 44 IN_D3- OUT_D3- 17 HDMID_TX0_DN 46 47
1 R19HD 1 R21HD IN OUT
4.7K 0
46
DDSP_D_TX_C_1_DP 42 IN_D2+ OUT_D2+ 19 HDMID_TX1_DP 46 47 BOM NOTE:
5% 5% IN 41 20 HDMID_TX1_DN OUT
2 EMPTY 2 CH
46 IN DDSP_D_TX_C_1_DN IN_D2- OUT_D2- OUT 46 47
402 402
46 IN
DDSP_D_TX_C_0_DP 39 IN_D1+ OUT_D1+ 22 HDMID_TX2_DP
OUT
47
46 REFDES PS8171 PTN3360D
46 DDSP_D_TX_C_0_DN 38 IN_D1- OUT_D1- 23 HDMID_TX2_DN 46
IN OUT 47 R61HD STUFF(422 OHM) STUFF(10K OHM)
HDMID_HPD_SINK 30
VCC3 VCC3 47 46 45 IN HPD_SINK VCC3
R60HD STUFF EMPTY
46 43 DDSP_2_HPD1 7 HPDX
OUT DDPC_CTRL_CLK 9 2
46 43 BI SCL VCC
1 R22HD 1 R28HD 46 43 DDPC_CTRL_DATA 8 SDA VCC 15
BI 21
4.7K 4.7K VCC VCC3
5% 5% 47 46 45 HDMID_SCL 28 SCL_SINK VCC 26
BI 29 40
2 EMPTY HDMID_ASQ1 2 EMPTY PRE_CFG 47 46 45 BI
HDMID_SDA SDA_SINK VCC
402
46
402
46 VCC 46
IN IN 46 HDMID_DDC_EN 32 DDC_EN
1 R23HD 1 R29HD BI 34
0 0 DDCBUF
5% 5% 1 R50HD 1 R51HD 1 R53HD 1 R1HD 1 R2HD
2 CH 2 EMPTY 2.2K 2.2K 10K
5% 5% 5% 10K 10K
402 402 HDMID_LS_PC0 3
46 BI PEQ 2 CH 2 CH 2 CH
5% 5%
C 46 HDMID_LS_PC1 4 PIO 2 CH 2 EMPTY C
BI HDMID_LS_REXT 6
402 402 402
402 402
46 BI REXT
46 BI HDMID_LS_CEXT 10 CEXT
GND 5 46 43 DDPC_CTRL_CLK
1 18
OUT DDPC_CTRL_DATA
BOM NOTE: ASQ0 GND 46 43 OUT
1 R24HD2 12 ASQ1 GND 24 46 HDMID_DDC_EN
0 C7HD 31 OUT HDMID_LS_OE_N
5% 2.2UF GND 46 OUT
20% 27 EMI0 GND 36 HDMID_LS_PC0
REFDES PS8171 PTN3360D 2 EMPTY
1 6.3V
X5R 33 EMI1 GND 37
46
46
OUT HDMID_LS_PC1
402
402 11 43 OUT HDMID_LS_REXT
APD GND 46 OUT
R22HD STUFF EMPTY 35 PRE <E PAD> GND 49
1 1 1 1
R23HD EMPTY STUFF R61HD R60HD R59HD R52HD
10K 0 0 0
R29HD STUFF EMPTY EMPTY 5% 5% 5% 5%
46
HDMID_ASQ1 CH EMPTY EMPTY EMPTY
OUT 402 402 402 402
HDMID_EMI0 2 2 2 2
VCC3 46 OUT
46 HDMID_EMI1
OUT
DESIGN NOTE:
46
PRE_CFG
OUT R52HD:
CAD NOTE: DEFENSIVE PULL DOWN SITE
B VCC3 PUT ALL CAPS NEAR TO B
PS8171 AND PTN3360D VCC PIN
C50HD
7 DDI2_TX3_DP 1 2 DDSP_D_TX_C_3_DP 46 2 U2DP
IN OUT 2 2 2 2 2 2 C61HD PTN3360D
.1UF 10% C11HD C9HD C10HD C58HD C59HD C60HD 0.1UF
10V 402 X5R 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 20% 2 VDD OUT_D4P 13 HDMID_CLK_DP
20% 20% 20% 20% 20% 20% 16V 11 14 HDMID_CLK_DN OUT 46 47
DDI2_TX3_DN C51HD 16V 16V 16V 16V 16V 16V 1 Y5V VDD OUT_D4N OUT 46 47
7 IN
1 2 DDSP_D_TX_C_3_DN
OUT 46 1 Y5V 1 Y5V 1 Y5V 1 Y5V 1 Y5V 1 Y5V 15 VDD OUT_D3P 16 HDMID_TX0_DP
402 402 402 402 402 402
402
21 17 HDMID_TX0_DN OUT 46 47
.1UF 10% VDD OUT_D3N OUT 46 47
10V X5R 26 19 HDMID_TX1_DP
402 C52HD
VDD OUT_D2P OUT 46 47
33 VDD OUT_D2N 20 HDMID_TX1_DN
7 IN
DDI2_TX2_DP 1 2 DDSP_D_TX_C_2_DP
OUT 46 40 22 HDMID_TX2_DP OUT 46 47
46
HDMID_EMI1 VDD OUT_D1P OUT 46 47
.1UF 10% IN 46 VDD OUT_D1N 23 HDMID_TX2_DN
OUT 46 47
10V
X5R
402 46 HDMID_LS_OE_N 25 OE_N REXT 6 HDMID_LS_REXT 46
C53HD
IN BI
7
DDI2_TX2_DN 1 2 DDSP_D_TX_C_2_DN 46 DDSP_D_TX_C_3_DP 48 4 HDMID_LS_PC1
IN OUT 46 IN IN_D4P NC BI 46
46 DDSP_D_TX_C_3_DN 47 IN_D4N NC 10 HDMID_LS_CEXT 46
.1UF 10% IN DDSP_D_TX_C_2_DP 45 34 BI
10V 46 IN IN_D3P NC
X5R 46 DDSP_D_TX_C_2_DN 44 IN_D3N NC 35 PRE_CFG
402 C54HD IN IN 46
7
46 46 IN
DDSP_D_TX_C_1_DP 42 IN_D2P
IN OUT DDSP_D_TX_C_1_DN 41 IN_D2N EQ5 3 HDMID_LS_PC0
A 46 IN BI 46 A
.1UF 10% 46 DDSP_D_TX_C_0_DP 39 IN_D1P
10V IN 38 1
X5R 46 IN DDSP_D_TX_C_0_DN IN_D1N GND
402 GND 5
C55HD HDMID_HPD_SINK 30 HPD_SINK GND 12
7 IN
DDI2_TX1_DN 1 2 DDSP_D_TX_C_1_DN
OUT 46
47 46 45 IN DDSP_2_HPD1 7 18
46 43 OUT HPD_SOURCE GND HDMID_ASQ1 46
.1UF 10% GND 24 IN
10V 46 43 DDPC_CTRL_CLK 9 SCL_SOURCE GND 27
X5R BI DDPC_CTRL_DATA 8 31 HDMID_EMI0
402 46 43 BI SDA_SOURCE GND IN 46
C56HD HDMID_SCL 28 SCL_SINK GND 36
7 IN
OUT 46
47 46 45 BI HDMID_SDA 29 37
47 46 45 BI SDA_SINK GND
.1UF 10% GND 43
10V 46 HDMID_DDC_EN 32 DDC_EN EPAD_GND 49
X5R BI
7 IN
DDI2_TX0_DN 1
C57HD
2
402
DDSP_D_TX_C_0_DN
OUT 46 REV=1
1 OF 1
IC [PAGE_TITLE=HDMI]
.1UF 10%
10V
X5R hc_cdb_mpi.sch_1.46
INTEL
402 <DOCUMENT_NUMBER> 46 1.0
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

L21DP L23DP
60OHM 60OHM
IND 4PIN IND 4PIN
D 46 HDMID_TX2_DP 2 1 HDMID_TX2_DN 46 46 HDMID_TX0_DP 2 1 HDMID_TX0_DN 46
BI BI BI BI
D
2
R134HD 1 R133HD R138HD 1 R137HD
0 0 0 0
5% 5% 5% 5%
EMPTY 2 EMPTY EMPTY 2 EMPTY
47 45 HDMID_BP_TX2_DP 402 3 4 402 HDMID_BP_TX2_DN 45 47 47 45 HDMID_BP_TX0_DP 402 3 4 402 HDMID_BP_TX0_DN 45 47
BI BI BI BI
1
IND IND
L22DP L24DP
60OHM 60OHM
IND 4PIN IND 4PIN
46 HDMID_TX1_DP 2 1 HDMID_TX1_DN 46 46 HDMID_CLK_DP 2 1 HDMID_CLK_DN 46
BI BI BI BI
2
2
R136HD 1 R135HD R140HD 1 R139HD
0 0 0 0
5% 5% 5% 5%
EMPTY 2 EMPTY EMPTY 2 EMPTY
47 45 HDMID_BP_TX1_DP 402 3 4 402 HDMID_BP_TX1_DN 45 47 47 45 HDMID_BP_CLK_DP 402 3 4 402 HDMID_BP_CLK_DN 45 47
BI BI BI BI
1
1
IND IND
C C
VCC
RT1HD
1 2 HDMI_FUSED_5PV
THRMSTR 1 1
C2HD C70HD
6V 470PF .1UF
0.5A 10% 20%
50V 25V
805 2 X7R 2 Y5V
D93461-002 402 603
J1DP
B B
CONN_HDMI
18 +5V REV=1
47 45 HDMID_BP_TX2_DP 1 DATA2+
IN 2 DATA2 SHIELD
47 45 HDMID_BP_TX2_DN 3 DATA2-
IN
IN 5 DATA1 SHIELD
IN
IN 8 DATA0 SHIELD
IN
47 45 HDMID_BP_CLK_DP 10 CLK+
IN 11 CLK SHIELD
VCC 47 45 HDMID_BP_CLK_DN 12 CLK-
IN
13 CEC
CR1HD 47 46 45 HDMID_SCL 15 SCL
IN HDMID_SDA 16
3
.45V 47 46 45 IN SDA
SOT23A
DIO HDMID_HPD_SINK 19
A 46 45 OUT HOT PLUG DET A
1
C12HD 1 R9HD 17
100PF DDC/CEC_GND
1 2 10% 20K
50V 5% 14
V_HDMID_SCL V_HDMID_SDA 2 EMPTY 2 CH
RSVD 1 OF 1
603 402
1 R62HD 1 R63HD CONN
2.2K 2.2K
5% 5%
2 CH 2 CH
402 402
HDMID_SCL
47 46 45 BI
47 46 45 BI
HDMID_SDA [PAGE_TITLE=HDMI]
hc_cdb_mpi.sch_1.47
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
C3DP
7 IN DDI1_TX0_DP 1 2
.1UF 10%
10V 402 X5R RT2HD MODULE NAME REV DATE
45 OUT DPC_TX0_DP
DDI1_TX0_DN 1
C1DP
2
J2DP DPC_PWR_P20 1 2
7 IN
.1UF 10%
E35729-002 THRMSTR
10V 402 X5R DISPLAY_PORT 1 1
C71HD C1HD
45 OUT DPC_TX0_DN
C4DP 470PF 1.0UF 6V
7 DDI1_TX1_DP 1 2 PACK_TYPE=TH 10% 10% 0.50A
IN 1 ML_LANE0 + DP_PWR 20 50V 16V
.1UF 10% 3 ML_LANE0 - 2 X7R 2 X5R
D 10V 402 X5R 402 603
45 OUT DPC_TX1_DP RETURN 19
D
C2DP 4 ML_LANE1 + R14HD
1 2 1 2 DPC_HPD_SINK
7 IN DDI1_TX1_DN 6 ML_LANE1 - HOT_PLUG_DETECT 18 DPC_HPD_SINK_R
OUT 45 48
.1UF 10% 0 5%
10V X5R 7 ML_LANE2 + GND 2 402 CH R1DP
45 DPC_TX1_DN 402 9 ML_LANE2 - GND 5 1 2 CAD NOTE:
OUT C5DP
1 2
7 IN DDI1_TX2_DP GND 8 100K 5% PLACE NEAR CONNECTOR PIN
.1UF 10% 10 ML_LANE3 + GND 11 402 CH
10V 402 X5R 12 ML_LANE3 - CONFIG1 13 HDMI_C_DNG_DETECT 48
45 OUT DPC_TX2_DP
C6DP OUT
7 DDI1_TX2_DN 1 2 CONGIG2 14 HDMI_CONFIG2
IN 15 AUXCH + GND 16
.1UF 10%
10V 402 X5R 17 AUXCH - 1 R17HD
45 OUT DPC_TX2_DN CASE_GND 21 1M
C1DP1 CASE_GND 22 5%
7 DDI1_TX3_DP 1 2
IN CASE_GND 23 2 CH DPC_HPD_SINK
.1UF 10% 402
10V X5R CASE_GND 24 48 45 IN
45 DPC_TX3_DP 402
OUT C1DP2
7 DDI1_TX3_DN 1 2 OPTION 1 OF 2
IN
.1UF 10%
10V 402 X5R REV=1 CONN
45 OUT
DPC_TX3_DN 3
DPC_AUX_DP
48 45 BI VCC
48 45 BI DPC_AUX_DN D Q1DP
C BSS138N C
R10HD 1 FET
1 2 G S
100K 5% 2
402 CH 1 R6DP
3 DPC_AUX_DP 100K
45 48 5%
BI
D Q2DP 2 EMPTY DDSP_1_HPD0 43
402 OUT
BSS138N
48 DP_DEVICE_DETECT
IN BI 48
1 FET
G S
DESIGN NOTE:
2
DDSP_C_AUX2_R_DP
C5HD HPD PASS GATE - PREVENT DRIVING HPD IN POWER OFF
1 2 DDSP_1_AUX_DP 43
BI
.1UF 10%
10V 402 X5R 48
3 DDSP_C_AUX2_R_DP BI
3 DDPB_CTRL_DATA
BI 43 48
3 DPC_AUX_DN 45 48
BI D Q10DP
B BSS138N D Q11DP B
D Q3DP BSS138N
BSS138N VCC3
48 DP_DEVICE_DETECT 1 EMPTY 1
R11HD IN G S 48 IN HDMI_DEVICE_DETECT EMPTY
1 2 G S
1 FET 2
G S 100K 5% 2
402 CH DPC_AUX_DP DPC_AUX_DN 45 48
2 BI
BI 45 48
C6HD DDSP_1_AUX_DN
1 2 43 +12V
DDSP_C_AUX2_R_DN BI
.1UF 10%
10V 402 X5R
1 R2DP 1 R5DP
20K 10K
3 DDPB_CTRL_CLK
1% 1%
BI 43
HDMI_DEVICE_DETECT 2 CH 2 CH
48 IN DESIGN NOTE: 402 402 DP_DEVICE_DETECT
D Q4DP VCC3 48
OUT
BSS138N R12HD DP/HDMI INTEROP SUPPORT
1 2 HDMI_DEVICE_DETECT 48
Q15DP OUT
2.2K 5%
1 FET 402 CH 1 R7DP
G S MBT3904DUAL 3 6 15K
A 2
1% A
DPC_AUX_DP
BI 45 48 HDMI_C_DNG_DETECT 1 R3DP 2 5 2 2 CH
3 DPC_AUX_DN
48 IN HDMI_R2Q5_DNG_DETECT HDMI_Q15DP_PIN2
402
BI 45 48 4.7K 5% 1
402 CH C13HD
D Q5DP 1 R4DP 2 470PF 4 1 XSTR 1 M14HD
10% 4.99K
BSS138N 2 50V 1%
1M 5% EMPTY
402 CH 2 CH
603 402
1 FET
G S
2 DDPB_CTRL_DATA 43 48
BI
VCC3
R13HD [PAGE_TITLE=HDMI_DISPLAY PORT]
1 2
2.2K 5%
402 CH hc_cdb_mpi.sch_1.48
INTEL
2 1
8 7 6 5 4 3 2 1
BOM NOTE: MODULE REV DETAILS

BOM NOTE: STUFF 10K OHM RES (R54LB) FOR PCH PORT80 LED FEATURE (TDE EXPERIMENT)
CRB: STUFF R11LB FOR SKU, 116 115 110 V_3P3_STBY\G

81 80 79 78 77 74 52 51 49 41 36 35 18 IN V_3P3_A
EV: MAKE SURE JUMPER(J10EV) SUIT CASE IS STUFF WHEN RESISTOR IS EMPTY 106 104 102 98 95 94 93 92 91 83 82 102 100 95 94 89 82 81 78 77 67 41 32 30 IN
R11LB
38 IN SLP_S3_PCH_N 1 2 SLP_S3_N
OUT 77 81 93 103 106 110
115 1 R309LB 1 R61LB
0 5% 10K
D 402 CH 1 1 1 1 1 10K 5%
R51LB 1 R50LB 5%
R179LB R178LB R198LB R54LB 499 R55LB 1 R307LB 1K 2 EMPTY D
1K 10K 10K 10K R53LB 2.2K 2.2K 5% 2 EMPTY 402
5% 5% 5% 5% 1% 499 5% 5% 1 R49LB 402
CH 2 CH
CH EMPTY CH CH 402 1% EMPTY 2 CH 402 1K
R128LB 402 402 402 402 CH 402 402 5% PCH_GP31
OUT 38
PCH_SMI_N 1 2 SMI_N 2 2 2 2 402 2 1 R28LB 2 CH SLP_WLAN_N 38 115
116 38 IN OUT 49 77
10K 402 PCH_GP72
OUT
0 5% 5% OUT 38
402 CH WAKE_N
1 R52LB 2 EMPTY OUT 20 22 23 24 25 38 66 114
2.2K 402
IO_PME_N R129LB IO_PME_R_N 5%
116 36 IN 1 2 OUT 77 104 2 CH NFC_GP57 18 38 49
0 5% 402
SML1CLK_PCH
OUT
402 CH OUT 38 104
SML1DATA_PCH 38 104
OUT
PCH_GP60 38 91
OUT
SMLINK0_CLK 18 38 67
OUT
SMLINK0_DATA 18 38 67
OUT
PCH_PORT80_LED 38 64
OUT
PCH_RI_PU 38
OUT
PCH_GP74_PU 18 38 49
OUT
PCH_GP28 OUT 38
C C
50V EMPTY
50V EMPTY
50V EMPTY
50V EMPTY
2
100PF 5%
2
C64LB
100PF 5%
100PF 5%
100PF 5%
C55LB
C54LB
C63LB
DESIGN NOTE:
VCC3
402
402
402
402
C63LB,C64LB,C55LB & C54LB CAPS
1
PLACEHOLDER FOR RC TUNE. DEFAULT EMPTY
1
1
2 1 1 1 1
BOM NOTE: 2 2 1 1
R95LB 2 R37LB R38LB R116LB R45LB
FOR LPT: GP70 STRAP - USB3 PORT4 R107LB R109LB R47LB 10K 10K 10K R43LB
CAD NOTE: 10K R78LB 5% 5% 5% 10K
GP71 - USB3 PORT5. 5% 10K 10K R46LB 10K 1 5% 10K
SOFT STRAP TO DETERMINE NATIVE FUNCTION 5% 5% 10K 5% 1K CH CH CH 5%
SOFT AUDIO TERMINATION: PLACE CLOSE TO PCH CH 5% 402 402 402 CH
402 CH CH CH 1 5% 402 CH
1 402 402 402 R106LB 2 2 2 2 402
1 1 CH
2 CH 2 2
CAD NOTE: 402 402 SMC_RUNTIME_SCI_N 37 104
1 2.2K
SMI_N
OUT
5% OUT 49 77
PLACE R71LB 500MILS NEAR TO R122LB
PLACE R72LB 500MILS NEAR TO R132LB CH PCIEX16_PRSNT2_N 20 37
402 OUT
PLACE R70LB <2 INCH TO R104LB 2 SATA0GP
OUT 37 116
PLACE R192LB 500MILS NEAR TO R133LB SATA1GP
BI 37 52 116
B 74 52 38 AUD_LINK_SDO_R122LB 1 R71LB 2 AUD_LINK_SDO 69 PCH_GP33 B

IN OUT OUT 38
15 5%
402 CH FP_RST_N 10 38 50 64
OUT 104 113 116
74 38
AUD_LINK_SYNC_R132LB 1 R72LB 2 AUD_LINK_SYNC 69
FP_AUD_DETECT
OUT 38 74
IN OUT PCH_SATA_LED_N
15 5% OUT 37 80
402 CH
SATA4GP 37 49 66 116
R70LB AUD_LINK_BCLK
OUT
74 38 AUD_LINK_BCLK_R104LB 2 1 69
IN OUT
15 5% PCH_GP70_PU 40 49
402 CH TERMINATION FOR SOFT AUDIO OUT
74 38 AUD_LINK_RST_R133LB_N 1 R192LB 2 AUD_LINK_RST_CDC 69
PCH_GP71_PU
40 49
IN OUT OUT
15 5%
402 CH DESIGN NOTE:
RESERVE R90LB FOR CRB
1 R90LB SMI_N 49 77
0 OUT
5%
PCH_GP70_PU 40 49
2 CH OUT
J6LB CMOS CLR JUMPER
J20LB
1X3HDR
PROTECTED RTC JUMPER 402
SATA4GP 37 49 66
1X3HDR 1 TP_CLRRTC OUT 116
1 TP_CLRCMOS
2 PCH_SRTCRSTB_PULLUP
2 PCH_RTCRST_PULLUP OUT 38 50
OUT 38 50 3 PCH_GP71_PU 40 49
A 3 NET_CLR_CMOS_JUMPER
NET_CLR_RTC_JUMPER OUT A
1 R69LB 1 R8LB
HDR 4.7K BOM NOTE: DESIGN NOTE: PCH_GP74_PU
HDR 4.7K 5% 1 R100LB
1 R62LB 1 R57LB 1 R127LB OUT 18 38 49
5% DEFAULT: SUITCASE JMPR CRB CAN EMPTY PU/PD RES, WEAK INTERNAL PD 10K 10K 10K
1-2 NORMAL * 2 CH 5% 10K 1 R153LBNFC_GP57
1-2 NORMAL * 2 CH 402 J20LB (1-2) 5% 5% 5% 100K OUT 18 38
402 DESIGN NOTE: 98 95 94 2 EMPTY 2 EMPTY 2 EMPTY 5% 49
2-3 CLR RTC 402 2 EMPTY
2-3 CLR CMOS BOM NOTE: DESIGN NOTE:
83 82
77 74
81
52 402 402 402 2 CH
CLR CMOS IS NOT A FEATURE
ON TIANO BIOS 36 35 18 IN
V_3P3_STBY\G 402 1 R152LB
* = DEFAULT DEFAULT: SUITCASE JMPR J6LB (1-2) * = DEFAULT INTERNAL DEBUG ONLY 51 49 41 100K
ON MPI/EV BOARD 80 79 78 1 R89LB 5%
93 92 91 CH
116 115 110 106 104 102 1 R99LB 10K 2
10K 5% 402
5% 2 CH
2 CH 402
PCH_GP44
402 OUT 38 52
PCH_GP45 38 91
OUT
[PAGE_TITLE=GPIO TERMINATION & RST STRAPS] hc_cdb_mpi.sch_1.49
INTEL
2 1
.
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE: VCC3 MODULE NAME REV DATE
RTC: FLIP-LID XTAL HOLDER (XY1LB) R88LB

1 2 SV_ADVANCE_GP48
OUT 37
USES STANDARD XTAL (Y1LB) 20K 5%
D78481-001 Y1LB 402 CH
XY1LB 32.768KHZ BOM NOTE: J15LB 1 SV ADVANCE MENU TABLE DEBUG FEATURE: FRONT PANEL SWITCHES
1 2 PCH_RTCX1_XTAL 1X2HDR
D XTAL_TH_RM RTC XTAL: ADD (MOD-FILE INSERTION)
HDR GP48 BOARD STYLE
REV=1 TH XTAL A91451-001
REF-DES
(32.768KHZ)
W/OUT X (Y1LB)
USING
DESIGN NOTE:
A91829-020 100
50 EV_SWITCH_ON_N 1 R85LB 2 SW_ON_N 38 64 100 113 116
D
1 RM1 RM2 2 XTAL 2 1 NORMAL MENU (DEFAULT) IN OUT
SV ADVANCE MENU JUMPER
33 5%
1 OF 1 1 R81CV 402 CH 1
0 0 SV ADVANCE MENU C43LB
1.0UF
RM 5% VCC3 20%
2 CH 10V
402 R92LB TEST_SETUP_MENU FP_RST_DEBUG_N 2 Y5V
1 2 IN 603
OUT 35
PCH_RTCX1
38
10K 5% R86LB
OUT 402 CH J8LB 1 TEST SETUP MENU TABLE 1 2 FP_RST_N
113 116
EV_SWITCH_ON_N OUT 10 38 49
1X2HDR OUT 50 100 64 104
0 1A
1
HDR
2
R77LB DESIGN NOTE:
PCH XTAL 1 2
1
603 CH
2
BOM NOTE: GP2 BOARD STYLE
RTC (10 MOHM RES): DO NOT CHANGE
A91829-020
10M 5% 2 SW8LB
603 CH R77LB TO 0402 PACK_TYPE J8LB ENABLE JUMPER 0-1 1 DISABLED (DEFAULT) SW9LB
DESIGN NOTE: 672681-002 672681-002
1 1 0 TEST SETUP MENU ENABLED
C42LB C41LB SW
18PF 18PF TEST SETUP MENU JUMPER SW
4
5% 5%
4
50V 50V
2 COG 2 COG
603 603
C PCH_RTCX2
38
J5LB C
OUT 1X2HDR
1 2
DESIGN NOTE:
R80LB HDR
REMOVE R81CV WITH RTC CRYSTAL CONNECTED TO PCH PIN ON CRB 79 52 51 50 41 IN V_3P0_BAT_VREG 1 2 PCH_INTRUDER_HDR_N
OUT 38
103 89 1M 5%
402 CH
1 MOHM INTRUDER PULL-UP (R80LB)
DESIGN NOTE:
20K RTC PULL-UP (R68LB)
R68LB
79 52 51 50 41 IN V_3P0_BAT_VREG 1 2 PCH_RTCRST_PULLUP
OUT 38 49
103 89 20K 1% C40LB
402 CH 1 2
1UF 20%
6.3V
R253LB X5R
79 52 51 50 41 V_3P0_BAT_VREG 1 2 603 PCH_SRTCRSTB_PULLUP 38 49
103 89
IN OUT
20K 1% C139LB
402 CH 1 2
1UF 20%
B 6.3V B
X5R
603
VCC3
CAD NOTE:
DESIGN NOTE:
OVERLAP R66LB AND R41LB PADS

FOR SOP ENABLE AND FLASH
STUFF FOR RECOVERY USAGE ONLY
1 R41LB
10K
5% DESIGN NOTE: CONFIG / RECOVERY JUMPER
2 EMPTY RECOVER/CONFIGURE HEADER MODE
402 J7LB D144776-012 IS SMT HDR VCC3
TH 1X3HDR BLOCK THERMAL TOOL
GP39_GFX_CRB_DETECT 37 JUMPER ON 1-2 * NORMAL
OUT
R73LB 2 JUMPER ON 2-3 CONFIGURE
1K JUMPER REMOVED RECOVERY
CONFIGURE= SAFE MODE 5%
1 R66LB CH * DEFAULT JUMPER SETTING
402 1
10K
5% J7LB
2 CH 1X3HDR
402 1 PCH_CONFIG_JUMPER 37
2
OUT
A RECOVERY_CONFIGURE_PULLUP A
VCC3 3 SPKR_R 1
R125LB HDR R74LB
1 2 MFG_MODE 1 R228LB 4.7K
OUT 37 5%
D14776-012 2.2K
10K 5% 5% CH
GFX SELECT TABLE 402 CH J14LB 1
2 CH 402
1X2HDR 402 2
GP39 GFX STYLE HDR 70 38 SPKR
BOM NOTE: A91829-020 IN
0 NORMAL GFX 2
J14LB ENABLE JUMPER 0-1
1 CUSTOMER GFX DESIGN NOTE:

MFG MODE JUMPER
[PAGE_TITLE=PCH PIN STRAPS]
hc_cdb_mpi.sch_1.50
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

110 106 104 102 98 95 94 93 92 91 V_3P3_STBY\G C15LB

74 52 49 41 36 35 18 2 1 112 107
83 82 81 80 79 78 77
IN 103 98
2
116 115 1UF 10% 51 44 C100LB
11 10 V_1P05_PCH 2 1
C18LB 6.3V
41 40
IN
VCC3 1UF X5R
D 10% 402 93
106
92
104
1UF 10%
6.3V
6.3V 116 113 X5R
D
X5R 41 11 V_CPU_VCCIO2PCH
402 IN 402
1
C16LB
2 1
1 2 2 C323LB
C3LB C34LB C35LB 2 1
.1UF 10% 1UF .1UF .1UF
16V 20% 10% 10% CAD NOTE:
X7R 6.3V 16V 16V 0.1UF 20%
402 2 X5R 1 X7R 1 X7R 16V
CAD NOTE: 603 402 402 PCH CORE POWER DECOUPLING Y5V
2 C14LB 1 V_3P3_BG
IN 41 115 402
PLACE C3LB C38LB
1UF 10%
6.3V C12LB EAST CORNER 2 1
X5R 2 1 OF PCH
402 1UF 10%
1UF 10% 6.3V
C62LB X5R
2 1 6.3V
X5R 402
.1UF 10% 1
C46BU
2
402
16V 2 C48LB 1
X7R
402 .1UF 10% 0.1UF 20%
C23UB 16V 16V
1 2 X7R
402 89
Y5V
402
1UF 10% C136LB 52 C39LB
6.3V V_1P5_PCH 1 2 41 V_3P0_BAT_VREG 2 1
X5R 106 66 44 41 40 37 36 IN IN C6LB
C 402 115 114 50 2 1 C
79 .1UF 10%
.1UF 10% 103 16V
10V EMPTY X7R 0.1UF 20%
402 402 16V
Y5V
402
C890LB
1 2
VCC3 VCC3 10UF 20%
6.3V
X5R
C127LB C10BC 805
2 1 2 1
C888LB
1UF 10% .1UF 10%
6.3V 10V
X5R EMPTY 94 92 83 41 18 IN V_3P3_EPW 10UF 20%
402 402
116 6.3V
C126LB 112 C128LB X5R
2 1 1 106 104 103 98 93 92 51 44 41 40 11 10 V_1P05_PCH 2 1 805
C111LB 107
IN
1UF
1UF 10% 10% 113 1UF 10%
6.3V 6.3V 6.3V
X5R DESIGN NOTE: X5R 2
402 402 2
C129LB
1
X5R
402
C125LB DEFENSIVE DESIGN FOR
2 1
1UF 10%
VCCASEFLEX0_3P3 POWER
B 1UF 10%
6.3V
X5R
B
6.3V 402 C130LB
X5R 2 1
402
1UF 10%
6.3V
V_1P05_ME X5R
402
112 92 41 IN
1 1
C112LB C90LB
1UF 10UF
10% 20% 116 113 112 107 C131LB
6.3V 92 51 44 41 40 11 10
V_1P05_PCH 1 2
6.3V
X5R 2 2 X5R IN
402 603 V_1P05_PCH
106 104 103 98 93
1UF 10%
44 41 40 11 10 IN 6.3V
DESIGN NOTE: VCC3 116 113 112 107 106 104 103 98 93 92 51 X5R 402
C24LB
STITCHING CAPS FOR NOA 1 2
C132LB
1 2
1UF 10%
C91LB 6.3V
X5R 1UF 10%
103 98 93 92 51 44 41 40 11 10 V_1P05_PCH 1 2 CAD NOTE: 6.3V
116 113 112 107 106 104
IN 402 X5R 402
0.1UF 20% V_1P05-FILTER CAPS: PLACE NEAR
16V
Y5V ENDS OF POWER CORRIDOR C25LB C133LB
1 2
402 1 2
A 1UF 10%
A
1UF 10% 6.3V
6.3V X5R 402
X5R
402
DESIGN NOTE: C134LB
1 2
GENERAL PURPOSE DCPL CAPS 1UF 10%

6.3V
X5R 402
[PAGE_TITLE=PCH DECOUPLING]
hc_cdb_mpi.sch_1.51
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE: MODULE NAME REV DATE
VCC3 DESIGN NOTE:
FOR GPIO37
LOW:TLS CIPHER SUITE WITH NO CONFIDENTIALITY.
1 R143LB HIGH:TLS CIPHER SUITE WITH CONFIDENTIALITY. R145LB
1K 49 38 IN
PCH_GP44 1 2
5%
10K 5%
D 2 CH 402 EMPTY
402 D
PCH_GP37 37 116
BOOT SELECT STRAPS
OUT
1 R79LB
10K
5% BOOT DEVICE GP51 GP19/SATA1GP
BOM NOTE:
2 EMPTY
LPC 0 0
402
EMPTY R34LB AND R31LB FOR
DESIGN NOTE: SPI 1 1 PRODUCT
DFX TEST MODE QUALIFIER FOR OTHER DFX STRAP WHEN SAMPLED LOW
116 49 37 SATA1GP 1 R34LB 2
OUT
1K 5%
R302LB 402 EMPTY
35
PCH_GP55 1 2
OUT
VCC3 A16 SWAP OVERRIDE 1K 5% PCH_GP51 1 R31LB 2
DESIGN NOTE: 402 EMPTY 35 OUT
OVERRIDE IF SAMPLED LOW DESIGN NOTE:
DESIGN NOTE: 1K 5%
402 EMPTY
DMI RX TERMINATION PCH_GP53 R30LB WEAK INTERNAL PULLUPS ON GP51. DEFAULT SPI BOOT DEVICE.
1 R36LB 35 OUT 1 2
1K
5% DMI AC COUPLING 1K 5%
DESIGN NOTE: 402 EMPTY
2 EMPTY FULL VOLTAGE MODE WHEN SAMPLED LOW
402 R320LB
C PCH_GP36 38 SUSCLK 1 2 C
OUT 37 116
DESIGN NOTE: OUT
1.5K 5% R321LB LED_DRIVE_GP15
116 115 V_3P3_STBY\G
1 R142LB 402 EMPTY
81 80 79 78 77 74 52 51 49 41 36 35 18 IN 1 2 OUT 38 80
10K (SUSCLK)GP62: OD PLL VR ENABLE 110 106 104 102 98 95 94 93 92 91 83 82
5% DISABLED WHEN SAMPLED LOW 4.7K 5%
402 CH
2 EMPTY
R306LB R126LB
402
DESIGN NOTE: 116 38 BI IGC_EN_N 1 2 1 2
0 5% 1K 5%
CLOCK VALIDATION STRAP 402 CH 402 CH
IGC IS ENABLED WHEN SAMPLED LOW
BOM NOTE: BOM NOTE:
18 OUT PCH_GP8
J81EV DEFAULT STUFF (1-2) J10LB DEFAULT 0-1, SPI
BOARD ID STRAPS DELETE J81EV IN CRB OVERRIDE PROTECTION J10LB
1X2HDR
116 115 110 106 104 102 V_3P3_STBY\G R33LB AUD_LINK_SDO_R122LB
BRD ID TABLE 81 80 79 78 77 74 52 51 49 41 36 35 18 2 1 AUD_LINK_PU 2 1 38 49 74
98 95 94 93 92 91 83 82
IN OUT
5% 1K
BIT3 2 1 0 BRD ID DESIGN NOTE: HDR CH 402
CAD NOTE: VCC3 LPT FLASH DESCRIPTOR OVERRIDE.HI FOR OVERRIDE SOP ENABLE JUMPER
0 0 0 1 FLATHEAD CREEK EV
B R82LB B
VCC3 1 R25LB V_3P0_BAT_VREG 2 1 PCH_INTVRMEN
0 0 1 0 FLATHEADCREEK DOE 52 51 50 41 IN OUT 38
10K DESIGN NOTE: 103 89 79
5% 390K 5%
0 1 1 1 FLATHEADCREEK CRB R96LB 402 CH 1 R83LB
1 2 SV_DETECT 2 CH IINTEGRATED 1.05V SUS VRM ENABLE 1K
OUT 37 402 5%
SUS VRM ENABLED WHEN SAMPLED HIGH
1 0 0 0 HADDOCK CREEK AIO 10K 5% 1 R93LB 2 EMPTY
402 EMPTY PCH_GP17 37
47K OUT 402
5%
2 CH 1 R101LB
402 10K
5%
2 EMPTY
402
DESIGN NOTE:
103 89 79 52 51 50 41
V_3P0_BAT_VREG 2 R75LB 1 DSWODVREN 38
VCC3 IN OUT
VCC3 VCC3 DSWODVREN HI FOR ALL PRODUCTS 390K 5%
402 CH
1 R98LB 1 R108LB
10K 10K 1 R24LB
5% 10K
5% 5%
2 EMPTY 2 EMPTY
402 402 2 EMPTY
402
PCH_GP6 PCH_GP34 VCC3
OUT 37 38 PCH_GP1
OUT OUT 37
A 1 R118LB 1 R2LB 1 R59LB A

10K 10K 10K 1 R42LB
5% 5% 5% 10K
2 CH 2 CH 2 CH 5%
402 402 402 2 CH
402
DESIGN NOTE:
PCH_GP49 37 116
OUT
1 R21LB
BIT GPIO 10K
PCH_GP46 38 91
5% OUT
CAD NOTE: 3 GP17 (PCH_GP17) 2 EMPTY
402
OVERLAP R98LB AND R118LB PADS 2 GP34 (PCH_GP34) 1 R94LB
OVERLAP R24LB AND R59LB PADS 100
1 GP1 (PCH_GP1) 5%
OVERLAP R108LB AND R2LB PADS 0 GP6 (PCH_GP6)
DESIGN NOTE:
2 EMPTY
402
[PAGE_TITLE=PCH STRAPS]
RESERVE GP69 (SV_DETECT) BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
GPIO49 CAN BE USE AS PCIE/MSATA MUX SELECT IN LPT
hc_cdb_mpi.sch_1.52
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SATA GEN 3 RIGHT ANGLE HEADERS BOM NOTE:
DEFAULT 0.01UF, 0402, A36096-045, 10%, 25V, X7R
OPTIONAL 0 OHM, 0402, A36093-001
D C202BU
SATAHDR_TX2_R_DP 1 2 SATAHDR_TX2_DP IN 37 D
.01UF 10%
25V 402
X7R
C203BU
SATAHDR_TX2_R_DN 1 2 SATAHDR_TX2_DN IN 37
J17LB .01UF 10%

25V 402
X7R
SATA3_2STACK C204BU
SATAHDR_RX2_R_DN 1 2 SATAHDR_RX2_DN OUT 37
GND A1
16 A2 .01UF 10%
NC A_TX+ 25V
A_TX- A3 X7R 402
17 NC GND A4
A_RX- A5 C205BU
A_RX+ A6 SATAHDR_RX2_R_DP 1 2 SATAHDR_RX2_DP OUT 37
GND A7
.01UF 10%
GND B1 C210BU
B2 SATAHDR_TX3_R_DP 1 2 SATAHDR_TX3_DP
MT3 B_TX+
18 IN 37
B_TX- B3
C B4 .01UF 10% C
15 GND
MT4 B_RX- 25V 402
B5 X7R
B6 C211BU
B_RX+ SATAHDR_TX3_R_DN 1 2 SATAHDR_TX3_DN 37
GND B7 IN
.01UF 10%
25V 402
X7R
CONN C212BU
SATAHDR_RX3_R_DN 1 2 SATAHDR_RX3_DN OUT 37
.01UF 10%
25V 402
X7R
C213BU
SATAHDR_RX3_R_DP 1 2 SATAHDR_RX3_DP OUT 37
.01UF 10%
25V 402
X7R
25V 402
X7R
B C206BU B
SATAHDR_TX0_R_DP 1 2 SATAHDR_TX0_DP IN 37
.01UF 10%
25V 402
X7R
J9LB C207BU
SATA3_2STACK
.01UF 10% SATA GEN 3 VERTICAL HEADER
25V
GND A1 X7R 402
16 NC A_TX+ A2 C208BU
A_TX- A3 SATAHDR_RX0_R_DN 1 2 SATAHDR_RX0_DN OUT 37
17 NC GND A4
A5 .01UF 10%
A_RX- 25V 402 J19LB SATAHDR_TX5_R_DP 1
C237BU
2 SATAHDR_TX5_DP
A_RX+ A6 X7R SATA IN 37
GND A7 C209BU 1X7HDR .01UF 10%
SATAHDR_RX0_R_DP 1 2 SATAHDR_RX0_DP OUT 37 TXP 2 25V
1 GND EMPTY402
.01UF 10% 3 C238BU
GND B1 25V 402 TXN
B2 X7R 4 GND
18 MT3 B_TX+
B_TX- B3 C214BU RXN 5 .01UF 10%
B4 SATAHDR_TX1_R_DP 1 2 SATAHDR_TX1_DP 7 GND 25V
15 GND
MT4 B_RX- IN 37
6 EMPTY402
B5 RXP
B6 .01UF 10% C239BU
B_RX+ 25V SATAHDR_RX5_R_DN 1 2 SATAHDR_RX5_DN 37
A GND B7 X7R 402 HDR OUT A
C215BU .01UF 10%
SATAHDR_TX1_R_DN 1 2 SATAHDR_TX1_DN IN 37 25V
EMPTY402
CONN .01UF 10% C240BU
25V 402
X7R
C216BU .01UF 10%

SATAHDR_RX1_R_DN 1 2 SATAHDR_RX1_DN OUT 37 25V
EMPTY402
.01UF 10%
25V
X7R 402
C217BU
.01UF 10%
25V 402
X7R [PAGE_TITLE=SATA CONNECTORS]
hc_cdb_mpi.sch_1.53
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

FRONT PANEL HEADER #1 MODULE NAME REV DATE
CAD NOTE:
DO NOT CHANGE TO 402 CAD NOTE:
OVERLAPPING FOOTPRINTS DO NOT CHANGE TO 402
D CR3BU OVERLAPPING FOOTPRINTS
1 R14BU 2 TVS6V 6.0V D
0 1A 1 R17BU 2
603 CH
6 1 0 1A
603 CH
104 98 5VDUAL
66 60 59
55 54 31 5 2
USB_P12_DP L1BU 58 57 56
IN
36 3 2 96 90 84
BI 112 L2BU
90OHM 4 3 4 1 USB_P13_R_DP BI 66
ACM2012 EMPTY
90OHM
USB_P12_DN L1BU EMPTY ACM2012
36 4 1
BI L2BU
90OHM DIO 3 2 USB_P13_R_DN BI 66
ACM2012 EMPTY
D16982-001 90OHM
ACM2012 EMPTY
1 R15BU 2
0 1A J8BU 1 R16BU 2
603 CH 2X5HDR_9 0 1A
1 2 603 CH
USB_P12_R_DN 3 4 USB_P13_J8BU_DN
USB_P12_R_DP 5 6 USB_P13_J8BU_DP
C 7 8 C
10 USB_OC_FRONT1_PIN10
HDR
1 R18BU 2
DESIGN NOTE:
1 0 1A
C226BU 603 EMPTY 1 R19BU CAUTION: 0 OHM TO GND
470PF 0
10%
BOM NOTE: 5% BOM NOTE:
50V
2 X7R 2 EMPTY
603 402 STUFF FOR CUSTOM
STUFF FOR PRODUCT
FUSED (OPT-P10-GND)
WITH FUSE ON
FRONT PANEL SUPPORT
FRONT PANEL
USB_FP1_PWR USB_OC_FRONT1_R_N
54
1 R20BU 2 54
IN OUT
0 1A
B 603 CH B
BOM NOTE: PORT 12,13 - OC6
STUFF FOR PRODUCT
WITH FUSE ON BOARD
NOT ON FP
FRONT PANEL POWER #1

DESIGN NOTE: DESIGN NOTE:
PLACE NORTH OF C13LB USB BREAKOUT STUFFING THE THERMISTOR ASSUMES FRONT PANEL CARD
HAS NO FUSE AND DOES NOT PROVIDE OVER-CURRENT PROTECTION
RT1BU
58 57
112 104
56 55 54
98
31 IN
5VDUAL 1 2 USB_FP1_PWR OUT 54
96 90 84 66 60 59
R60BU 1 C253BU
1 R54BU THRMSTR 1 470.0UF
15K 6V 10K 20%
5% 1.50A
5% 6.3V
ELEC
A 2 CH 2 CH 2 RDL A
402 402
USB_OC_FRONT1_N
OUT 36 1 R58BU 2
CAD NOTE:
0 5%
1 R55BU DUAL FOOTPRINT: PLACE 0 OHM
1206 EMPTY
10K 1206 IN PARALLEL WITH THERMISTOR
5% CAD NOTE:
2 CH BOM NOTE:
PLACE DECOUPLING AS CLOSE AS POSSIBLE
USB_OC_FRONT1_R_N 402
54 STUFF 0 OHM INSTEAD OF THERMISTOR FOR
IN PRODUCT WITH FUSE ON FRONT PANEL TO USB CONNECTOR
[PAGE_TITLE=USB FP HDR 1]
hc_cdb_mpi.sch_1.54
INTEL
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MODULE REV DETAILS

CR11BU
TVS6V 6.0V
6 1
D
CAD NOTE: D
5VDUAL
DO NOT CHANGE TO 402 96 90 84 66 CAD NOTE:
56 55 54 31 5 2
OVERLAPPING FOOTPRINTS 60 59 58 57
IN DO NOT CHANGE TO 402
112 104 98 OVERLAPPING FOOTPRINTS
1 R122BU 2 4 3
1 R144BU 2
0 1A
603 CH 0 1A
603 CH
DIO
D16982-001
USB_P6_DP L61BU
36 3 2 L62BU
BI 2 3 USB_P7_DP
90OHM 36
ACM2012 EMPTY
BI
90OHM
L61BU EMPTY ACM2012
36 BI USB_P6_DN 4 1 L62BU
90OHM 1 4 USB_P7_DN BI 36
ACM2012 EMPTY J22BU 90OHM
2X5HDR_9 EMPTY ACM2012
1 R121BU 2 1 2
USB_P6_R_DN 3 4 USB_P7_R_DN
1 R145BU 2
C 0 1A USB_P6_R_DP 5 6 USB_P7_R_DP C
603 CH 7 8 0 1A
10 USB_OC_FRONT2_PIN10 1 R141BU 2 603 CH
0 1A
HDR 603 EMPTY
1 R40BU
0
5%
2 EMPTY
402
55 USB_FP2_PWR 1 R142BU 2 USB_OC_FRONT2_R_N

IN OUT 55
0 1A
603 CH
BOM NOTE:
B B
STUFF FOR PRODUCT
WITH FUSE ON BOARD
1
C121BU NOT ON FP
470PF
10%
50V
2 X7R
603 PORT 6, 7 - OC3

DESIGN NOTE:
STUFFING THE THERMISTOR ASSUMES FRONT PANEL CARD
RT2BU
98 96 90 84 66 60 59 58 57 56 55 54 31 IN 5VDUAL 1 2 USB_FP2_PWR OUT 55
112 104
1 C254BU
1 R56BU
THRMSTR 1 R61BU 470.0UF
15K 6V 10K 20%
A 5% 1.50A
5% 6.3V A
ELEC
2 CH 2 CH 2 RDL
402 USB_OC_FRONT2_N 402
OUT 36 1R59BU 2
CAD NOTE:
0 5%
1 R57BU 1206 EMPTY
DUAL FOOTPRINT: PLACE 0 OHM
5% CAD NOTE:
2 CH BOM NOTE:
402 PLACE DECOUPLING AS CLOSE AS POSSIBLE
STUFF 0 OHM INSTEAD OF THERMISTOR FOR
55
USB_OC_FRONT2_R_N PRODUCT WITH FUSE ON FRONT PANEL TO USB CONNECTOR
IN
hc_cdb_mpi.sch_1.55
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MODULE REV DETAILS

USB_FP3_PWR 1
R85BU
2 USB_OC_FRONT3_R_N
56 IN OUT 56
0 1A
603 CH
1
C303BU
470PF
10%
D 2 50V
X7R 1 R12BU
603 0 D
1A
2 EMPTY
603
J19BU
CONN_USB3_FP
REV=1
1 VBUS VBUS 19
USB3_ID_PIN10 10 ID
USB3_RX2_DN USB3_TX1_DN
40 2 SSRX1- SSTX2- 15 40
OUT USB3_RX2_DP 3 14 USB3_TX1_DP IN
1 R13BU 40 OUT SSRX1+ SSTX2+ IN 40
0
USB3_TX2_DN USB3_RX1_DN
1A 40 5 SSTX1- SSRX2- 18 40
IN USB3_TX2_DP 6 17 USB3_RX1_DP OUT
2 EMPTY 40 IN SSTX1+ SSRX2+ OUT 40
603
36 USB_P1_DN 8 D1- D2- 12 USB_P0_DN 36
BI USB_P1_DP 9 11 BI
36 BI D1+ D2+ USB_P0_DP BI 36
7 GND GND 16
C 4 GND GND 13 C
1 OF 1
PORT 0,1 - OC0 CONN
B B

DESIGN NOTE:
112 104
90 84
59
54
58
31
5VDUAL 1 RT8BU
2 USB_FP3_PWR
56
57 55
IN OUT
1 C307BU
1 R81BU
66
98
60
96
THRMSTR 1 R84BU 470UF
15K 6V 10K 20%
5% 3.50A
5% 10V
ALUM
2 CH 2 CH 2 RDL
OUT 36 1 R83BU 2
CAD NOTE:
0 5%
1 R82BU 1206 EMPTY
A DUAL FOOTPRINT: PLACE 0 OHM A
5% CAD NOTE:
2 CH BOM NOTE:
MODFILE RT8BU TO C92281-012 STUFF 0 OHM INSTEAD OF THERMISTOR FOR
56
IN
hc_cdb_mpi.sch_1.56
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MODULE REV DETAILS

R155BU
USB_FP4_PWR 1 2 USB_OC_FRONT4_R_N
57 IN OUT 57
0 1A
603 CH
1
C189BU
470PF
D 10%
50V D
2 X7R 1 R156BU
603 0
1A
2 EMPTY
603
J9BU
CONN_USB3_FP
REV=1
1 VBUS VBUS 19
USB3_FP4_ID_PIN10 10 ID
USB3_RX6_DN USB3_TX5_DN
40 2 SSRX1- SSTX2- 15 40
OUT USB3_RX6_DP 3 14 USB3_TX5_DP IN
1 R157BU 40 OUT SSRX1+ SSTX2+ IN 40
0
USB3_TX6_DN USB3_RX5_DN
1A 40 5 SSTX1- SSRX2- 18 40
IN USB3_TX6_DP 6 17 USB3_RX5_DP OUT
2 EMPTY 40 IN SSTX1+ SSRX2+ OUT 40
603
36 BI USB_P5_DN 8 D1- D2- 12 USB_P4_DN BI 36 VCC
36 USB_P5_DP 9 D1+ D2+ 11 USB_P4_DP 36
BI BI VCC
C 7 GND GND 16 C
4 GND GND 13
1 OF 1 2 1 1
C53LB C49LB C51LB
PORT 4,5 - OC2 CONN .1UF .1UF .1UF
10%
10% 10%
10V 10V 10V
1 X5R 2 X5R 2 X5R
402 402 402 VCC3
CAD NOTE:
USB STITCH CAPS
B B

DESIGN NOTE:
112 104
90 84
59
54
58
31
5VDUAL 1 RT4BU
2 USB_FP4_PWR
57
56 55
IN OUT
C30BU
1 R21BU
66
98
60
96
THRMSTR 1 R4BU 470UF
15K 6V 10K 20%
5% 3.50A
5% 10V
ALUM
2 CH 2 CH RDL
OUT 36 1 R2BU 2
CAD NOTE:
0 5%
1 R22BU 1206 EMPTY
DUAL FOOTPRINT: PLACE 0 OHM
5% CAD NOTE:
A 2 CH BOM NOTE: A
MODFILE RT8BU TO C92281-012 STUFF 0 OHM INSTEAD OF THERMISTOR FOR
57
IN

hc_cdb_mpi.sch_1.57
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MODULE REV DETAILS

BACK PANEL USB BOM NOTE:
DEFAULT USE E47637-001 FOXCONN PART, AVOID LOTES UNTIL SIE FURTHER NOTICE
IPN E47637-003 INCLUDE LOTES & FOXCONN PART
36
USB3_TX3_DP 1
C165BU
2 USB3_TX3_C_DP
61
PORT 2,3 - OC1 BP USB3 J10BU
IN OUT
.1UF 10%
CON2XUSB3
C161BU 402
10V
D USB3_TX3_DN 1 2 X5R USB3_TX3_C_DN
36 IN OUT 61 58 VREG_USB_BP1_STACK 1 VBUS VBUS 10 VREG_USB_BP1_STACK 58 D
BI 2 11 BI
.1UF 10%
58 BI USB_P2_R_DN D- D- USB_P3_R_DN
BI 58
58 USB_P2_R_DP 3 D+ D+ 12 USB_P3_R_DP 58
10V 402
C163BU USB3_TX4_C_DP BI 4 13 BI
36
USB3_TX4_DP X5R 1 2 61
GND GND
IN OUT 61 USB3_TX3_ESD_DP 9 SSTX+ SSTX+ 18 USB3_TX4_ESD_DP 61
IN USB3_TX3_ESD_DN 8 17 USB3_TX4_ESD_DN IN
.1UF 10% 61 IN SSTX- SSTX- IN 61
10V 402
7 GND GND 16
C162BU
USB3_TX4_DN 1 2 X5R USB3_TX4_C_DN 61 OUT USB3_RX3_ESD_DP 6 SSRX+ SSRX+ 15 USB3_RX4_ESD_DP OUT 61
36 IN .1UF 10% OUT 61 61 OUT USB3_RX3_ESD_DN 5 SSRX- SSRX- 14 USB3_RX4_ESD_DN OUT 61
10V 402
X5R
19 SHLD SHLD 21
20 SHLD SHLD 22
1 OF 1
REV=2 CONN
R36BU
1 2
0 1A
603 EMPTY 6.0V
C U5BU C
TVS6V
L9BU
36 BI USB_P2_DN 2 3 USB_P2_R_DN 58
BI USB_P2_R_DP
90OHM 1 6 USB_P2_R_DN
ACM2012 IND 58 BI BI 58
L9BU USB_P2_R_DP
36 BI USB_P2_DP 1 4
BI 58 2 5 5VDUAL
BI 31 54 55 56 57 58 59 60 66 84 90 96 98 104
90OHM 112
ACM2012 IND
R37BU USB_P3_R_DP USB_P3_R_DN
58 3 4 58
1 2 BI BI
CAD NOTE: 0 1A DESIGN NOTE:
603 EMPTY
DO NOT CHANGE TO 402 STUFF L9BU & L10BU FOR EV & ERB
OVERLAPPING FOOTPRINTS DIO
R38BU AND EMPTY R36BU, R37BU, R38BU, R39BU
1 2
0 1A ONLY FOR EV & ERB VCC
603 EMPTY
Q8CV
1
B L10BU B
36 BI USB_P3_DP 1 4 USB_P3_R_DP BI 58
58 OUT VREG_USB_BP1_STACK 3
90OHM 2
ACM2012 IND
L10BU
USB_P3_DN 2 3 USB_P3_R_DN BAT54C
36 BI BI 58 SOT23C
90OHM EMPTY
ACM2012 IND
R39BU
1 2
0 1A 58 IN VREG_USB_BP1_STACK
603 EMPTY
1
C26BU
4.7UF
DESIGN NOTE: 10%
6.3V
2 X5R
DEFENSIVE DESIGN CAP 603
2 R65BU 1 USB_OC_BACK1_N 36
OUT
15K 5%
402 CH
2 CAD NOTE:
BOM NOTE: R66BU PLACE CAP AS CLOSE AS POSSIBLE

10K CAD NOTE:
A MODFILE RT6BU TO C92281-012 5% TO USB CONNECTOR A
CH
402 PLACE AS CLOSE AS POSSIBLE
104 98 1 TO USB CONNECTOR
84 66 RT6BU 58 IN VREG_USB_BP1_STACK
58
54
57
31 IN 5VDUAL 1 2 VREG_USB_BP1_STACK OUT 58 1
56 55 DESIGN NOTE: C230BU
60 59 THRMSTR 2 1 C257BU 470PF
96 90 470.0UF 10%
112 6V R67BU 20% DOUBLE STACK USB 50V
3.50A 10K 6.3V 2 X7R
5% ELEC STUFF ALWAYS 402
CH
2 RDL
VREG_USB MUST BE SPLIT 1
402
AMONGST ALL USB CHANNELS. [PAGE_TITLE=USB BACK PANEL/DP STACK 2]
DO NOT DAISY CHAIN
hc_cdb_mpi.sch_1.58
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MODULE REV DETAILS

CAD NOTE:
DESIGN NOTE: BOM NOTE:
DO NOT CHANGE TO 402
CONNECTOR STUFFING OPTIONS:
MJ/USB DUAL OVERLAPPING FOOTPRINTS
R32BU RJ45/2 USB - C73572-001 (DEFAULT)
CAD NOTE:
1 2 DOUBLE STACK USB - 749193-001, NOT 642575-124 VREG_USB_BP_MJ
68 59 IN
0 1A
D 603 EMPTY PLACE CAP AS CLOSE AS POSSIBLE
DOUBLE-STACK CONNECTOR FOR USB/LAN IS ON OTHER PAGE
WITH THE REST OF THE CONNECTOR 1 TO USB CONNECTOR D
C20BU
4.7UF
L7BU 10% 68 59 IN VREG_USB_BP_MJ
USB_P10_DN 1 4 USB_P10_R_DN 6.3V
36 BI BI 59 68 DESIGN NOTE: 2 X5R 1
90OHM 603
C229BU
ACM2012 IND DEFENSIVE DESIGN CAP 470PF
L7BU 10%
USB_P10_DP 2 3 USB_P10_R_DP 50V
36 BI BI 59 68 2 X7R
90OHM CR6BU 402
ACM2012 IND TVS6V 6.0V
R33BU
1 2 1 6 J11BU
CAD NOTE:
0 1A 2 X USB
603 EMPTY VREG_USB_BP_MJ
2 5 5VDUAL OVERLAP WITH MAGJACK FOOTPRINT 68 59 IN 1 9
IN 31 54 55 56 57 58 59 60 66 84 90 96 98
R34BU 104 112 USB PINS ARE TRANSPOSE
68 59 USB_P10_R_DN 2
1 2 BI USB_P10_R_DP 3
68 59 BI
0 1A 3 4 4 10
603 EMPTY BOM NOTE:
EMPTY, EXCEPT FOR USB W/NO-LAN OPTION 68 59 VREG_USB_BP_MJ
IN
CONNECTOR STUFFING OPTIONS: 5 11
DIO RJ45/2 USB - A11509-001 (OLDER DESIGNS,
C L8BU 68 59 USB_P11_R_DN 6 C
USB_P11_DN 1 4 USB_P11_R_DN PRE-GIGABIT LAN) BI USB_P11_R_DP 7
36 BI BI 59 68 68 59 BI
DOUBLE STACK USB (NO LAN) - 749193-001 8 12
90OHM
ACM2012 IND
L8BU USB_P11_R_DP
36 USB_P11_DP 2 3 59 68
EMPTY
BI BI
90OHM
ACM2012 IND DESIGN NOTE:
PORT 10,11 - OC5
R35BU STUFF L7BU & L8BU FOR EV & ERB
1 2
AND EMPTY R32BU, R33BU, R34BU, R35BU
0 1A
603 EMPTY ONLY FOR EV & ERB
2 R62BU 1 USB_OC_BACK2_N 36
OUT
BOM NOTE: 15K 5%
402 CH 2
CHANGE C317BU TO 10V VOLTAGE RATING
(IPN: A65154-041) R63BU CAD NOTE:
10K
B 5% B
PLACE AS CLOSE AS POSSIBLE
CH
104 98 402 TO USB CONNECTOR
84 66 RT3BU 1
58
54
57
31
5VDUAL 1 2 VREG_USB_BP_MJ 59 68
56 55
IN OUT
60 59 THRMSTR 2
C255BU 1
96 90
112 1 C317BU R64BU
1
470.0UF
C256BU
1000UF 470PF
20.0% 1.50 10K 20% 10%
10V 5% 6.3V 50V
ALUM ELEC 2 X7R
2 TH VREG_USB MUST BE SPLIT
CH
402
2 RDL 603
AMONGST ALL USB CHANNELS. 1
DO NOT DAISY CHAIN
A A
[PAGE_TITLE=USB BACK PANNEL]

hc_cdb_mpi.sch_1.59
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MODULE REV DETAILS

CAD NOTE:
DO NOT CHANGE TO 402 DESIGN NOTE:
OVERLAPPING FOOTPRINTS
STUFF L5BU & L6BU FOR EV & ERB CAD NOTE:
R30BU
2 1 AND EMPTY R30BU, R31BU, R28BU, R29BU
D 1A 0 ONLY FOR EV & ERB
PLACE CAP AS CLOSE AS POSSIBLE
EMPTY 603 TO USB CONNECTOR D
USB_P8_BP_DN L6BU VREG_USB_BP0_STACK
60 BI 2 3 USB_P8_R_DN BI 60
60 IN
90OHM
ACM2012 IND 1
C228BU
L6BU 470PF
60 BI
USB_P8_BP_DP 1 4 USB_P8_R_DP BI 60 PORT 8,9 - OC4
10%
50V
90OHM 2 X7R
ACM2012 IND CR5BU 402
TVS6V 6.0V
R31BU
2 1
1A
EMPTY
0
603
1 6 J12LB
2 X USB
2 5 5VDUAL 31 54 55 56 57 58 59 60 66 84 90 96 98 104 1 9
IN 112
60 USB_P9_R_DN 2
BI USB_P9_R_DP 3
60 BI
3 4 4 10
CAD NOTE:
OVERLAPPING FOOTPRINTS 60 VREG_USB_BP0_STACK 5 11
C DIO IN USB_P8_R_DN 6 C
60 BI
R28BU D16982-001 USB_P8_R_DP 7
1 2 60 BI 8 12
0 1A
603 EMPTY
CONN
L5BU BOM NOTE: E36183-001
36 USB_P9_DP 1 4 USB_P9_R_DP 60
BI BI
90OHM STUFF CONNECTOR BY DEFAULT
ACM2012 IND
L5BU 2USB/DP STACK
36 USB_P9_DN 2 3 USB_P9_R_DN 60
BI BI DESIGN NOTE:
90OHM
ACM2012 IND
J12LB DUAL USB STACK
R29BU
1 2 ON TOP OF DISPLAY PORT CONNECTOR
0 1A
603 EMPTY
B USB_P8_DN R255LB USB_WLAN_DN B

60 36 BI 1 2 BI 114
0 5%
402 EMPTY
R256LB
USB_P8_DP 1 2 USB_WLAN_DP
60 36 BI BI 114
0 5%
402 EMPTY
DESIGN NOTE:
USB ISOLATION FOR MINI PCIE CONN
R23BU USB_P8_BP_DN
USB_P8_DN 1 2
60 36 BI BI 60
0 5%
402 CH
2 R68BU 1 USB_OC_BACK0_N 36 R24BU USB_P8_BP_DP
OUT USB_P8_DP 1 2
15K 5% 60 36 BI BI 60
0 5%
402 CH
402 CH
2
R69BU DESIGN NOTE:
10K CAD NOTE:
5%
A CH PLACE AS CLOSE AS POSSIBLE USB ISOLATION FOR MINI PCIE CONN A
402
1 TO USB CONNECTOR CAD NOTE:
RT7BU
59 58 57 56 55
112
54 31
5VDUAL 1 2 VREG_USB_BP0_STACK
60 OVERLAP RES WITH R255LB & R23BU, R256LB & R24BU
104 98 96 90 84 66 60
IN OUT
THRMSTR 2 1 C259BU 1
R70BU 470.0UF C260BU
1.50 20% 470PF
10K 6.3V 10%
5% ELEC 50V
CH
2 RDL 2 X7R
603
VREG_USB MUST BE SPLIT 1
402
AMONGST ALL USB CHANNELS.
DO NOT DAISY CHAIN
[PAGE_TITLE=USB BACK PANNEL]
hc_cdb_mpi.sch_1.60
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

CAD NOTE:
D OVERLAPPING FOOTPRINTS
D
DESIGN NOTE:
STUFF L21BU & L22BU FOR EV & ERB

AND EMPTY R30BU, R31BU, R28BU, R29BU
ONLY FOR EV & ERB
L21BU
60OHM
IND 4PIN
USB3_TX3_C_DP 2 1 USB3_TX3_C_DN USB3_TX3_ESD_DN
58 BI BI 58 61 58 BI 3.3V
2
R134BU 1 R133BU U6BU
0 0 ESD3V3U4ULC
5% 5%
2 1 OUT 9
USB3_TX3_ESD_DP EMPTY EMPTY USB3_TX3_ESD_DN
61 58 402 3 4 402 58 61
BI BI
1
USB3_TX3_ESD_DP
61 58 2 OUT 8
IND BI
L22BU
60OHM
C IND 4PIN USB3_TX4_ESD_DN C
USB3_TX4_C_DP 61 58 4 OUT 7
58 2 1 USB3_TX4_C_DN 58 BI
BI BI
2
1 R136BU R135BU
0 0 61 58 USB3_TX4_ESD_DP 5 OUT 6
5% 5% BI
USB3_TX4_ESD_DP 2 EMPTY EMPTY USB3_TX4_ESD_DN
58 402 3 4 402 58 61 3
BI BI GND
1
61
IND
REV=1 DIO
L23BU
60OHM
IND 4PIN
USB3_RX3_DP 2 1 USB3_RX3_DN
36 BI BI 36
2
1 R138BU R137BU
0 0
5% 5%
USB3_RX3_ESD_DP 2 CH CH USB3_RX3_ESD_DN
58 402 3 4 402 58 61 USB3_RX4_ESD_DN
BI BI 3.3V
1
61 58 BI
61
B U7BU B
EMPTY
ESD3V3U4ULC
1 OUT 9
L24BU
60OHM
IND 4PIN USB3_RX4_ESD_DP 2 8
USB3_RX4_DP USB3_RX4_DN 61 58 BI OUT
36 2 1 36
BI BI
2
1 R140BU R139BU
0 0
5% 5%
USB3_RX4_ESD_DP 2 CH CH USB3_RX4_ESD_DN
58 402 3 4 402 58 61 USB3_RX3_ESD_DN 4 OUT 7
BI BI
1
61 58 BI
61
EMPTY
61 58 USB3_RX3_ESD_DP 5 OUT 6
BI
GND 3
REV=1 DIO
A A
[PAGE_TITLE=USB3 ESD DIODES]

hc_cdb_mpi.sch_1.61
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D
D
C C
B B
A A
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MODULE REV DETAILS

D
D
C C
VCC3
B B
R92BU
35 P_INTC_N 1 2 VCC3
OUT
R93BU 8.2K 5%
35 P_INTB_N 1 2 402 CH
OUT
8.2K 5%
R94BU
35 P_INTD_N 402 CH 1 2
OUT
8.2K 5%
R95BU
35 P_INTA_N 1 2 402 CH
OUT PCIEX1_SLOT6_PRSNT2_N 1 R50BU 2
8.2K 5% 35 24 OUT
402 CH 8.2K 5%
402 CH
R97BU
35 22 PCIEX1_SLOT4_PRSNT2_N 1 R51BU 2
P_INTF_N 1 2 OUT
79 35 OUT 8.2K 5%
8.2K 5% R98BU 402 CH
35 17 EXTTS_SNI_DRV0_PCH 402 CH 1 2 1 R52BU 2
OUT 35 23 OUT PCIEX1_SLOT5_PRSNT2_N
R99BU 8.2K 5%
1 2 402 CH 8.2K 5%
35 17 EXTTS_SNI_DRV1_PCH 402 CH
OUT
8.2K 5%
402 CH
A A
[PAGE_TITLE=PCH TERMINATION]
hc_cdb_mpi.sch_1.63
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D VCC
D
64 SW_ON_R_N 1 R71BU 2 SW_ON_N 38 50 100 113 116

IN OUT
33 5%
402 CH 1
VCC3 C261BU
1.0UF
20%
10V
2 Y5V 1 R74BU 2
R3BU 603
1 2 470 5%
402 CH
330 5%
402 EMPTY
1 R72BU 2
VCC J16BU
330 5% 2X5HDR_10
402 CH
VCC_HDLED_PWR 1 2 GPIO_GRN_BLNK_HDR_R
IN 64
64 IN HD_LED_G_N 3 4 GPIO_YLW_BLNK_HDR_R
IN 64
5 6 SW_ON_R_N 64
OUT
116 113 104 50 49 38 10 OUT FP_RST_N 7
9
8
C C
HDR
VCC
CP3BU CP3BU CP1BU CP1BU CP3BU CP3BU VCC

4 470PF 2 470PF 3 470PF 1 4 470PF 1 470PF 3 470PF
C265BU
20% 20% 20% 470PF 20% 20% 20% R76BU
50V 50V 50V 10% 50V 50V 50V 1 2 VREG_HD_ACT_LED_R
EMPTY EMPTY EMPTY 50V EMPTY EMPTY EMPTY
5 7 6 2 EMPTY 5 8 6 220 5%
SM SM SM 402 SM SM SM 402 CH 2
CR1BU
GREEN
LED
HD_LED_N 1
80 64 IN
B B
BOM NOTE: BOM=CORE_STDFNTPNL_E
DEFAULT EMPTY: STUFF 0 OHM RES (R206LB) FOR PCH PORT80 LED FEATURE (TDE EXPERIMENT)
PCH_PORT80_LED 1
R206LB
2 GPIO_GRN_BLNK_HDR_R
OUT 64
HD ACTIVITY LED
49 38 IN
0 5%
402 EMPTY
VCC
R48LB
1 2 CR6LB
HD_LED_G_N OUT 64
470 5%
402 CH DUAL LED
1 R77BU 2 1
80 IN GPIO_GRN_BLNK_HDR 80 IN GPIO_GRN_BLNK_BRD 2 1
0 5% R80BU
0
402 CH J18BU 5%
1X3HDR2 80 GPIO_YLW_BLNK_BRD 4 3
CH IN
1 1 C263BU 402
A 470PF 2 LED A
102276-304 3 10%
50V
GREEN/YELLOW
2 EMPTY HD_LED_N IN 64 80 DESIGN NOTE: C96838-007
HDR 603 CR6LB - S0: GREEN LIGHT
80 GPIO_YLW_BLNK_HDR 1 R78BU 2 S3: YELLOW LIGHT
IN
0
402
5%
CH
1 C264BU
1 R41BU CAD NOTE:
1K
470PF
10%
2
5%
CH
2 50V
EMPTY
SILKSCREEN ON BRD: S0 = GREEN LIGHT, S3 = YELLOW LIGHT
402 603
[PAGE_TITLE=STD FRONT PANEL HDR]

GPIO_YLW_BLNK_HDR_R
OUT 64
hc_cdb_mpi.sch_1.64
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

L_BKLTEN MODULE NAME REV DATE
65 37 IN 1 R52DP
100K
5% Q7DP
2 CH PMOSFET J3DP
402 VCC3
VCC3 1x44hdr_edp PU/PD TO AUX CHANNEL
1 R8DP 2 V3P3S_DP_EMB
D
3
VDD_EMB_S
S
D 1 V3.3S_DP_EMB
VCC 0 5% 2 V3.3S_DP_EMB D
1 3 DDSP_3_AUX_DP C11DP
2010 CH 1 R11DP C15DP 1 C16DP V3.3S_DP_EMB 1 2
G
4 43 BI
1 R9DP 2 1M 1 22UF 220UF V3.3S_DP_EMB 1 R21DP
1
C17DP 20% 20% 5 .1UF 10%
5%
6.3V 6.3V V3.3S_DP_EMB 10V 402 X5R 100K
2 CH 1000PF 2 6 GND 5%
0 5% 10% X5R TANT
2
1 R10DP 2
EMPTY
1 2010 EMPTY 402 50V 603 7343 7 GND 2 EMPTY
C14DP
EMB_VDDEN_N
2
5%
.1UF X7R 8 GND 402
10% 603 9 EMB_AUXP
10V R12DP GND OUT 65
2 65 EMB_HPD 10 EMB_HPD C12DP
X5R 1 2 EMB_VDDEN_D_N OUT 11 43 BI DDSP_3_AUX_DN 1 2
402 NC EMB_AUXN
402
.1UF 10%
1K
100K 5% 12 OUT 65
402 CH NC 10V 402 X5R 1 R22DP
13 GND 100K
EDP_D_TX3_DN 14 TXN3_C 5%
37 IN L_VDDEN 3 65 IN EDP_D_TX3_DP 15
65 IN TXP3_C 2 EMPTY
16 GND 402
Q6DP
1 R13DP 2
D EDP_D_TX2_DN 17
BSS138N 65 IN TXN2_C
CH
1%
+12V 65 EDP_D_TX2_DP 18 TXP2_C
IN 19 GND
1 65 EDP_D_TX1_DN 20 TXN1_C
FET IN EDP_D_TX1_DP 21
1 R57DP 2 VCC_EDP_BKLT
100K
402 G S 65 IN TXP1_C
65 22 GND HPD INVERSION FOR EDP
OUT 2 EDP_D_TX0_DN 23
0.002 1% 65 IN TXN0_C
1206 CH 65 IN EDP_D_TX0_DP 24 TXP0_C EMB_HPD
C 25 GND 65 IN C
EMB_AUXP 26 1 R25DP
65 BI EMB_AUXP 100K
VCC3 65 EMB_AUXN 27 EMB_AUXN 5%
VCC_EDP_AMOLED BI 28
1 R58DP 2 1 R16DP 2 65 IN VSS_EDP_AMOLED VSS_EDP_AMOLED 2 CH
65 IN V3P3S_DP_EMB_AUXPWR 29 V3.3S_EMB_AUXPWR 3 402
0.002 1% 30 NC
1206 EMPTY 0.002 1% 1 1 VCC
1206 CH C7DP C8DP 65 VCC_EDP_BKLT 31 VCC_EDP_BKLT D Q8DP
22UF 22UF IN 32
20% 20% 1 65 VCC IN VSS_EDP_AMOLED VSS_EDP_AMOLED BSS138N
6.3V 6.3V C9DP 33 GND
2 EMPTY 2 X5R 0.1UF 34 VCC
603 603 20%
16V TP_DBL_CLK 35 DBL_CLK 1 FET
2 Y5V 36 L_BRIGHTNESS G S
402 L_BKLTEN 37
VCC3 65 37 IN L_BKLT_EN 2
38 VCC_EDP_BKLT 1 R24DP
1 R17DP 2 VDD_ALS 39 VDD_ALS 100K
40 5%
0.002 1% GND 2 EMPTY DDSP_3_HPD2
1206 CH 103 17 SMB_CLK_THRM 41 SMB_THRM_CLK 43
1 BI SMB_DATA_THRM 42 402 OUT
C10DP 103 17 BI SMB_THRM_DATA
0.1UF 103 65 ALS_INTR_N 43 ALS_INTR#
20% IN TP_VDD_LPP 44
2 16V TP_VDD_LPP
Y5V
402
37 L_BKLTCTL 1 R18DP 2 1 OF 1
IN
B 0 5% REV=1 CONN DESIGN NOTE:
B
402 CH J6DP
R50DP 1X2HDR
DISP_UTIL 1 2 L_BRIGHTNESS 1
7 IN
0 5% 2 HPD PASS GATE - PREVENT DRIVING HPD IN POWER OFF
DDI3_TX3_DP C50DP 402 EMPTY
7 IN
1 2 EDP_D_TX3_DP
OUT 65 HDR
.1UF 10%
10V 402 X5R
DDI3_TX3_DN C51DP
1 2 EDP_D_TX3_DN
7 IN OUT 65
.1UF 10%
10V X5R
DDI3_TX2_DP 402 ADDITIONAL AMOLED POWER REQUIREMENTS
C52DP
7 1 2 EDP_D_TX2_DP 65
IN OUT J4DP VN_ELVSS_EDP_AMOLED
IN 65
1X3HDR
.1UF 10% 1
10V
X5R 2 VCC_EDP_AMOLED 65
DDI3_TX2_DN C53DP 402 EDP_D_TX2_DN
3
IN
1 2
7 IN OUT 65
HDR
VCC3 J5DP
.1UF 10% CAD NOTE:
10V 1X2HDR
DDI3_TX1_DP X5R C54DP 2 1
402 1 2 EDP_D_TX1_DP THE NET VSS_EDP_AMOLED NEED TO BE CONSIDERED AS POWER PLANE
7 IN OUT 65 1 R29DP
A .1UF 10% 8.2K HDR A
10V 5%
X5R VSS_EDP_AMOLED 1 R56DP 2 VN_ELVSS_EDP_AMOLED 2 CH
DDI3_TX1_DN 1
C55DP 402
2 EDP_D_TX1_DN
65 IN IN 65 402 ALS_INTR_N OUT 65 103
7 IN OUT 65 0 5%
402 EMPTY
.1UF 10% 1
10V
X5R EDP_D_TX0_DP R55DP
DDI3_TX0_DP 402 C56DP
1 2 0 STUFF UNSTUFF
7 IN OUT 65 1 R51DP
5%
.1UF 10% CH NORMAL EDP PANEL R55DP & R57DP R56DP & R58DP 0
10V 402 5%
X5R 2 AMOLED EDP PANEL R56DP & R58DP
R55DP & R57DP 2 EMPTY
DDI3_TX0_DN 402 EDP_D_TX0_DN 402
C57DP
1 2
7 IN OUT 65
.1UF 10%
10V [PAGE_TITLE= EDP]
X5R
402
hc_cdb_mpi.sch_1.65
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
J18LB D
MINI_PCIE C59768-003
V_1P5_PCH
115 114 106 51 44 41 40 37 36 IN 48 +1.5V USB_D+ 38 USB_MSATA_R_DP
BI 66
6 +1.5V USB_D- 36 USB_MSATA_R_DN
BI 66
V_3P3_MINI_PCIE
28 +1.5V
115 114 66 IN SMB_DATA 32 SMB_DATA_RESUME 20 22 23 24 25 38 81 114
C152LB IN
SATAHDR_TX4_DP .1UF X5R
1 C2LB
41 +3.3VAUX SMB_CLK 30 SMB_CLK_RESUME
IN 20 22 23 24 25 38 81 114
37 OUT 0.1UF
20% 16V
39 +3.3VAUX PERST* 22 PLTRST_N
IN 35 67 77 79 82 103 114
2
W_DISABLE_MSATA R146LB
1
10% 402 10V Y5V

52 +3.3VAUX W_DISABLE* 20
1 2 V_3P3_MINI_PCIE
2 402
24 +3.3VAUX 10K 5%
IN 66 114 115
C153LB 2 +3.3VAUX UIM_VPP 16
X5R 402 EMPTY
37 OUT SATAHDR_TX4_DN .1UF UIM_RESET 14
PETP0 UIM_CLK
2
SATAHDR_TX4_R_DP 33 12
1
10% 402 10V SATAHDR_TX4_R_DN 31 PETN0 UIM_DATA 10

R155LB SATAHDR_RX4_R_DN 25 PERP0 UIM_PWR 8
37 SATAHDR_RX4_DN 1 2
IN 0 5%
SATAHDR_RX4_R_DP 23 PERN0
402 CH 13 REFCLK+
R156LB
11 REFCLK-
37 SATAHDR_RX4_DP 1 2
7 CLKREQ*
IN 0 5%
1 WAKE* SATA4GP
C 402 CH GND 43
OUT 37 49 116 V_3P3_MINI_PCIE C
44 IN CK_MSATA_100M_DP 46 LED_WPAN* GND 37 115 114 66 IN
44 IN CK_MSATA_100M_DN 44 LED_WLAN* GND 35
114 66 IN WLAN_CLKREQ 42 LED_WWAN* GND 29
1
38 25 24 23 22 20 OUT WAKE_N GND 27
66 114 49 WPAN_LED_HDR_2 TP_COEX_2 5 COEX2 GND 21 R147LB
IN 10K
66 WLAN_LED_HDR_2 TP_COEX_1 3 COEX1 GND 15
IN GND 9 5%
TP_BT_RF_KILL_2 51 RESERVED GND 50 CH
TP_DAS 49 RESERVED GND 40 402
2
TP_VENDOR_SPECIFIC_1 47 RESERVED GND 34
TP_VENDOR_SPECIFIC_2 45 RESERVED GND 26 WLAN_CLKREQ
OUT 66 114
19 RESERVED/UIM_C4 GND 18
17 RESERVED/UIM_C8 GND 4
R150LB
53 MECH_53 1 2
54 MECH_54 0 1A
55 MECH_55 603 CH
56 MECH_56
L1LB
USB_MSATA_DN 4 1 USB_MSATA_R_DN
66 BI BI 66
REV=1 CONN 90OHM
B ACM2012 EMPTY
B
L1LB
66 USB_MSATA_DP 3 2 USB_MSATA_R_DP 66
BI BI
90OHM
ACM2012 EMPTY
R151LB 6.0V CR1LB
TVS6V
R135LB 1 2
USB_P13_DN USB_MSATA_DN
66 36 BI 1 2 BI 66 0 1A
0 5% 603 CH
6 1
402 EMPTY
CAD NOTE:
R138LB USB_MSATA_DP
66 36 USB_P13_DP 1 2 66 DO NOT CHANGE TO 402 V_3P3_MINI_PCIE
BI 0 5%
BI OVERLAPPING FOOTPRINTS 115 114 66 IN 5 2
402 EMPTY
4 3
DESIGN NOTE:
USB ISOLATION FOR MINI PCIE CONN

EMPTY
R175BU USB_P13_R_DN
USB_P13_DN 1 2
66 36 BI 0 5%
BI 54 J22LB
402 CH R140LB 1X2HDR
115 114 66
V_3P3_MINI_PCIE 1 2 1 2 WLAN_LED_HDR_2 66
R178BU USB_P13_R_DP IN WLAN_LED_HDR_J18LB
OUT
A USB_P13_DP 1 2 220 5% A
66 36 BI BI 54 D51601-002
0 5% 402 CH HDR J29BU
402 CH PCIE_MINI_CLIP
90 84 60 59 58 57 56 55 54 31 5VDUAL
DESIGN NOTE: 112 104 98 96
IN
1
USB ISOLATION FOR MINI PCIE CONN J21LB 2
NC
NC
R141LB 1X2HDR
C72BU 1 2
CAD NOTE:
1 2 WPAN_LED_HDR_J21LB 1 2 WPAN_LED_HDR_2 OUT 66
REV=1.0
HDR
220 5%
0.1UF 20%
OVERLAP RES WITH R135LB & R175BU, R138LB & R178BU 16V 402 CH HDR
Y5V
402
[PAGE_TITLE=MSATA] BPAGE DRAWING

hc_cdb_mpi.sch_1.66
2 1
8 7 6 5 4 3 2 1
DESIGN NOTE: MODULE REV DETAILS

DESIGN NOTE: RENAME PLTRST_LAN_N TO PLTRST_N FOR CRB MODULE NAME REV DATE
R16LN DEFENSIVE DESIGN
U1LN
G29290-002 INTEL CLARKVILLE
94 68 67 V_3P3_LAN 1 R16LN 2 CLKREQ_N 48 CLK_REQN REV=1 MDI_PLUS_0 13 LAN_MDI0_DP 68
IN LAN_MDI0_DN OUT
10K 5% 67 IN PLTRST_LAN_N 36 PE_RSTN MDI_MINUS_0 14
OUT 68
805 CH
D 44 CK_GLAN_DP 44 PE_CLKP MDI_PLUS_1 17 LAN_MDI1_DP 68
IN CK_GLAN_DN LAN_MDI1_DN OUT
MDI
PCIE
44 IN 45 PE_CLKN MDI_MINUS_1 18
OUT 68 D
67 HSI3_C_DP 38 PETP MDI_PLUS_2 20 LAN_MDI2_DP 68
OUT HSI3_C_DN LAN_MDI2_DN OUT
R295EV 67 OUT 39 PETN MDI_MINUS_2 21
OUT 68
114 103 82 79 77 66 35 PLTRST_N 2 1 PLTRST_LAN_N 67
IN 0 5% OUT HSO3_C_DP LAN_MDI3_DP
402 CH 67 IN 41 PERP MDI_PLUS_3 23
OUT 68
67 HSO3_C_DN 42 PERN MDI_MINUS_3 24 LAN_MDI3_DN 68
IN OUT
R115CV
SMLINK0_CLK 1 2
SMBUS
49 38 18 OUT
0 5% V_3P3_LAN
402 CH VDD3P3_IN 5
IN 67 68 94
R159CV SMLINK0_CLK_R 28 SMB_CLK VDD3P3_OUT 4
49 38 18 SMLINK0_DATA 1 2 SMLINK0_DATA_R 31 SMB_DATA
OUT RSVD1
0 5% RSVD1_VCCP3P3 1
OUT 67
BOM NOTE:
402 CH LANWAKE_N 2 LANWAKE_R_N
OUT 67
SVR_EN 6 SVR_EN 67 V_3P3_LAN 67 68
LAN_DISABLE_R_N IN IN 94
STUFF R5LN FOR LPT INTERPOSER, EMPTY FOR LPT 3
LAN_DISABLE_N 1 R11LN
0
R5LN 1A
V_3P3_LAN 1 2 VDD3P3 15
LED
94 68 67 IN 2 CH
10K 5% 68 OUT LAN_LED0 26 LED0 VDD3P3 19 C21LN 603
402 EMPTY 68 OUT LAN_LED1 27 LED1 VDD3P3 29 V_3P3_C 1 2
68 LAN_LED2 25 LED2 1UF 10%
C R4LN OUT 6.3V C
LAN_DISABLE_N 1 2 X5R
38 IN 402
VDD0P9 47
0 5% VDD0P9 46
JTAG
402 CH
1 R73LN IN TPEV_LAN_JTDI 32 JTAG_TDI VDD0P9 37
10K TPEV_LAN_JTDO 34 JTAG_TDO
5% OUT TPEV_LAN_JTMS
2 EMPTY 67 IN 33 JTAG_TMS VDD0P9 43 V_0P9_LAN
67 TPEV_LAN_JTCK 35 JTAG_TCK
402 IN 1
1 R38LN 2 LAN_TESTEN VDD0P9 11
1 C16LN
30 TEST_EN VDD0P9 8 C1LN 1
C2LN 10UF
.1UF 10%
1K 5% VDD0P9 40
10%
.1UF
10% 10V
402 CH VDD0P9 22
2 10V 10V 2 X5R
VDD0P9 16 EMPTY
402
2 EMPTY 805
C44LB R29LB 402
HSO3_DP 1 2 HSO3_R_DP HSO3_C_DP 4.7UH
36 IN OUT 67
67 LAN_XTL_DN 9 XTAL_OUT 1 2
0OHM OUT LAN_XTL_DP
.1UF 10% SM 67 IN 10 XTAL_IN IND 1 1
16V 12 RBIAS C10LN C15LN C5LN C7LN
X7R C45LB R60LB LAN_RBIAS_R2GND CTRL0P9 7 L2LN 10UF .1UF .1UF .1UF
36 IN HSO3_DN 402 1 2 HSO3_R_DN HSO3_C_DN
OUT 67 LAN_1P0_CTRL
10% 10% 10% 10%
10V 10V 10V 10V
.1UF 10% 0OHM VSS_EPAD 49 2 X5R 2 X5R EMPTY EMPTY
16V SM 1 805 402 402 402
X7R R50LN
402 CAD NOTE:
R81LB C98LB 3.01K
IC
36 OUT HSI3_DP 1 2 HSI3_R_DP 1 2 HSI3_C_DP
IN 67 PLACE R50LN NEAR U1LN 1%
B CH DESIGN NOTE:
B
0OHM .1UF 10%
SM 16V 402
X7R 2 SMBUS ADD IS OXE0
402 94 68 67 IN V_3P3_LAN
R84LB C99LB
36 HSI3_DN 1 2 HSI3_R_DN 1 2 HSI3_C_DN 67
OUT IN 1 1
0OHM C6LN C13LN
SM .1UF 10% 22.000UF .1UF
16V 20% 10%
X7R 94 68 67 IN V_3P3_LAN 6.3V 10V
DESIGN NOTE: 402 2 X5R 2 X5R
805 402
GROUND ISOLATION RESISTOR R29LB, R60LB, R81LB AND R84LB PLACE CLOSE TO RX
1 R58LN 1 R69LN
CAD NOTE:
10K 10K
5% 5% PLACE C13LN AND C6LN NEAR VDD PINS
2 EMPTY 2 EMPTY
402 402
67 OUT TPEV_LAN_JTMS LAN CRYSTAL LAN_XTL_DP 67

OUT
TPEV_LAN_JTCK
67 OUT
R8LN
2
67 38 OUT LANWAKE_N 1 2 LANWAKE_R_N
IN 67
94 68 67 IN V_3P3_LAN C22LN
0 5% 22PF
A DESIGN NOTE:
402 CH 1 Y1LN 5%
50V A
25.000MHZ COG
RENAME R8LN.2 TO LANWAKE_R_N SM 402
1
REMOVE & SHORT 2 PIN OF R147CV FOR CRB, AIO & DOE SKU XTAL
V_3P3_LAN
67 68 94
2 A93545-056
R9LN
IN 1 R71LN 1 R72LN
1 4.7K 4.7K C23LN
4.7K 5% 5% LAN_XTL_DN_M3LN 1 2 DESIGN NOTE:
5%
2 CH 2 EMPTY PLEASE CREATE A IPN FOR Y2LN
SVR_EN
2 EMPTY
402 402 402 22PF 5%
50V
67 OUT 1 M3LN 2
67 IN LAN_XTL_DN 402
COG CAD NOTE:
67 RSVD1
1 R10LN OUT 0 5%
102 0 LANWAKE_R_N 402 CH OVERLAP FOOTPRINT FOR Y1LN & Y2LN
94 89 67 OUT
78 77 V_3P3_A R13LN 5%
32 30 1 2 LANWAKE_N 38 67 2 CH
49 41
IN OUT 402
82
100
81
95
4.7K
402
5%
CH [PAGE_TITLE=LAN CONTROLLER]
DESIGN NOTE: BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
ONCE LPT PCH POLICY BIT CONFIRM WORKING, REMOVE 4.7KOHM R13LN PU TO V_3P3_A CONNECTION. hc_cdb_mpi.sch_1.67
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
LAN CONNECTOR 1000

JA1LN
DEFAULT GIGABIT GBE_MAGJACK3_10
67 BI LAN_MDI0_DP 10 TD0+
MAGJACK BI-COLOR SPEED LED 67 BI LAN_MDI0_DN 11 TD0- VCT 9 VCT_PIN9
LAN_MDI1_DP 12 18 1 C14LN
67 BI TD1+ SGND
10 MBPS OFF 67 BI LAN_MDI1_DN 13 TD1- .1UF
10%
10V 1
67 LAN_MDI2_DP 14 TD2+
2 X5R C27LN
C BI 15 402 1UF C
100 MBPS GREEN 67 BI LAN_MDI2_DN TD2- 10%
16V
67 LAN_MDI3_DP 16 TD3+
2 X5R
BI 17 603
1000 MBPS YELLOW 67 BI LAN_MDI3_DN TD3-
IO CAD NOTE:
USB STACK GND=23..30
C73572-001 PLACE CAP/RES NEAR MAGJACK_PIN9
JA1LN
2 X USB
68 59 VREG_USB_BP_MJ
IN 1 1000
59 USB_P11_R_DN 2
BI USB_P11_R_DP 3
59 BI 4
68 59 VREG_USB_BP_MJ
IN
5
59 USB_P10_R_DN 6 IO
BI USB_P10_R_DP 7
59 BI 8
B DESIGN NOTE:
B
MAGJACK USB PORTS PINS ARE TRANSPOSE
WITH DOUBLE STACK USB PORT
MAGJACK LED
1000
JA1LN
GRN_LED R23LN
V_3P3_LAN 20 19 LAN_LED0_R 1 2 LAN_LED0
94 67 IN OUT 67
A 330 5% A
1 IO 1 402 CH
C29LN C28LN
470PF 470PF
10% 1000 10%
50V 50V
2 X7R JA1LN 2 X7R
402 402
GRN_LED
R25LN
67 IN LAN_LED1 22 21 LAN_LED2_R 1 2 LAN_LED2 BI 67
330 5%
1 IO 1 402 CH
C26LN YLW_LED
C25LN DESIGN NOTE:
470PF 470PF
10% 10%
50V 50V
2 X7R 2 X7R LED SERIES R INTEGRATED IN MAGJACK. BACKUP.
402 402
[PAGE_TITLE=LAN:MAGJACK]
hc_cdb_mpi.sch_1.68
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.05.00 9-15-06
70 IN AUD_CODEC_VREF
2
C4AU 1 U1AU SURR REAR L/R LINE IN / SURR SIDE
CAD NOTE: PLACE R14AU NEAR AUDIO CODEC 5% 10PF
ALC889 PORT F PORT C
D 50V REV=1
COG 27 VREF PORT_A_L 39 AUD_PORT_A_L 74 CEN / LFE D
402 BI FRONT / LINE OUT
PORT_A_R 41 AUD_PORT_A_R 74
PORT G PORT D
AUD_LINK_BCLK 6 BI
R14AU 49 IN BCLK
70 AUD_LINK_SDI2_CODEC 1 2 AUD_LINK_SDI2 8 SDATA_IN PORT_B_L 21 AUD_PORT_B_L 74
S/PDIFF OUT MIC IN
OUT BI PORT F/E
33 5%
49 IN 402 CH AUD_LINK_SDO 5 SDATA_OUT PORT_B_R 22 AUD_PORT_B_R BI 74
49 AUD_LINK_SYNC 10 SYNC FACING BACK PANEL

IN 23 AUD_PORT_C_L
1 PORT_C_L BI 72
C98AU 69 IN AUD_LINK_RST_N 11 RESET*
10PF PORT_C_R 24 AUD_PORT_C_R 72
HEADPHONE PORT A REALTEK
5% BI
50V
2 MIC PORT B
EMPTY 70 IN AUD_PC_BEEP 12 BEEP DESIGN NOTE:
402 35 AUD_PORT_D_L
PORT_D_L BI 72
AZALIA:
TP_AUD_CD_IN_L 18 36 AUD_PORT_D_R REALTEK- ALC885/889 (5 STACKS)
CD_L PORT_D_R BI 72
TP_AUD_CD_GND 19 CD_GND
PORT_E_L 14 AUD_PORT_E_L BI 72
TP_AUD_CD_IN_R 20 CD_R
C PORT_E_R 15 AUD_PORT_E_R BI 72 C
TP_AUD_SPDIF_IN 47 SPDIFI/EAPD
PORT_F_L 16 AUD_PORT_F_L BI 73
71 OUT AUD_SPDIF_OUT 48 SPDIFO/ADAT
PORT_F_R 17 AUD_PORT_F_R BI 73
74 72 70 OUT AUD_SENSE_A 13 SENSE_A

PORT_G_L 43 AUD_PORT_G_L BI 73
73 72 70 OUT AUD_SENSE_B 34 SENSE_B
PORT_G_R 44 AUD_PORT_G_R BI 73
PORT_H_L 45 TP_AUD_PORT_H_L
PORT_H_R 46 TP_AUD_PORT_H_R
DACREF 37 AUD_VREF_37
28 AUD_VREF_28 1
PORT_B_VREFO_L OUT 75 C2AU
.1UF
10%
PORT_C_VREFO 29 TP_AUD_VREF_29 10V
B X5R 2 B
402
PORT_B_VREFO_R 32 TP_AUD_VREF_32
AUD_VREF_31
AUD
PORT_E_VREFO 31 75
OUT
PORT_F_VREFO 30 TP_AUD_VREF_30
GPIO2 33 AUD_FILTER_33 OUT 70
V_AUD_ANALOG JDREF 40 AUD_DVDD_CORE_40

76 70 25 AVDD1
IN
VCC3 38 AVDD2 AVSS1 26
M17AU TP_AUD_GPIO1
1 2 3 GPIO1 AVSS2 42 1 R149AU
MULTI AUD 20K
V_AUD_DIGITAL 1 2 TP_AUD_VOL_2 1%
CH 603 DVDD SPDIFO2/GPIO0/DMIC_CLK 2 CH
402
9 DVDD_IO DVSS 4
1 OF 1 DVSS_IO 7
AUD_DVDD_IO
R75AU
2 1 R156AU 49 AUD_LINK_RST_CDC 1 2 AUD_LINK_RST_N 69
C7AU 2 2 2 0 IC IN OUT
AUD
10UF C5AU C3AU C110AU 5% 0 5%
A 20% .1UF .1UF 10UF 2 CH 402 CH A
6.3V 10% 10% 20%
1 X5R 16V 16V 6.3V 402
805 1 X7R 1 X7R 1 X5R
603 603 805
CAD NOTE:
PLACE NEXT
TO PIN 1 1 R157AU
CAD NOTE: 4.7K
5%
PLACE NEXT TO 2 EMPTY
PINS 9 402
DESIGN NOTE:
R157AU DESIGN EXPERIMENT
ALWAYS EMPTY [PAGE_TITLE=AUDIO CODEC]
hc_cdb_mpi.sch_1.69
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.05.00 9-15-06
JACK DETECT NETWORK
D 76 70 69 V_AUD_ANALOG
IN D
1 R9AU
5.11K
1%
2 EMPTY
402
AUD_SENSE_B OUT 69 72 73
CAD NOTE: 1
AUD_CODEC_VREF OUT 69 C10AU
PLACE NEAR PIN 34 1000PF
C20AU
1 C19AU
1 10%
50V
.1UF 10.0UF 2 EMPTY
10% 20% 402
10V 6.3V
X5R 2 X5R 2 VREF SUPPLY
402 805 AUD
CAD NOTE:
PLACE NEAR PIN 27
70 69 IN V_AUD_ANALOG
76
AUD 1 R11AU
5.11K
1%
C 2 EMPTY C
CAD NOTE: CAD NOTE: 402
PLACE NEXT TO PIN 25 PLACE NEXT TO PIN 38
V_AUD_ANALOG OUT 69 70 76
AUD_SENSE_A OUT 69 72 74
CAD NOTE: 1
1 1 1 1 C15AU
C13AU C11AU C16AU C17AU PLACE NEAR PIN 13 1000PF
10%
10UF .1UF 10UF .1UF
50V
20%
6.3V
10%
10V
20%
6.3V
10%
10V
2 EMPTY
2 X5R 2 X5R 2 X5R 2 X5R 402
805 402 805 402
AUD
R13AU
AUD C18AU
50 38 IN SPKR 1 2 AUD_PC_BEEP_PN1 1 2 AUD_PC_BEEP
OUT 69
10K 5% 0.1UF 20%
1 R12AU 2
B SUPPLY DECOUPLING 402 CH
100
5%
C8AU
.01UF
10%
16V
Y5V
402
B
2 CH 1 25V
402 EMPTY
402
CAD NOTE: DUAL FOOTPRINT FOR R60AU & R61AU
AUD AUD
DESIGN NOTE:
EMPTY R60AU & STUFF R61AU IF USE SV AZALIA CARD
PC BEEP
STUFF R60AU & EMPTY R61AU IF NOT USE SV AZALIA CARD
AUD_FILTER_33 69
OUT
R60AU
1 2 AUD_LINK_SDI2_CODEC 69
IN
0 5% 1
402 CH C9AU
10UF
R61AU 20% CAD NOTE:
A 38 AUD_LINK_SDI2_R 1 2 AUD_LINK_SDI2_HDR_R 74 2 6.3V
A
OUT IN EMPTY PLACE CIRCUIT NEXT TO PIN 33
0 5% 805
402 EMPTY
AUD
[PAGE_TITLE=AUDIO DCPL, CIRCUITS & JACK SENSE]

hc_cdb_mpi.sch_1.70
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.05.00 9-15-06
D
D
BOM NOTE:
DEFAULT:5 STACK STUFF.
OPTIONAL:3 STACK.
BOM NOTE:
DEFAULT: ALC885/888: 10 OHM
C C
CAD NOTE: VCC

PLACE NEXT TO U1AU PIN 48
JA5AU
DFP_AUD5STK
69 AUD_SPDIF_OUT 1 R88AU 2 AUD_SPDIF_VIN F3 VIN
IN
10 5%
402 CH F2 VCC
F1 GND
1 C76AU
CONN
470PF
10% NC=40,41
2 50V GND=36,37,38,39,42,43
X7R
402
B B
1 C84AU
R108AU
1 2 .1UF
10%
10K 5% 10V
402 EMPTY 2 EMPTY
402
A A
[PAGE_TITLE=AUDIO SPDIF]

hc_cdb_mpi.sch_1.71
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1

DEFAULT: STUFF JA5AU WITH C94525-003 5-STACK MODULE NAME REV DATE
OPTIONAL: STUFF JA6AU WITH C73570-001 3-STACK
BL AUDIO 0.05.00 9-15-06
JA5AU
DFP_AUD5STK C94525-003
32
D
R45AU
AUD_JACK_33 33 TOP D
1 2 34
PORT C
AUD_JACK_34
AUD
10K 1%
BOM NOTE: CH 35
402
FB OPTION: 0.2AMP (693286-014), 0603
RES OPTION: 0 OHM (108506-004), 0603
FB OPTION: DEFAULT
1
600
0.2A
R93AU CONN
1 2 AUD_SENSE_A
OUT 69 70 72 74
BROAD
AUD_PORT_LINE_L_C M7AU 0 5%
C102AU 402 CH
69 BI AUD_PORT_C_L 1 2
BI 72 72 BI AUD_PORT_LINE_L_C 1 2 AUD_L_LINEOUT_C
MULTI
4.7UF 20.0%
16V FB C41AU
ALUM 2 1 JA6AU
TH 600
0.2A 470PF 10% 3 STACK AUDIOJACK_SW
BROAD 50V 32
M4AU X7R
C103AU AUD_PORT_LINE_R_C AUD 402
69 BI AUD_PORT_C_R
BI 72 72 BI AUD_PORT_LINE_R_C 1 2 AUD_R_LINEOUT_C 35
MULTI
4.7UF 20.0% 33
16V FB
ALUM R43AU C34AU
TH 2 1 34
1 2
C 470PF 10%
C
20K 5% 1
402 EMPTY 50V C1AU 1
X7R .1UF
AUD 402 10%
R36AU 16V
EMPTY
1 2 EMPTY 2
402
20K 5% AUD
402 EMPTY
JA5AU
AUD DFP_AUD5STK
C37AU C94525-003
AUD 600 22
69 AUD_PORT_D_L 1 2 AUD_PORT_LINE_L_D 72 0.2A
BI BI 72
AUD_SENSE_A
BROAD 69 23
M6AU OUT
100UF 20% 70
74
R46AU MIDDLE
6.3V 72 BI AUD_PORT_LINE_L_D 1 2 AUD_L_LINEOUT_D 1 2 AUD_JACK_24 24
MULTI AUD
ALUM
RDL
C36AU
FB 2
C40AU
1
5.11K
402
1%
CH 25 PORT D
100UF 600
470PF 10% 1
69 BI AUD_PORT_D_R AUD_PORT_LINE_R_D
BI 72 0.2A 50V
1 2 BROAD X7R CONN
6.3V 20% M3AU 402
ALUM
72 AUD_PORT_LINE_R_D 1 2 AUD_R_LINEOUT_D AUD
RDL BI JA6AU
MULTI
B FB 3 STACK AUDIOJACK_SW B
C44AU
2 1 22
R42AU
1 2 470PF 10% 25
20K 5% 50V
X7R
402 CH 402
AUD 23
R48AU AUD 24
1 2
20K 5% 1
402 CH EMPTY
73 70 69 OUT JA5AU
600 DFP_AUD5STK
AUD 0.2A
C94525-003
2
BROAD
R35AU M8AU
C104AU AUD_SENSE_B 3
69 BI AUD_PORT_E_L 1 2 AUD_PORT_EB_L
1 2 AUD_PORT_LINE_L_MIC
BI 72 75 75 72 BI AUD_PORT_LINE_L_MIC 1 2 AUD_L_MIC
5.10 5%
MULTI BOTTOM
4.7UF 20.0% AUD_JACK_4 4
402 CH 16V FB C43AU
ALUM
TH 600
0.2A
2
470PF 10%
1
5 PORT E
BROAD 50V 1
M5AU X7R
402
A 75 72 AUD_PORT_LINE_R_MIC 1 2 AUD_R_MIC AUD CONN A
R34AU C105AU BI MULTI
AUD_PORT_E_R 1 2 1 2 AUD_PORT_LINE_R_MIC
69 BI AUD_PORT_EB_R
BI 72 75 C38AU
FB 2 1
5.10 5% 4.7UF 20.0%
402 CH 16V R44AU 470PF 10% JA6AU
ALUM 1 2 50V AUD
TH
20K 5% X7R 3 STACK AUDIOJACK_SW
402 EMPTY AUD 402 2
R47AU 5
R37AU 1 2
1 2 AUD
39.2K 1% 3
20K 5% 402 CH
402 EMPTY
4
AUD 1 EMPTY
[PAGE_TITLE=AUDIO JACKS] hc_cdb_mpi.sch_1.72
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
STUFF THIS PAGE FOR 5-STACK BOM NOTE: BL AUDIO 0.05.00 9-15-06
FB OPTION: 0.2AMP (693286-014), 0603
RES OPTION: 0 OHM (108506-004), 0603
DEFAULT: FB OPTION
BOM NOTE:
D 5STACK:STUFF C106AU,C107AU
D
600 JA5AU
0.2A
BROAD DFP_AUD5STK C94525-003
D1
C106AU
M12AU
69 BI AUD_PORT_F_L 1 2 AUD_PORT_REAR_L 1 2 AUD_PORT_REAR_L_JACK 73 72 70 69 OUT AUD_SENSE_B D2
MULTI R62AU
4.7UF 20.0% 1 2 AUD_JACK_D3 D3
16V FB C54AU AUD
ALUM
TH
600
0.2A
1
470PF 10%
2
20K
402
1%
CH D4 PORT F
BROAD 50V TOP
X7R G1
C107AU
M14AU AUD 402
69 AUD_PORT_F_R 1 2 AUD_PORT_REAR_R 1 2 AUD_PORT_REAR_R_JACK CONN
BI MULTI
4.7UF 20.0% C51AU
16V FB 1 2
C ALUM R66AU
C
TH 1 2 470PF 10%
20K 5% 50V
X7R
402 CH 402
R64AU
AUD 1 2
20K 5%
402 CH
AUD AUD
B B
BOM NOTE:
5STACK:STUFF C108AU,C109AU
600 JA5AU
0.2A DFP_AUD5STK
BROAD
C94525-003
E1
C108AU
M11AU
AUD_SENSE_B E2
69 BI AUD_PORT_G_L 1 2 AUD_PORT_CNT_L 1 2 AUD_PORT_CNT_L_JACK 73 72 70 69 OUT
MULTI R67AU
4.7UF 20.0% C53AU 1 2 AUD_JACK_E3 E3
16V 600
FB 1 2 AUD
ALUM 10K 1%
A
TH 0.2A
BROAD
470PF 10%
50V
402 CH E4
PORT G A
M13AU
AUD X7R
402
G1 BOTTOM
C109AU
69 AUD_PORT_G_R AUD_PORT_LFE_R 1 2 AUD_PORT_LFE_R_JACK CONN
BI MULTI
4.7UF 20.0% C56AU
16V FB 1 2
ALUM R114AU
TH 1 2 470PF 10%
20K 5% 50V
X7R
402 CH 402
R130AU
AUD 1 2
20K 5% AUD
402 CH
[PAGE_TITLE=AUDIO JACK (BLACK ORANGE]
AUD BPAGE DRAWING
hc_cdb_mpi.sch_1.73
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.05.00 9-15-06
CAD NOTE:
PLACE R81AU NEAR R132LB WITHIN 500MILS
PLACE R80AU <2 INCH TO R104LB
PLACE R72AU NEAR R122LB WITHIN 500MILS
D PLACE R69AU NEAR R133LB WITHIN 500MILS
D
R80AU
1 2 116
C100AU 102 98 95 94 93
CAD NOTE: 2 1 77 52 51 49 41 36 35 18 V_3P3_STBY\G
15 5% IN
402 CH EMI CAP
92 91 83 82 81 80 79
115 110 106
78
104
VCC3 +12V
10PF 5%
PLACE NEXT TO PIN 1 50V
R69AU COG
1 2 402 J7AU
15 5% 2X8HDR12
49 38 IN AUD_LINK_BCLK_R104LB 402 CH AUD_LINK_BCLK_HDR 1 2
49 38 IN
AUD_LINK_RST_R133LB_N
R81AU AUD_LINK_RST_HDR 3 4
AUD_LINK_SYNC_R132LB 1 2 AUD_LINK_SYNC_HDR 5 6
49 38 IN
15 5% AUD_LINK_SDO_HDR 7 8
402 CH AUD_LINK_SDIO_J7AU_PIN9 9 10
AUD_LINK_SDO_R122LB 1 R72AU 2 AUD_LINK_SDI1_HDR 11
52 49 38 IN AUD_LINK_SDI3_HDR 13 14
15 5% AUD_LINK_SDI2_HDR 15 16
402 CH
38 AUD_LINK_SDI1_R 1 R76AU 2 HDR

C OUT 1 R1AU 2 AUD_SENSE_A C
33 5% A91836-050 OUT 69 70 72
402 CH 47 5%
402 CH
38 AUD_LINK_SDI3_R 1 R77AU 2 R4AU
OUT 1 2 AUD_LINK_SDI0
OUT 38 2
33 5% C57AU
402 CH 33 5% 1000PF
402 CH 10%
50V
1 R78AU 2 X7R 1
70 OUT AUD_LINK_SDI2_HDR_R 402
33 5%
402 CH
J6AU AUD R94AU
2X5HDR_8 AUD_FP_DETECT_HDR
2 1 FP_AUD_DETECT 38 49
OUT
75 74 AUD_PORT_B_L_HDR AUD 1 2 0 5%
BI AUD_PORT_B_R_HDR 3 4 402 CH
75 74 BI
74 AUD_PORT_A_R_HDR 5 6 AUD_FP_SENSE_MIC
BI AUD_SENSE_A_FP 7
74 AUD_PORT_A_L_HDR 9 10 AUD_FP_SENSE_HP
BI
HDR
1 1
R95AU R96AU
B 39.2K 20K B
1% 1%
R89AU C89AU CH CH
AUD_PORT_B_R 1 2 AUD_PORT_B_R_C_HDR 1 2 AUD_PORT_B_R_HDR 402 402
69 BI BI 74 75
2 2 2
0 5% 100UF 20%
402 CH 6.3V 2 2 2 R143AU
ALUM R145AU R144AU 20K
TH R146AU 5%
R85AU 20K 20K
C92AU 20K 5% 5% EMPTY AUD AUD
69 AUD_PORT_B_L 1 2 AUD_PORT_B_L_C_HDR 1 2 AUD_PORT_B_L_HDR 74 75 5%
BI BI CH EMPTY 402
0 5% 100UF 20%
CH 402 402 1
402 CH 6.3V 402 1 1
ALUM 1
TH
BOM NOTE:
AUD AUD AUD AUD
USE 220UF FOR DOLBY SKU'S ONLY
ELSE USE 100UF
2 2 2 2 2 2 2
C60AU C65AU C58AU C59AU C66AU C64AU C61AU
R90AU C93AU .01UF .01UF 220PF 220PF 220PF
69 AUD_PORT_A_R 1 2 AUD_PORT_A_R_C_HDR 1 2 AUD_PORT_A_R_HDR 74 10% 10% 10% 10% 220PF 220PF 10%
BI BI 25V 25V 50V 50V 10% 10% 50V
0 5% 100UF 20%
1 X7R 1 X7R 1 X7R 1 X7R 1 50V
1 50V 1 EMPTY
402 CH 402 402 402 402 X7R EMPTY 402
A 6.3V 402 402 A
ALUM
TH AUD
AUD AUD AUD AUD AUD
AUD
CAD NOTE:
PLACE 220PF CAPS CLOSE TO 2X5 AUDIO FRONT PANEL CONNECTOR

R86AU C94AU
69 AUD_PORT_A_L 1 2 AUD_PORT_A_L_C_HDR 1 2 AUD_PORT_A_L_HDR 74
BI BI
0 5% 100UF 20%
402 CH 6.3V
ALUM [PAGE_TITLE=AUDIO FP HEADERS & HDA HEADER]
TH

hc_cdb_mpi.sch_1.74
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

REAR MIC BIAS BL AUDIO 0.05.00 9-15-06
D
FRONT MIC BIAS D
R121AU
AUD_MIC2_DIODE 1 2 AUD_PORT_LINE_R_MIC
OUT 72
2.2K 5%
402 CH
CR1AU
1
R113AU
69 IN AUD_VREF_31 1 2 AUD_MIC1_DIODE_MIC_BIAS 6
1K 5%
402 CH 2
BAW56S
SOT363
DIO
CR1AU
R110AU
2
AUD_PORT_B_R_HDR
4 1 2 OUT 74
C80AU AUD_VREF_28 R107AU
AUD_VREF_FP_MIC_R
2.2K 5%
4.7UF R117AU 69 1 2 3 402 CH
20% AUD_MIC1_DIODE 1 2 AUD_PORT_LINE_L_MIC
OUT 72 IN AUD_VREF_FP_MIC
6.3V 1K 5% R111AU AUD_PORT_B_L_HDR

X5R 2.2K 5% 402 CH 5 1 2 74
805 402 CH
AUD_VREF_FP_MIC_L
OUT
1
C BAW56S 2.2K 5% C
2
SOT363 402 CH
C83AU DIO
4.7UF
20%
AUD 6.3V
X5R
805
1
AUD
B B
A A
[PAGE_TITLE=AUDIO MIC BIAS & SPIDIF HDR]

hc_cdb_mpi.sch_1.75
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

BL AUDIO 0.05.00 9-15-06
D
D
CAD NOTE:
PLACE ETCH RESISTORS UNDER CODEC
1 R140AU 2
0OHM
SM
V_5P0_STBY\G M15AU
96 95 94 93 92 91 90 83 80 77 IN
115 MULTI
AUD
EMPTY 603
3
Q1AU
FET
1 SOT23
C 2
C
C79254-001
R15AU
2 1 R15AU_PN1_Q1AU_PN1
5% 10M 1
CH 402 C6AU
4.7UF
10%
+12V 16V
2 EMPTY V_AUD_FILTERED 1 R134AU 2 V_AUD_ANALOG 69
805 OUT 70
0OHM
1
SM
1 C72AU 1 C75AU CAD NOTE:
C71AU 1UF 100UF
0.1UF 20% 20.0% ADD SEVERAL VIAS AFTER ETCH RESISTOR
20% 6.3V 25V TO V_AUD_ANALOG
16V 2 X5R ELEC
2 Y5V 603 2 RDL
402
B B
C85AU C86AU C87AU

1 2 1 2 1 2
.01UF 10% .01UF 10% .01UF 10%

25V 25V 25V
X7R X7R X7R
402 402 402
AUD AUD AUD
C88AU C90AU C91AU
1 2 1 2 1 2
1 2
C77AU
A 470PF C111AU .01UF 10% .01UF 10% .01UF 10% A
10% 470PF 25V 25V 25V
50V 10% X7R X7R X7R
2 X7R 1 50V 402 402 402
402 X7R AUD AUD AUD
402
CAD NOTE:
DISTRIBUTE THREE NEAR THE REAR AUDIO JACK.
CAD NOTE: AUD ONE NEAR THE FRONT PANEL AUDIO CONNECTOR.
REMAINING ALONG ANTI-ETCH BETWEEN ANALOG / DIGITAL GROUND
PLACE GROUND::AUD-GROUND DECOUPLING SITE AS
CLOSE AS POSSIBLE TO AUDIO TRIPLE-STACK CONNECTOR
[PAGE_TITLE=AUDIO VREG]
hc_cdb_mpi.sch_1.76
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

116 115 110 106 104
LPC BUS HEADER 79
102
78
98
77
95
74
94
52
93
51
92
49 41 36 35
91 83 82 81
18
80
IN V_3P3_STBY\G MODULE NAME REV DATE
(ATX EV SPECIFIC) R143LH

DESIGN NOTE: 1 2 1 R6LH PS_ON_N
VCC 1K 5%
1K OUT 80 89
5%
D PS ON LOGIC 402 EMPTY
2 EMPTY
VCC3 R156LH 402 3 D
1 106 103 93 81 77 49 SLP_S3_N 1 2 1 Q15LH
J4LH C77EV 115 110
IN SLP_S3_N_XSTR_PIN1
MMBT3904
2X14HDR_G8 .1UF 10K 5% XSTR
20% 402 CH 2
CK_P_33M_LPCLAI_R 1 2 25V 116 115 110 106
77 IN 2 Y5V 93 92 91 83 82 81 R155LH
103 38 L_FRAME_N 3 603 51 49 41 36 35 18 IN V_3P3_STBY\G 1 2
IN 5 6 80 79 78 77 74 52
114 103 82 79 67 66 35 IN PLTRST_N 104 102 98 95 94 10K 5%
L_AD<3..0> 3 7 8 2 L_AD<3..0> 402 CH
103 77 38 BI 9 10 BI 38 77 103
1 77 IN H_SLOTOCC_N
0 11 12
116 113 81 29 28 27 26 IN SMB_CLK_MAIN 13 14 SMB_DATA_MAIN OUT 26 27 28 29 81 113 116
1 J2LH
V_3P3_STBY_CK_14M 15 16 SER_IRQ 37 79 103 1X2HDR
17 18 IN DESIGN NOTE:
HDR
TPM_CLKRUN_N 103
19 20 OUT DEBUG EV FEATURE: CPU DETECTION FOR FORCE POWER-ON
103 38 IN LPCPD_N L_DRQ_N OUT 38
38 10 H_SKTOCC_N 2
100 37 KBRST_N 23 24 A20GATE 37 104
IN
IN 25 26 OUT 1 R20LH 1
R12PR
49 IN SMI_N IO_PME_R_N IN 49 104 2.7K 0 BOM NOTE:
115 96 95 94 93 92 91 90 83 80 77 76 IN V_5P0_STBY\G 27 28 LPC_L_DRQ1_N OUT 38 5% 5%
INSERT JUMPER AT PIN 1-2 OF J2LH IF NO CPU STUFFED
2 CH 2 CH
116 115 110 106 104 102 98 95 94 R49LH 402 402
77 74 52 51 49 41 36 35 18 V_3P3_STBY\G 1 2 CONN
93 92 91 83 82 81 80 79 78
IN H_SLOTOCC_N
OUT 77
0 1A
805 CH
C DESIGN NOTE: C
STUFF R20LH TO DEFAULT ENABLE (MOBILE ONLY FEATURE) 116 115 110 V_3P3_STBY\G
DESIGN NOTE: 81 80 79 78 77 74 52 51 49 41 36 35 18 IN
106 104 102 98 95 94 93 92 91 83 82
R74CV 1 1 R126LH 1
CK_PCH_14M_LPC
C75EV C76EV DEFAULT STUFF R49LH.14MHZ CLK OPTION FOR PASL
44 IN 1 2 .1UF .1UF
680
20% 20% 5%
0 5% 25V 100
402 EMPTY 2 Y5V 2 25V
R29LH CH 2 BACKFEED_CUT_N 94
603 Y5V 402 31
603 115 96 95 94 93 92 91 90 83 80 77 76 IN V_5P0_STBY\G 1 2 OUT 80
1K 5% 96
402 EMPTY 3
CK_P_33M_PCI1 R57CK R58CV R89LH
44 IN 1 2 CK_P_33M_LPCLAI_PCI1 1 2 CK_P_33M_LPCLAI_R
OUT 77 PWRGD_PS 1 2 PWRGD_PS_RR 5 Q12LH
DESIGN NOTE: 103 95 89 81 77 IN
22 5% 0 5% XSTR
402 CH 402 CH 10K 5%
STUFF R62LH PWRGD_3V OP FOR LPT FAST BOOT 402 EMPTY 3904DUAL
R62LH 4
PWRGD_3V 1 2
116 103 82 81 77 38 37 13 IN
BOM NOTE: 15K 5%
402 CH Q12LH_BF_CUT
EMPTY R89LH PWRGD_3V OP FOR LPT FAST BOOT 6
STUFF R62LH PWRGD_3V OP FOR LPT FAST BOOT R88LH
115 110 106 103 93 81 77 49 SLP_S3_N 1 2 SLP_S3_RR_N 2 Q12LH
IN XSTR
B 4.7K 5% B
1 R14LH 402 CH 1 R107LH 3904DUAL
100K 1
1K 5%
DESIGN NOTE: 5%
2 EMPTY
2 EMPTY
402
BACKFEED CUT LOGIC 402
V_3P3_A
100 95 94 89 82 81 78 77 67 49 41 32 30 IN
102
DESIGN NOTE: R27LH 1
680
APS CONNECTOR 5%
R44LH CH 2 BACKFEED_CUT_LAN_N
402 94
112 98 96 95 94 89 78 44 32 31 30 IN V_5P0_A 1 2 OUT
1K 5%
402 EMPTY 3
116 115 110 106 104 102 J15BU R45LH
79 78 77 74 52 51 49 41 36 35 18 IN V_3P3_STBY\G R101BU PWRGD_PS 1 2 PWRGD_PS_LAN_R 5 Q8LH
98 95 94 93 92 91 83 82 81 80 2X4HDR_7 SLP_S3_N_J15BU 1 2 SLP_S3_N
IN 49 77 81 93 103 106 110 115 103 95 89 81 77 IN XSTR
R87BU 10K 5%
1 2 0 5%
116 402 EMPTY 3904DUAL
CH
94 89 82 81 78 77 67 49 41 32 30 IN
V_3P3_A 1 2 V_3P3_A_J15BU 3 4 402
V_3P3_STBY\G
IN 18 35 36 41 49 51 52 74 77 78 79 80 81 82 4
102 100 95
0 5%
5 6 83 91 92 93 94 95 98 102 104 106 110 115 R78LH
8 R102BU PWRGD_3V 1 2
A 402 CH
1 2 PCH_SLP_M_N
116 103 82 81 77 38 37 13 IN A
SLP_S4_N IN 38 92 94 103 115
104 90 38 IN 1 2 PCH_SLP_M_N_J15BU
15K 5% Q8LH_BF_CUT
SLP_S4_N_J15BU
HDR 0 5% 402 CH
0 5% 402 CH 6
402 CH
IPN: A91836-074 R46LH
R100BU 115 110 106 103 93 81 77 49 SLP_S3_N 1 2 SLP_S3_LAN_R_N 2 Q8LH
IN XSTR
4.7K 5%
DESIGN NOTE: 402 CH 1 R48LH 3904DUAL
1 R47LH 100K 1
1K 5%
BACKFEED CUT LAN LOGIC 5%
2 EMPTY
2 EMPTY 402
402
DESIGN NOTE:
STUFF R78LH PWRGD_3V OP FOR LPT FAST BOOT
BOM NOTE: [PAGE_TITLE=LPC_BUS]
EMPTY R45LH PWRGD_3V OP FOR LPT FAST BOOT BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
STUFF R78LH PWRGD_3V OP FOR LPT FAST BOOT hc_cdb_mpi.sch_1.77
INTEL
2 1
CR-78 :
8 @HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE787 6 5 4 3 2 1

SCHMITT TRIGGER (U6LH): STUFF BY DEFAULT
MULTI-CIRCUIT INVERTORS (U6LH, R1LH): DO NOT UN-STUFF FOR FEATURE TESTING DESIGN NOTE:
U6LH U6LH
R81LH
74LVC14 74LVC14 RESUME RESET LOGIC R21LH PCH_DPWROK
102 100 95 94 1 2
67 49 41 32 30 IN V_3P3_A 2 1 STBYPWG_RC_N 1 2STBYPWG_SCHMITT_N 3 4 STBYPWG_N OUT 38 78
89 82 81 78 77 47K 5% 499 1%
IC 402 CH
402 CH IC 1 R125LH
D VCC=14 VCC=14 10K
1 1 5% D
C19LH GND=7 GND=7 C106LH
1UF VCC=V_3P3_A VCC=V_3P3_A .1UF 1 2 CH
10% 10% C5LH 402
6.3V 10V .01UF
2 X5R 2 X5R 10%
402 402 25V
2 EMPTY
BOM NOTE: 402 R13LH
1 R18LH IF U6LH= 74HC14.EMPTY C106LH
1 2 PCH_RSMRST_R13LH_N U3LH
0 1 5% STM1061
IF U6LH= 74LVC14, STUFF C106LH 3.0V
5% 89 82 402 EMPTY Vth=
100 95 94 89 82 81 78 77 67 49 41 32 30 V_3P3_A
102
IN 2 CH 77 67
V_3P3_A
R28LH 1 OUT*
112 98 96 95 94 89 78 77 44 32 31 30 V_5P0_A 402 32 30 IN 1 2 3
IN 49 41
2
VCC
81 78 10K 5%
100 95 94 89 82 81 78 77 67 49 41 32 30 IN V_3P3_A 95 94 1 R1LH 402 EMPTY
VSS
102 102 100 1 1

1 R306LH STBYPWG_R_N
OUT 78 C4LH 5% OPT 2 OF 2
1UF 2 EMPTY IC
560 10%
1 R9LH 1 R305LH 5% 6.3V 603
1K 2 EMPTY 2 EMPTY
5% 4.7K 402 RSMRST_IC
5% 402
112 98 96 95 R7LH 2 EMPTY
2 CH R15LH 1 R19LH
44 32 31 30 IN V_5P0_A 1 2 402
402 1 2 PCH_RSMRST_N 909
94 89 78 77 OUT 30 38 78 103 116
5.6K 1% 1%
402 CH 0 5% 2 EMPTY
STBYPWG_BJT_PIN3 402 EMPTY
402
C 95 94 89 82 R303LH C
49 41 32 30 IN V_3P3_A 1 2 MBT3904DUAL 3 6 Q40LH
81 78 77 67 33K 5% R8LH
102 100
402 EMPTY 1 2 5 2 R22LH DESIGN NOTE:
STBYPWG_2_BJTPIN5 STBYPWG_BJT_PIN5 STBYPWG_BJT_PIN2
1 2
0 5% DEFENSIVE DESIGN
402 CH 2.1K 1%
402 CH
1 R304LH 1 XSTR
1.1K C101LH 4 1
1% 1UF
10%
2 CH
2 6.3V R23LH
402 EMPTY 1 2 INVSUS 1 R51LH 2 RSMRST_PWRGD_N
402 78 OUT IN 79 103
2.1K 1%
402 CH 1K 5%
402 CH
STBYPWG_PIN3 R24LH 78 STBYPWG_R_N 1 R52LH 2
1 2 OUT
0 5%
3 0 5% 402 EMPTY
STBYPWG_PIN1 402 EMPTY
1 Q2LH
MMBT3904 DESIGN NOTE:
XSTR
2 STUFF R52LH FOR NON-DEEP SX
STUFF R51LH FOR DSW S4/S5
DESIGN NOTE:
B STUFF R12LH FOR NON-DEEP SX MODE B
V_5P0_A PCH_DPWROK R12LH PCH_RSMRST_N
95 94 89 78 77 44 32 31 30 IN 1 2
112 98 96 78 38 IN
0 5%
402 EMPTY
102 100
67 49 41
95
32
94
30
V_3P3_A 116 115 110
V_3P3_STBY\G
102 100
V_3P3_A
89 82 81 78 77
IN 1 R137BV 81 80 79 77 74 52 51 49 41 36 35 18 IN 41 32 30 IN
22K 106 104 102 98 95 94 93 92 91 83 82 95 94 89 82 81 78 77 67 49
1 R890EV 5%
1 R30LH
2
10K 2 CH 10K
5% 603 R40LH 5%
2 EMPTY SLP_SUS 47K U6LH
402 OUT 78 96 5% 2 CH
3 402 74LVC14 116
CH R31LH R32LH
R144BV Q17BV_PIN5
402 Q5LH_PIN3 1 2 U6LH_PIN1 5 6 U6LH_PIN2 1 2 PCH_RSMRST_N 78
SLP_SUS_N 1 2 Q17BV OUT 30 38 78 103 116 30
104 38 32 30 IN 5 5% 38
22K 5% XSTR
78
INVSUS 1 3
0
402 CH IC
100
402
5%
CH
103
402 CH 3904DUAL OUT
4 1 R11LH 1 R25LH 2 VCC=14
0
INVSUS_R 5 Q5LH
1 J5LH 5% XSTR
VCC=V_3P3_A
1X2HDR 0 5% 1 GND=7
2 CH 402 CH 3904DUAL
C6LH
HDR 402 4 1UF
1 10%
M3LH 1 M4LH 6.3V
A 2 Q8LH_PIN3 2.2UF 22K 2 EMPTY A
10% 5% 402
6 6.3V
SLP_SUS R10LH 2 X5R 2 CH
96 78 1 2 Q8LH_PIN1 2 Q17BV 603 402
IN 5% XSTR
10K 3904DUAL
402 CH
1 R33LH
1 2
0 5%
402 EMPTY
BOM NOTE:
FOR LPT FAST BOOT
M3LH CHANGE TO 0.22UF [PAGE_TITLE=RESUME RESET LOGIC]
R40LH CHANGE TO 22K, R25LH TO 20K
hc_cdb_mpi.sch_1.78
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

SPI_TPM_HEADER
D
D
1 R88BU 2 J30BU SPI_CS0_N_TPM 1 R149BU 2 SPI_CS0_PRI_N_SW
83 84
103 78 IN
RSMRST_PWRGD_N PCH_RSMRST_N_TPM BI
0 5%
SPI_TPM 0 5%
402 CH
402 CH REV=1
1 R5BU 2 SPI_CLK_TPM CS0* 2 SPI_CS1_N_TPM 1 R123BU 2 SPI_CS1_SEC_N_SW 83 84 85
85 84 83 IN
SPI_CLK_PRI_SEC_FLSH_SW 3 GPIO CS1* 4 BI
0 5%
33 5% 402 CH
402 CH 5 GND VCCSTBY 6 V_3P3_SPI 79 83 84 85
DQ2_TPM
IN
7 CLK DQ2 8
1 R176BU 2 DQ2 1 R185BU 2
1 R187BU 2 DQ3 1 R7BU 2 DQ3_TPM
9 DQ3 MISO/DQ1 10
SPI_IO2
SPI_IO3
38 BI 11 HOLD* MOSI/DQ0 12 33 5% 0 5% BI 38
0 5% 33 5% 402 CH 402 CH
402 CH 402 CH 13 TPM_CS2* GND 14
IN 84 85
85 84 IN 15 WP* SERIRQ 16
17 PIRQ* VCC 18
SPI_MISO_TPM 1 R180BU 2 SPI_MISO_SW
19 PLT_RST* RSVD 20 OUT 83 84
1 R186BU 2 SPI_CS2 1 R177BU 2 SPI_R_CS2 33 5%
38 SPI_CS2_N 0 5% 0 5%
SYM 402 CH
IN OPTION 1
402 CH 402 CH
SPI_MOSI_TPM 1 R6BU 2 SPI_MOSI_PRI_SEC_FLSH_SW 83 84 85
1 R182BU 2 IN
85 84 83 79 IN
V_3P3_SPI SPI_WP_N_TPM HDR 33 5%
C 1K 5% 402 CH C
SER_IRQ
402 CH IN 37 77 103
P_INTF_N
1 R183BU2
EMPTY
63 35 IN
5%
V_3P3_STBY\G 104 106 110 115 116

114 103 PLTRST_N IN 18 35 36 41 49 51 52 74 77 78 80
67 66 35 IN 81 82 83 91 92 93 94 95 98 102
402
33
82 77 V_3P3_SPI_TPM 1 R212BU 2
0 5%
402 CH
1 R213BU 2 V_3P0_BAT_VREG
IN 41 50 51 52 89 103
0 5%
402 EMPTY
CAD NOTE:
R212BU & R213BU OVERLAP PAD
B B
A A
[PAGE_TITLE= SPI TPM]

INTEL
hc_cdb_mpi.sch_1.79 <DOCUMENT_NUMBER> 79 1.0
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE:
POWER LED LOGIC DESIGN NOTE:

DESIGN NOTE:
D GPIO_YLW_BLNK_HDR
OUT 64 LED_DRIVE_GP15: FP LED HEADER CONTROL
S0: LOW D
S3,S4: HIGH
115 96 95 94 93 92 91 90 83 80 77 76 V_5P0_STBY\G
IN LED_DRIVE_GP15
80 52 38 IN GPIO_GRN_BLNK_HDR 64
1 R116LH OUT
8.2K 1 R41LH
5% 115 96
GPIO_YLW_BLNK_BRD 1K
V_5P0_STBY\G 64 3
2 CH 90 83 80 77 76 IN OUT Q9LH
5%
R115LH 402 R8BU 95 94 93 92 91
1 R120LH R3LH 2 EMPTY
LED_DRIVE_GP15 1 2 PCH_QRT1_BJT5 1 2 FET
52 38 IN PCH_QRT1_BJT2
8.2K 89 80 77 PS_ON_N 1 2 1 402
80 8.2K 5% 1K 5% 5% IN R2Q1_GRNLED_HDR
402 EMPTY 402 CH R36LH 2 CH R9BU 2.2K 5% 2

3 2 1 402 CH
402 PCH_QRT0_BJT2 1 2
Q22LH 5 PCH_QRT1_R8BU
5% 8.2K
1K 5% GPIO_GRN_BLNK_BRD
EMPTY 402 OUT 64
IC 402 CH
6 R122LH 6
100 R37LH 4
3 1 R42LH
80 31 LATCHED_BACKFEED_CUT 1 2 2 Q22LH 94 80 31 IN
LATCHED_BACKFEED_CUT 2 1 2 Q23LH 3
96 94
IN 100 96 PCH_QRT0_BJT5
Q23LH 5 Q14LH
1K
8.2K 5% IC 5% 8.2K IC PCH_QRT0_R9BU 5%
402 CH CH 402 R5LH FET
1 1 IC PS_ON_N 1 2 1 2 EMPTY
89 80 77 IN
4 94 95
R2Q1_GRNLED_BRD
402
R44LB 90 91 2.2K 5% 2
V_5P0_R44LB 1 2 V_5P0_STBY\G
IN 76 77 402 CH
330 5% 80 83
92 93
402 CH 96 115
C R75BU C
V_5P0_R75BU 1 2 V_5P0_STBY\G
IN 76 77 80 83 90 91 92 93 94 95 96 115
330 5%
402 CH
OUT 77 80 89
J128EV
1X2HDR
PS_ON_N 1 2
TPEV_PS_ON_SIO_JUMPER
HDR R693EV
1 2
BOM NOTE: 0 5%
402 CH
DESIGN NOTE: PS ON HEADER (J128EV): DEFAULT STUFF FOR 0-1
LATCHED_BACKFEED CUT LOGIC
B 116 115 110 106 104 V_3P3_STBY\G B

79 78 77 74 52 51 49 41 36 35 18 IN
102 98 95 94 93 92 91 83 82 81 80
R76LH 1
R74LH 1 3.9K DESIGN NOTE:
8.2K 5%
5%
CH 2
CH
402
2 LATCHED_BACKFEED_CUT HARD DRIVE STATUS LED CTRL
100
402 31 80
OUT 94 96 R111LH
1 2
3 0 5%
VCC3 402 EMPTY
LATCH_BKFEEDCUT_BASE_DRV1 1 Q64LH
MMBT3904
XSTR
2
1 R130LH 1 R131LH
3 5.1K 5.1K
R72LH 5% 5%
96 94 77 31 BACKFEED_CUT_N 1 2 BACKFEED_CUT_RR_N 5 Q63LH 2 CH 2 EMPTY
100
IN XSTR 402 402
10K 5%
402 CH 3904DUAL
HD_LED_N OUT 64
116 4
98 95 94 93 92 91 R73LH DIS_LATCH_BFCN
PCH_SATA_LED_BJT2
74 52 51 49 41 36 35 18 IN V_3P3_STBY\G 1 2
A 83 82 81 80 79 78 77 MBT3904DUAL 3 6 A
115 110 106 104 102 10K 5%
402 CH PCH_SATA_LED_N R136LH
6
37 1 2 5 Q30LH 2
R71LH 49
IN PCH_SATA_LED_BJT5
90 38 10 H_DRAMPWRGD 1 2 DRAM_PWROK_RR 2 Q63LH 5.1K 5%

IN XSTR 402 CH
22K 5% 3904DUAL 4 1 XSTR
402 CH
1
1 R75LH
100K
5%
2 EMPTY
402
[PAGE_TITLE=PWR LED LOGIC]

hc_cdb_mpi.sch_1.80
INTEL
2 1
8 7 6 5 4 3 2 1
+12V MODULE REV DETAILS

DESIGN NOTE: SMB_DATA_RESUME OUT 20 22 23 24 25 38 66 81 114
SMB RESUME/MAIN LOGIC 1 R82LH

1K
3
Q10LH
5% FET 116 115 110 106 104 102 98 V_3P3_STBY\G
1 SOT23 78 77 74 52 51 49 41 36 35 18
2 CH 95 94 93 92 91 83 82 81 80 79
IN
2
402 PWRGD_PS_SMBUS_ISOLATE C79254-001 1 R129LH
2.7K
1 R128LH
2.7K
D SMB_DATA_MAIN 26 27 28 29 77 81 113 5%
3 OUT 116 5% D
102 98 95 94 93 92 R69LH R109LH 2 CH
2 CH
74 52 51 49 41 36 35 18
V_3P3_STBY\G 1 2 1 2 Q16LH_PIN2 1 Q6LH 402
91 83 82 81 80 79 78 77
IN MMBT3904 402
116 115 110 106 104 1K 5% 10K 5% XSTR 81 66 38 25 24 23 22 20 SMB_CLK_RESUME
402 CH 402 CH 2 114 20
IN SMB_DATA_RESUME
SMB_CLK_RESUME 114 81 66 38 25 24 23 22
IN
OUT 20 22 23 24 25 38 66 81
114 VCC3
3
Q11LH
FET
1 SOT23
2 1 R152LH
C79254-001 1 R153LH 8.2K
SMB_CLK_MAIN OUT 26 27 28 29 77 81 113
8.2K
5%
5%
116 2 CH
116 2 CH 402
113 81 77 29 28 27 26 SMB_CLK_MAIN 402
IN SMB_DATA_MAIN
113 81 77 29 28 27 26 IN
R101LH 116
1 2 VR_READY_OPT_R
4.7K 5%
402 CH 1 R50LH
DESIGN NOTE: C108LH R87LH
.1UF 1 2
10% 0 5%
POWER-GOOD 3V LOGIC 2 16V
X7R
10K 5% 402 EMPTY
C 402
402 CH C
R103LH Q1LH_PIN6_PIN4
1 2 3
4.7K 5% 6 R85LH
402 CH 1 2 Q1LH_PIN5 5 Q1LH
104 102 98 95 94 93 92
74 52 51 49 41 36 35 18 V_3P3_STBY\G 2 Q1LH 10K 5%
XSTR
91 83 82 81 80 79 78 77
IN V_3P3_A XSTR 1 R86LH 3904DUAL
89 82 78 77 67 49 41 32 30 Q1LH_PIN3 402 CH
116 115 110 106 2 R174LH 102 100 95 94
IN 3904DUAL 4.7K 4
1K 1 R4LH 1 5%
5% 10K
1 CH 5% 2 CH
402
402 2 EMPTY
402
R26LH R320LH PCH_SYSPWROK 38 81 82
PWRGD_PS_BUF 1 2 PWRGD_PS_OPT 1 2 OUT 100 113
6
0 5% 0 5% U6LH
402 CH 402 EMPTY PWRGD_PS_BUF_R 2 Q5LH 74LVC14
XSTR R53LH
R102LH 3904DUAL U6LH_PIN9 9 8 PWRGD_PS_U6LH_PN8 2 1
PWRGD_PS 1 2 6
103 95 89 77 IN 1 5% 0
R321LH IC EMPTY 402
10K 5% 1 R35LH Q13LH_PIN3 1 2 Q13LH_PIN2 2 Q13LH
402 CH 0 XSTR M2LH VCC=14
5% 10K 5% 3904DUAL 1 2 VCC=V_3P3_A
402 CH
B 2 CH 1 MULTI GND=7 B
PWRGD_PS_XSTR_PIN5_R 402 3
R2LH PWRGD_3V
EMPTY 402
M105LH 1 2 OUT 13 37 38 77 82 103
116
PWRGD_PS_XSTR_PIN5 5 Q13LH R55LH 1 2 249 1%
XSTR MULTI 402 EMPTY
1 R158LH
1 100K 1
C102LH 3904DUAL
0 5% 402 EMPTY
5%
C107LH
1UF 4 M20LH 402 EMPTY 100PF
402 EMPTY
R58LH
10% 1 2 2 CH 5%
5%
6.3V MULTI BOM NOTE: 402 50V
2 X5R R63LH 2 COG
402 113 110 107 103 82 11 VR_READY 2 1 M105LH STUFF FOR LPT FAST BOOT 402
IN 603 X5R
5% 0 1UF 10%
16V
0
EMPTY 402
R154LH
DESIGN NOTE: 1 2
FOR FASTER BOOT UP TEST: 0 5%
402 EMPTY R67LH
STUFF R63LH, EMPTY R26LH 1 2
SLP_S3_N_XSTR_Q19LH_PIN6
0 5%
402 EMPTY BOM NOTE:
DEFAULT EMPTY (R67LH):
116 115 STUFF FOR ENG EXP.
81 80 79 78 77 74 52 51 49 41 36 35 18 V_3P3_STBY\G
110 106 104 102 98 95 94 93 92 91 83 82
IN
2 R147LH 1 R38LH 2 PCH_SYSPWROK
10K OUT 38 81 82 100 113
5% 0 5%
A 1 CH 6 402 CH A
402
SLP_S3_N_XSTR_Q19LH_PIN3 2 Q19LH
3 XSTR
3904DUAL
R171LH 1
115 110 106 103 93 77 49 SLP_S3_N 1 2 SLP_S3_N_XSTR_Q19LH_PIN5 5 Q19LH
IN XSTR
DESIGN NOTE: 10K 5% 1
402 CH C103LH 3904DUAL
.1UF 4
LPT FAST BOOT: 10%
10V
STUFF R85LH, R103LH, M105LH, R101LH, R38LH 2 EMPTY
402
EMPTY R320LH, R4LH, R2LH, R154LH, M20LH
BOM NOTE: [PAGE_TITLE=PWR GOOD LOGIC]

DEFAULT EMPTY (DECOUPLING CAP C103LH): DEFENSIVE DESIGN BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
hc_cdb_mpi.sch_1.81
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE: R26PR
BOM NOTE: 1 2 PWRGD_3V OUT 13 37 38 77 81 82 103 116
LPT FAST BOOT: LPT FAST BOOT: 249 1%
STUFF R26PR STUFF R26PR 402 EMPTY
EMPTY R17LH, R30PR, R33PR
EMPTY R17LH, R30PR, R33PR CHANGE M1LH TO 1UF
CHANGE M1LH TO 1UF CHANGE R16LH TO 51K OHM
CHANGE R16LH TO 51K OHM CHANGE R77LH TO 1K OHM
R18PR
1 2 PCH_SYSPWROK OUT 38 81 82 100 113 PLTRST_PEG_PCIE_SLOTS_N
OUT 82
CHANGE R77LH TO 1K OHM
D 0 5%
402 EMPTY 1 R43LH D
U6LH 100K
74LVC14 5%
R30PR DESIGN NOTE: 3 2 CH
GLUE
V_3P3_A R16LH 11 10 1 2 PLTRST_CPU_N D Q3LH
IN PU_V_3P3_A_R16LH PLTRST_N_PIN10_13
OUT 10 37 113 402
51.1K 1% 178 1% PMOSFET
402 CH IC 402 EMPTY 1 R33PR PCIE RESET LOGIC
VCC=14 84.5
GND=7 1% 1
BOM NOTE: S G
VCC=V_3P3_A 2 EMPTY PCIE_RESET_R
402
100
102
LPT INTERPOSER:STUFF R30PR AND R33PR, EMPTY R18PR 2
78
95
77
94
32
67
89
30
49
82
41
81
1 R43PR CAD NOTE:
0 PLACE R33PR AND R30PR
5% U6LH
NEAR U6LH 74LVC14
2 CH
113 110 107 103 82 81 11
VR_READY R77LH 402 13 12 GLUE_PLTRST_PCIE_SLOTS_N 1 R90LH 2 PLTRST_PEG_PCIE_SLOTS_R_N
IN OUT 82
1K 1% 49.9 1%
402 EMPTY R83LH IC 402 CH
PLTRST_N_R33PR 1 2 PLTRST_N_R83LH VCC=14
0 5% GND=7 BOM NOTE:
3 402 EMPTY100 95 V_3P3_A R34LH
R17LH 32 30 1 2
VCC=V_3P3_A
ISOLATION RESISTOR R90LH
PLTRST_N IN UN-STUFF FOR FEATURE TESTING
114 103 82 79 77 67 66 35 1 2 PLTRST_N_R30PR 5 Q7PR 94 89 82 81 78 77 67 49 41 1K 5%
IN XSTR 102
402 CH
10K 5%
C 402 EMPTY M1LH 3904DUAL C
4
MULTI 3
EMPTY 402 R65LH
5.1K 114 103 82 79 77 67 66 35 PLTRST_N 1 2 PLTRST_N_R65LH 5 Q4LH
IN XSTR
10K 5% 3904DUAL
402 CH 1 4
R84LH
5.1K
5% R39LH
CH 38 GPIO_PCIE_RESET 1 2
1 402
IN
116 115 V_3P3_STBY\G C7LH 2 1K 5%
81 80 79 78 77 74 52 51 49 41 36 35 18 IN .1UF 402 CH 1
C2LH
110 106 104 102 98 95 94 93 92 91 83 10% .1UF
10V 10%
1 R61LH 2 X5R PLTRST_PEG_PCIE_SLOTS_N
22K 402 3
OUT 82
2
10V
EMPTY
5% U2LH R54LH
Q16LH
402
2 CH 1 2 GPIO_PCIE_RESET_R 1
74LVC1G14 MMBT3904
402 1K 5% 1 XSTR
Q7PR_PIN6 REV=1 402 CH C11LH
.1UF 2
6 1 NC VCC 5 1 R56LH 2 PCH_SYSPWROK 38 81 82 100 113 10%
OUT 10V
113 1 R60LH 2 100 1% 2 EMPTY
B 103 82 81 11
VR_READY Q7PR_PIN2 2 Q7PR 2 A 402 EMPTY 402 B
110 107
IN XSTR
0 5%
402 CH 3904DUAL
3 GND Y 4 U2LH_PIN4
1 1 1 R57LH 2 PWRGD_3V 13 37 38 77 81 82 103 116
C1LH 1 OF 1 OUT
1 R59LH .1UF 249 1% R97LH
10% IC 402 CH PLTRST_PEG_PCIE_SLOTS_N
10K 10V 82 IN 1 2 PLTRST_PEG_SLOTS_N
OUT 20
5% 2 X5R 0 5%
2 EMPTY 402 402 CH
402 DESIGN NOTE:
U2LH: SCHMITT-TRIGGER INVERTER R98LH

1 2 PLTRST_PCIE_SLOTS_N
OUT 22 23 24 25
U2LH: DEFENSIVE DESIGN 0 5%
402 CH
BOM NOTE:
LPT FAST BOOT:
PLTRST_PEG_PCIE_SLOTS_R_N R99LH
VCC3 CHANGE R149CV TO 1K OHM 82 IN 1 2
U1CV CHANGE C16CV TO 0.022UF 0 5%
402 EMPTY
VCC3 MAX6895AAZ
R148CV
REV=1 1 2 PWRGD_3V OUT 13 37 38 77 81 82 102 100 95 94
LPT FAST BOOT: 1
5 VCC OUT 4 0 5% 103 116 67 49 41 32 30 IN V_3P3_A
STUFF R216LB 1 R216LB R216LB DEFENSIVE DESIGN, C17CV PWRGD3V_PCHSYSPWROK_4
402 EMPTY 89 82 81 78 77
10K .1UF 1 1
EMPTY R200LB 10%
100
113
A 5% C21LH A
82
38
81
10V R135CV CDELAY_U1CV .01UF
2 EMPTY 2 X5R CDELAY 6 R149CV PCH_SYSPWROK 20%
402 402 1K
1 OUT 50V
1% ENABLE 1K 5% 2 X7R
CH 402 CH 603
402 C16CV
R200LB 2 .022UF
113
82
110
81 11 VR_READY 1 2 PCH_SYSPWROK 38 81 82
10%
IN OUT 50V CAD NOTE:
107 103 0 5% 100 113 X7R
402 EMPTY IN_U1CV 3 IN GND 2 603 PLACE DECOUPLING (C21LH) CLOSE
1 TO SCHMITT TRIGGER (7414)/U6LH
2 R150CV DESIGN NOTE:
DESIGN NOTE: C59LB 1K G34169-001 IC
.1UF 1% U1CV IS TO FIX 100MS DELAY ISSUE IN LPT A0
10%
EV FOR FUTURE ENGINEERING 50V CH
EMPTY 1 402 U1CV:DEFENSIVE DESIGN
DEBUG ONLY 805 2
[PAGE_TITLE=PCIE RESET LOGIC]
hc_cdb_mpi.sch_1.82
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

U10BU SPI_CLK_PRI_SEC_FLSH
U9BU 74CBT3125
SPI_MOSI_PRI_SEC_FLSH 38 84
74CBT3125 IN
IN 38 84 2
2 104 83 PCH_SPI_OE_N 1 A
PCH_SPI_OE_N
1 A IN OE
104 83 IN OE VCC=V_5P0_STBY B
VCC=V_5P0_STBY B VCC=14 3
D VCC=14 3 GND=7 IC
GND=7 IC 85 84 83 79 OUT SPI_CLK_PRI_SEC_FLSH_SW D
85 84 83 79 SPI_MOSI_PRI_SEC_FLSH_SW
OUT
U10BU
U9BU 74CBT3125 SPI_CLK_EC
74CBT3125 BI 103
SPI_SI_EC IN 103 5
5 EC_SPI_OE_N A
104 83 4
EC_SPI_OE_N 4 A IN OE
104 83 IN OE VCC=V_5P0_STBY B
VCC=14 6 GND=7 IC
GND=7 SPI_CLK_PRI_SEC_FLSH_SW V_5P0_STBY\G 76 77 80 83 90 91 92 93 94
IC 85 84 83 79 OUT IN 95 96 115
85 84 83 79 SPI_MOSI_PRI_SEC_FLSH_SW
OUT
U10BU 1
U9BU 74CBT3125 V_3P3_STBY\G 110 115 116 C180BU
74CBT3125 IN 18 35 36 41 49 51 52 74 77 78 79 80 .1UF
SPI_SO_EC OUT 103 9 81 82 91 92 93 94 95 98 102 104 106 10%
10V
9 EC_SPI_OE_N 10 A 2 X5R
104 83 IN OE 402
104 83 EC_SPI_OE_N 10 A VCC=V_5P0_STBY B
IN OE
VCC=14 8 GND=7 IC
SPI_MISO_SW
GND=7 IC 85 84 83 79 OUT V_3P3_SPI
84 83 79 IN CR2BU
C U10BU 30V C
SCHOTTKY
U9BU 74CBT3125 V_3P3_EPW_DIODE V_3P3_EPW
1 2 18 41 51 83 92 94
74CBT3125 SPI_MISO IN
OUT 38 84 12
12 104 83
PCH_SPI_OE_N
13 A SM
PCH_SPI_OE_N IN OE DIO
104 83 13 A VCC=V_5P0_STBY B 0.5A
IN OE
VCC=14 11 GND=7 IC OUT 84
GND=7 85 84 83 79 V_3P3_SPI
SPI_MISO_SW IC OUT
84 83 79 IN
V_5P0_STBY\G C52BU
115 96 95 94 93 92 91 90 83 80 77 76 IN 1 2
U12BU SPI_CS0_ISOLATE_N .1UF 10%
74CBT3125 10V
IN 38 84
X5R
2 402
104 83 PCH_SPI_OE_N 1 A
IN OE
VCC=V_5P0_STBY B
B VCC=14 3 B
GND=7 IC
84 83 79 SPI_CS0_PRI_N_SW
OUT
U12BU
74CBT3125 SPI_CS0_N_EC
IN 103
5
104 83 EC_SPI_OE_N 4 A
IN OE
VCC=V_5P0_STBY B
VCC=14 6 J24BU
GND=7 IC 1X2HDR
R172BU
84 83 79 OUT SPI_CS0_PRI_N_SW 84 83 79 OUT SPI_CS0_PRI_N_SW 2 1 1 2 V_3P3_SPI
OUT 79 83 84 85
U12BU 3.3K 5%
74CBT3125 SPI_CS1_N_PU 1 R166BU 2 V_3P3_EPW EMPTY 402 EMPTY
IN 18 41 51 83 92 94
9 3.3K 5% J26BU
EC_SPI_OE_N 10 A 402 CH 1X2HDR
104 83 IN OE R173BU
VCC=V_5P0_STBY B 85 84 83 79 OUT SPI_CS1_SEC_N_SW 2 1 1 2 MODE J24BU J25BU J26BU
VCC=14 8 3.3K 5% NORMAL OPERATION 1-X ALL OPEN 1-X
GND=7 IC J25BU EMPTY 402 EMPTY
SPI_CS1_SEC_N_SW 1X3HDR PROGRAM SPI0 1-2 1-2 1-2
85 84 83 79 OUT 1
A 2 SPI_CS_N PROGRAM SPI1 1-2 2-3 1-2 A
U12BU SPI_CS1_ISOLATE_N 3
74CBT3125
IN 38 84
12 EMPTY
PCH_SPI_OE_N A
104 83 IN 13 OE
VCC=V_5P0_STBY B J27BU
VCC=14 11 2X4HDR
GND=7 1 2
IC 3 4 SPI_CLK_PRI_SEC_FLSH_SW 79 83 84 85
SPI_CS1_SEC_N_SW SPI_MISO_SW 5 6 SPI_MOSI_PRI_SEC_FLSH_SW
BI
85 84 83 79 OUT 84 83 79 BI BI 79 83 84 85
7 8
V_5P0_STBY\G 2
C33BU
1
EMPTY
94 93 92 91 90 83 80 77 76 IN A91836-070
115 96 95 .1UF 10%
10V
X5R
402 [PAGE_TITLE=SPI PROG CIRCUIT] hc_cdb_mpi.sch_1.83
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

PRIMARY SERIAL FLASH

D
D
DESIGN NOTE:
CAD NOTE:
SCHEMATICS 64MBIT SPI IPN :E79340-001
PLACE CLOSE
TO SPI 1
BOM NOTE:
CAD NOTE:
EMPTY R160LB FOR SINGLE SPI
OVERLAY SPI PARTS WITH EACH OTHER
R160LB BOM NOTE:
85 IN SPI_MISO_SEC_FLSH 1 2
0 5%
SPI (SOCKET): XU3LB (D72836-001 LOTES), (D62233-001 WIESON)
402 CH SPI (BLANK): U3LB (G36217-001 WINBOND W25Q64CV) 8 PIN 64 MBIT
CAD NOTE:
85 84 83 79 V_3P3_SPI
PLACE 0.5-2 INCH IN
FROM SPI CHIP
R169LB
84 83 79 OUT SPI_MISO_SW 1 2 SPI_MISO_FLSH
IN 84
C 33 5% C
402 CH
8
OUT 84 XU3LB
SPI_MOSI_PRI_SEC_FLSH_SW R164LB SPI_SKT
1 2 OUT 84
85 84 83 79 IN VCC
33 5% SPI_MOSI_FLSH 5 D
402 CH SPI_CLK_FLSH 6 C
R165LB 1 2
85 84 83 79 IN SPI_CLK_PRI_SEC_FLSH_SW 1 2 SPI_WP0_N 3
S* Q
W*
33 5% SPI_HOLD0_N 7 HOLD*
402 CH
SPI_CS0_PRI_N_SW VSS
84 83 79 IN
OUT 84 SKT
R35LB
4
OUT 84
85 79 IN
DQ2 1 2
33 5%
402 CH
R67LB DESIGN NOTE:
DQ3 1 2
85 79 IN
33 5% OVERLAPPING PARTS: ONLY STUFF ONE(U3LB) OR (U2LB)
402 CH
R8CV CAD NOTE:
83 38 IN SPI_CS1_ISOLATE_N 1 2 SPI_CS1_SEC_N_SW
OUT 79 83 85
B 0 5% OVERLAY SPI (U3LB) & (U2LB) WITH EACH OTHER B
402 EMPTY
R33CV
83 38 IN SPI_CS0_ISOLATE_N 1 2 SPI_CS0_PRI_N_SW
OUT 79 83 84
0 5%
402 EMPTY
R60CV SPI_MISO
84 83 79 IN SPI_MISO_SW 1 2 OUT 38 83
0 5%
402 EMPTY U2LB
R65CV AT26DF321
85 84 83 79 OUT V_3P3_SPI 1 2 V_3P3_EPW_DIODE
IN 83 SO 8 SPI_MISO_FLSH
OUT 84
0 5% 85 84 83 79 V_3P3_SPI 2 VCC
84 V_3P3_SPI IN 3
79 IN 402 EMPTY NC
83 84 SPI_MOSI_FLSH 15 SI NC 4
85 R67CV IN 16 5
85 84 83 79 SPI_CLK_PRI_SEC_FLSH_SW 1 2 SPI_CLK_PRI_SEC_FLSH
38 83
84 IN SPI_CLK_FLSH SCK NC
OUT IN 84 83 79 IN SPI_CS0_PRI_N_SW 7 CS* NC 6
0 5% 84 SPI_WP0_N 9 WP* NC 14
402 EMPTY IN 1 13
R68CV 84 IN SPI_HOLD0_N NC NC
SPI_MOSI_PRI_SEC_FLSH NC 12
A R170LB 1 R163LB 1 85 84 83 79 OUT SPI_MOSI_PRI_SEC_FLSH_SW 1 2 IN 38 83 10 11 A
1K 1K GNDOPTION 2 NC
5% 5% 0 5%
402 EMPTY
CH 2 CH 2 REV=1 EMPTY
402 402 SPI_WP0_N 84
OUT
V_3P3_SPI
R171LB 1 IN 79 83 84 85
1K SPI_HOLD0_N 84
OUT
5% C74LB
5VDUAL 1 2
EMPTY 2 104 98 96 90 66 60 59 58 57 56 55 54 31 IN
402 112
BOM NOTE: .1UF 10%
1 1 16V
DEFAULT EMPTY (R171LB) C79LB
1.0UF
C78LB
.1UF
EMPTY
402
DESIGN FEATURE 20% 20%
FOR DISABLING EXTERNAL 2 10V
2 25V
FLASH PROTECTION Y5V
603
Y5V
603 [PAGE_TITLE=SERIAL FLASH PRIMARY]
hc_cdb_mpi.sch_1.84
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS
SECONDARY SERIAL FLASH

D DESIGN NOTE: D
SCHEMATICS 64MBIT SPI IPN :E79340-001
CAD NOTE:
OVERLAY SPI PARTS WITH EACH OTHER
BOM NOTE:
SPI (SOCKET): XU4LB (D72836-001 LOTES), (D62233-001 WIESON)
SPI (BLANK): U4LB (G36217-001 WINBOND W25Q64CV) 8 PIN 64 MBIT
CAD NOTE:
85 84 83 79 V_3P3_SPI
PLACE 0.5-2 INCH IN
FROM SPI CHIP
R110LB
84 OUT SPI_MISO_SEC_FLSH 1 2 SPI_MISO_SEC_FLSH_OUTPUT
33 5% SPI
402 CH
8
OUT 85 XU4LB
C SPI_MOSI_PRI_SEC_FLSH_SW R111LB 85 SPI_SKT C
84 83 79 IN 1 2 OUT
VCC
33 5% SPI_MOSI_SEC_FLSH 5 D
402 CH 6
SPI_CLK_SEC_FLSH C
R112LB 1 2
84 83 79 IN SPI_CLK_PRI_SEC_FLSH_SW 1 2 3
S* Q
SPI_WP1_N W*
33 5% SPI_HOLD1_N 7 HOLD*
402 CH
VSS
85 84 83 79 SPI_CS1_SEC_N_SW
IN OUT 85
SKT
85
4
R91LB OUT
84 79 IN DQ2 1 2
33 5%
402 CH
R97LB
84 79 IN DQ3 1 2
33 5%
402 CH
DESIGN NOTE:
B OVERLAPPING PARTS: ONLY STUFF ONE(U4LB) OR (U5LB)
B
CAD NOTE:
OVERLAY SPI (U4LB) & (U5LB) WITH EACH OTHER
85 84 83 79 V_3P3_SPI
IN
85 84 83 79 V_3P3_SPI
IN
U5LB
AT26DF321
SO 8
2 VCC
R115LB 1 NC 3
R113LB 1 1K 85 IN SPI_MOSI_SEC_FLSH 15 SI NC 4
1K 16 5
5%
5% 85 IN SPI_CLK_SEC_FLSH SCK NC
CH 2 85 84 83 79 SPI_CS1_SEC_N_SW 7 CS* NC 6
CH 2 402
IN 9 14
402 SPI_WP1_N 85
85 IN SPI_WP1_N WP* NC
OUT 85 SPI_HOLD1_N 1 NC NC 13
IN 12
NC
R114LB 1 SPI_HOLD1_N
10 GNDOPTION 2 NC 11
1K OUT 85
5% V_3P3_SPI
A EMPTY 2 IN 79 83 84 85 REV=1 EMPTY A
402
BOM NOTE:
DEFAULT EMPTY (R114LB)
DESIGN FEATURE
FOR DISABLING EXTERNAL 1 2
C80LB C81LB
FLASH PROTECTION 1.0UF .1UF
20% 20%
10V 25V
2 Y5V 1 Y5V
603 603
[PAGE_TITLE=SERIAL FLASH SECONDARY]

hc_cdb_mpi.sch_1.85
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

FAN CONFIGURATION CAD NOTE:
MODULE NAME
SST
REV
1.1.2
DATE
WW17.5
CPU FAN:
ATX: PLACE BELOW/RIGHT OF CPU SOCKET
+12V +12V
D J3TH
1X4HDR D
1
CPU_FAN_DRIVER 1
2 R18TH
1 1 3 3.3K
VCC3 R14TH C7TH 4 5%
.1UF
0 20% CH
1A 25V HDR 402
2 EMPTY 2
DESIGN NOTE: VCC3 CH 603
805 1 R13TH 2 CPU_FAN_TACH
CPU_TACH_OUT
OUT 103
DELETE R121CV, R122CV C80741-001
2
15K 5%
1 3 402 CH 1
DIRECT CONNECT CPU_FAN_CTRL_EC IN CRB Q2TH
FET R15TH 1
R17TH 1 R16TH 2 1 C10TH
2.2K CPU_FAN_DRIVER_GATE
6.2K .01UF
5% 5% 220 2 5% 20%
50V
CH CH 402 CH 2 EMPTY
402 402 603
2 2
R121CV R34TH
103 IN CPU_FAN_CTRL_EC 1 2 CPU_FAN_CTRL_EC_FPGA
1 2 CPU_FAN_CTRL_OUT CPU_FAN_OUT
0 5%
402 CH 0 5%
402 CH
C C
CAD NOTE:
REAR CHASSIS FAN (J4TH):
ATX: PLACE NEAR BACK-PANEL
VCC3
+12V
+12V
J4TH 1
1 R24TH VCC3 1X4HDR
2.2K REAR_FAN_TACH_DRIVER 1 R23TH
5%
2 CH 3 1 2 3.3K
5%
402 R20TH Q3TH 1 3
104
REAR_FAN_CTRL_EC 1 2 1
FET R21TH C9TH 4 CH
402
IN REAR_FAN_PWM_R
0 .1UF
2
5% 0 2 1A 20%
B CH 402 C80741-001 CH 2 25V HDR R19TH B
EMPTY 1 2 REAR_FAN_TACH 104
805 603
REAR_TACH_OUT
OUT
2 15K 5%
402 CH 1
1 R31TH 2 REAR_FAN_R_CTRL REAR_FAN_CTRL R22TH
6.2K 1
0 5% 5%
C8TH
402 CH .01UF
BOM NOTE: CH 20%
402 50V
VCC3 STUFF FOR 4-PIN FAN
2 2 EMPTY
EMPTY FOR 3-PIN FAN 603
+12V +12V
1 R53TH J5TH
2.2K 1X4HDR 1
5% VCC3
2 CH
FRONT_FAN_TACH_DRIVER 1 R26TH
402 3 1 2 3.3K
Q4TH 3 5%
104 IN
FRONT_FAN_CTRL_EC 1 R27TH 2 FRONT_FAN_PWM_R 1
FET R29TH
0
1
C12TH
4 CH
402
5% 0 2 1A .1UF
HDR 2
20%
CH 402 C80741-001 CH 25V 1 R25TH 2 FRONT_FAN_TACH 104
805 2 EMPTY
FRONT_TACH_OUT
OUT
2 603 15K 5%
402 CH 1
A R28TH 1 A
6.2K C11TH
1 R35TH 2 FRONT_FAN_R_CTRL 5% .01UF
FRONT_FAN_CTRL
CH 20%
0 5% 402 50V
402 CH 2 2 EMPTY
603
CAD NOTE:
FRONT CHASSIS FAN (J5TH):
ATX: PLACE BELOW/LEFT OF DIMM B
[PAGE_TITLE=FAN CIRCUITRY]
hc_cdb_mpi.sch_1.86
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

PB MOUNTING HOLE
J1PB J8PB J13PB
MTG_HOLE MTG_HOLE MTG_HOLE
D NC9 9 NC9 9 NC9
D
EMPTY EMPTY EMPTY
J2PB J7PB J14PB

NC9 9 NC9 9
NC9
EMPTY EMPTY EMPTY
J4PB J6PB J15PB

NC9 9 NC9 9
NC9
EMPTY EMPTY EMPTY CAD NOTE:
LB12PB & LB14PB: WEEE & ENGINEERING SAMPLE LABEL CAN PLACE EITHER TOP/BOTTOM PCB
C C
J3PB J5PB J16PB
NC9 9 NC9 9 NC9 D99257-001
LB14PB WEEE1010
EMPTY EMPTY EMPTY LABEL LB12PB
LABEL
1
J11PB J10PB NONFCC_VAL_LABEL
MTG_HOLE MTG_HOLE EMPTY
NC9 9 NC9 9
DESIGN NOTE:
EMPTY EMPTY EV BRD/INTERNAL BRD USE D99257-001
CRB/EXTERNAL BRD USE D57446-001
J9PB J12PB
MTG_HOLE MTG_HOLE PB_FREE_2LI G35124-001
NC9 9 NC9 LB4PB LB13PB
LABEL
LABEL
B EMPTY EMPTY B
1
1
DESIGN NOTE:
EMPTY EMPTY 3000X1000_TARGET
LABELS LB7PB
LABEL DESIGN NOTE:
1500X150_TARGET CAD NOTE:
B4_SILK
LB6PB INTEL_LOGO LB1PB
1
LABEL LB13PB: FPGA LEDS NETNAME LIST
LABEL DESIGN NOTE:
LB6PB: PLACE KOZ TARGET NEAR CPU AND DIMMS FOR BUILD/WOC NOTES
1
A30094-001
1
1375X250_TARGET
EMPTY LB15PB
LABEL
DESIGN NOTE: 200956-001 (NO CONCEPT MODEL): CE MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS)
600X200 E1_SILK
DESIGN NOTE: 628492-001: FCC MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS) LB9PB LB2PB A19177-001
1
LABEL
DESIGN NOTE: 622954-001: C-TICK MARK SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (MAY NOT BE ON RVP DESIGNS) LABEL
DESIGN NOTE:
DESIGN NOTE: KOREAN CERT (NO IPN, NO CONCEPT MODEL) SHOULD BE COVERED WITH BLANK WHITE LABEL UNTIL CERTIFIED (NOT ON RVP DESIGNS) 622954-001 DESIGN NOTE:
1
LB9PB: FOR LAN STEPPING
1375X250_TARGET EMPTY LB15PB: CPU VBOOT SUPPORT LABEL
LB5PB DESIGN NOTE:
UPDATE ACCORDING TO CPU VREG EU1VR
LABEL
A 600X200 A
A19177-001 LB5PB: ISN BLANK LABEL AND KOZ (ASSY LABEL) LB10PB E2_SILK
LABEL
DESIGN NOTE:
LB3PB
LABEL
622954-001
1375X250_TARGET DESIGN NOTE: LB9PB: FOR PCH STEPPING
LB20PB
1
LABEL
SILK TARGET FOR MAC ADDRESS LABEL EMPTY
A19177-001 600X200
1
LB11PB
LABEL
EMPTY DESIGN NOTE: 622954-001 [PAGE_TITLE=MTG HOLES/LABELS]

LB8PB
LABEL DESIGN NOTE:
SILK TARGET FOR RESERVED PURPOSE BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
1000X187 hc_cdb_mpi.sch_1.87
INTEL
1
LB9PB: FOR VR12.5 STEPPING <DOCUMENT_NUMBER> 87 1.0

8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

IBX 03/13/08
D
CORE VR MODULE D
V_SM POWERED BY 5VDUAL

V_SM_VTT POWERED BY V_SM
V_1P05_PCH POWERED BY V_SM
V_1P05_ME POWERED BY V_5P0_STBY\G
VCORE POWERED BY VREG_12V_POWER

C
V_1P8_SFR POWERED BY VCC3 C
5VDUAL POWERED BY V_5P0_STBY\G OR VCC

V_3P3_STBY\G POWERED BY V_5P0_STBY\G
V_3P3_EPW POWERED BY V_3P3_STBY\G OR VCC3
V_5P0_A V_3P3_A
VCC3 VREG_12V_POWER
V_5P0_STBY\G
B B
VCC V_1P8_SFR
(EV ONLY)
5VDUAL V_3P3_STBY\G V_1P5_PCH

VCORE
V_SM V_3P3_EPW
A A
V_1P05_PCH V_SM_VTT V_1P05_ME
[PAGE_TITLE=POWER MAP]
hc_cdb_mpi.sch_1.88
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

-12V VCC3 VCC +12V

D
D
98 96 95 94 89 78 77 44 32 31 30 V_5P0_A PWRGD_PS 77 81 95 103
112
IN OUT
1 R33BV
22K J2BV 1
5% 2X12PWR_KP20 C145BV
2 CH 470PF
13 1 10%
402 50V
14 2 2 X7R
R37BV 15 3 402
80 77 IN PS_ON_N 1 2 BV_PS_ON_HEADER_N 16 4
0 5% 17 5
402 CH VCC 18 6
1 1 19 7
C37BV C35BV 8
1UF 470PF V_5P0_A
20% 10% 21 9
OUT 30 31 32 44 77 78 89 94 95 96 98 112
6.3V 50V 22 10
2 Y5V 2 X7R
402 603 23 11
24 12 1 1 1
VCC3 C30BV C32BV C41BV
1.0UF .1UF .1UF
20% 20% 20%
CONN 2 10V
2 25V
2 25V
Y5V Y5V Y5V
603 603 603
C C
96 95
78 77 V_5P0_A DESIGN NOTE: DESIGN NOTE:
31 30 IN VCC3
44 32 LED IS LIGHT WHEN STUFF [1-2]
94 89 POWER CONNECTOR DECOUPLING
112 98 LED IS NOT LIGHT WHEN STUFF[1-0]
J3BV 1 1 R35BV 2
VCC VCC3 +12V -12V
1X2HDR BOM NOTE:
HDR 10K 5%
STUFF JUMPER SUITCASE [1-2] 402 CH
2
BV_VREG_MAIN_R34BV 2X4_POWER_DETECT OUT 35 89 116
1 R34BV
750 DESIGN NOTE:
5%
2 CH 1 C31BV2 1C231BV2 1 C40BV2 USED TO DETECT 2X4 PRESENCE
402 CONNECT TO GPIO
BV_VREG_MAIN_STBY_LED_R .1UF 20% .1UF 20% .1UF 20% J4BV.4 WILL PULL GPIO36 TO GND WHEN 2X4 PLUG IN
25V 25V 25V
Y5V Y5V Y5V
603 603 603
2
CR5BV C34BV C33BV C39BV
B GREEN 100UF 100UF 100UF B
LED 1 2 1 2 1 2 1 C36BV2
1 VREG_12V_POWER 107 108 109 110 111
20.0% 25V 20.0% 25V 20.0% 25V .1UF 20% OUT
ELEC ELEC ELEC 25V
RDL RDL RDL Y5V
603
J1BV
2X2HDR J4BV
1 2 2X4PWR
3 4
1 P1 P5 5
BATTERY CR6BV 2 P2 P6 6
100 95 94 82 EMPTY 3 7
49 41 32 30 IN V_3P3_A 2 2X4_GND 4
P3 P7
8
81 78 77 67 P4 P8
102 3 V_3P0_BAT_VREG OUT 41 50 51 52 79 103
HDR
1 R36BV 2 BV_VBAT_VREG_R_CR 1 1 R79BV
1 1K
1K 5% C150BU BAT54C C38BV
1 2 SOT23_C 1UF 1 1 5%
402 CH
XBT1BV DIO 10%
6.3V
C28BV
470PF
C27BV
470PF
2 CH
.1UF 20% 2 402
X5R 10% 10%
2 25V Y5V 402 50V 50V 2X4_POWER_DETECT 35 89 116
BV_VREG_VBAT_R 3 603
2 EMPTY 2 EMPTY OUT
A 1 603 603 A
BOM NOTE: CAD NOTE:
THROUGH-HOLE 3PCOIN
BATTERY ADDED IN MOD FILE PLACE NEAR PCH
CAD NOTE:
DO NOT PLACE BATTERY NEAR
MOUNTING HOLES, GROUND OR VIAS
[PAGE_TITLE=POWER-CONN, BATTERY]

hc_cdb_mpi.sch_1.89
INTEL
2 1
8 7 6 5 4 3 2 1

96 95 94 93 92 91 83 80 77 76 V_5P0_STBY\G MODULE NAME REV DATE
IN 1
DESIGN NOTE: 1 R47BV 115
C45BV
1K 1 C23BV 1 C24BV 1 22.000UF
VSM VR CONTROL 5% 3 BV_VSM_EN 3300UF 470UF C25BV 20%
Q27BV 90 20% 20% 22.000UF
2 CH 1 1 R108BV OUT 6.3V 6.3V 20% 2 6.3V
402 R77BV
BV_VSM_EN_VCC3_CTRL_R
MMBT3904 20K 2 ALUM
2 EMPTY
2 6.3V X5R
805
1 2 XSTR 5% 1 R61BV RDL RDL X5R
2
BV_VSM_EN_VCC3_CTRL
EMPTY 2 0 805
D 10K 5% M1BU 2 CH 5%
1 R62BV 402 402
MULTI
CH 1UF
1K 2 CH CAD NOTE: D
5% 402 BV_V_5P0_STBY_B1
CH
DUAL FOOTPRINT
2 BV_VSM_EN_PIN3
402
402
6 3 MBT3904DUAL 1
1 C29BV 1 C26BV C284BV
1
1 22.000UF
R19BV 3300UF 470UF C283BV 20%
104 77 38 SLP_S4_N 1 2 BV_SLP_S4_B1 2 5 20% 20% 22.000UF 6.3V
IN 6.3V 6.3V 20% 2 X5R
EMPTY EMPTY 6.3V
10K 5%
Q5BV 2 RDL 2 RDL 2 X5R 805
402 CH
1 XSTR 805
C242BV 1 4
1.00UF
20%
6.3V CAD NOTE:
2 EMPTY DESIGN NOTE:
402 DUAL FOOTPRINT
DUAL SITE THE MLCC'S WITH
THE BULK CAPACITOR
L1BV
1UH CAD NOTE:
98 96 90 84 66 60 59 58 57 56 55 54 31
5VDUAL 1 2 PLACE CLOSE BV_5V_DUAL_FILTERED
112 104
IN
1 TO FET
C IND C14BV C
1UF
20%
6.3V
H_DRAMPWRGD
CR3BV 2 X5R
1 R56BV OUT 10 38 80 1 2 603
100 1 R58BV
5% 1K 3
2 CH 5% 1 R60BV
603 2 CH 0 D Q3BV
402 5% EU2BV BAT54C G16062-001
2 EMPTY APW7138 3
SOT23_C
402 EMPTY R1BV
REV=1 1 2 BV_VSM_UGATE_1 1
BV_VSM_PGOOD 16 PGOOD VIN 1 G S
12 PVCC UG 14 BV_VSM_UGATE 0 1A FET
2 805 CH 2 3
VCC D Q8BV
R101BV C4BV D99281-007
5VDUAL 1 2 3 FCCM 1 2 G16062-001
54
31
55
56
57
58
59
60
66
84
90
96
98
112
104 IN BV_VSM_FCCM
4 13 BV_VSM_BOOT L2BV
10K 5% EN BOOT 1UF 10%
R29BV 560NH
402 EMPTY PHASE 15 25V 603 X5R 1 2 BV_VSM_UGATE_R29BV 1 2 1 V_SM OUT 11 16 26 27 28
R102BV BV_VSM_FSET 7 FSET ISEN 9 BV_VSM_CNTRL_PIN2
G S 29 38 91 93 111
BV_VSM_VCC 1 2 0 1A FET IND
5 R54BV 805 CH 2
0 5% NO CONNECT NC 1 2
C99BV 402 CH 6 FB
1 2
8 VO 8.25K 1%
B 4.7UF 10% 11 BV_VSM_LGATE 402 CH BV_PHASE_NODE_VSM B
6.3V X5R LG
603 C54BV PGND 10
1 2 17
4.7UF 10% OPTION 2 OF 2 GND
6.3V 603 X5R IC
BV_VSM_EN
3 3 1 R17BV
90 IN DESIGN NOTE:
D Q4BV D Q2BV 2.2
5% CAPS MOVE FROM TO 108
R18BV 2 CH
1 2 BV_VSM_LGATE1_A 805
BV_PHASE_NODE_S_RC
0 1A 1 1
805 CH G S
FET G S
FET 1
C10BV
2 G16062-001 2 4700PF
G16062-001 20%
C116BV R16BV 50V
1 2 2 X7R
1 2 BV_VSM_LGATE2_B
603
2200PF 10% 0 1A CAD NOTE:
1 R57BV 50V X7R 805 CH
33K 402 PLACE NEAR DRAIN AND
5% SOURCE OF LS FET
2 CH
402
R3BV
BFB_VSM_CNTRL_PIN6 1 2 BFB_VSM_CNTRL_PIN5R3
CAD NOTE: 1 R208BV

A 1 R4BV 10K 1%
0
A
PLACE THESE COMPONENTS 8.06K 402 CH
5%
CLOSE TO THE CONTROLLER 1%
2 CH
2 CH 1 R25BV 2 CAD NOTE:
402 PLACE NEAR MIDDLE OF DIMM
402
BFB_VSM_RBV
0OHM
SM
R172BV DDR_FB_OV2
1 2 91
IN
63.4K 1%
402 CH
R167BV
1 2 DDR_FB_OV1
IN 91
120K 1%
CAD NOTE: 402 CH
CAD NOTE: ROUTE NETS IN PARALLEL: R125BV
1 2 DDR_FB_OV3
IN 91 [PAGE_TITLE=VREG:V_SM]
PLACE R574EV CLOSE TO PIN R4BV.1 FOR AVMC BV_VSM_CNTRL_PIN2 40.2K 1% BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
402 CH hc_cdb_mpi.sch_1.90
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
DDR_FB_OV2
MODULE REV DETAILS
90 OUT V_5P0_STBY\G
NOTE: STUFF R167BV AND R172BV AS DEFAULT 115
76 77 80 83 90 91
IN 92 93 94 95 96
DDR_FB_OV1
DDR GPIB OUTPUT VOLTAGE SELECTION 90 OUT 1 R166BV
PCH_GP46 PCH_GP45 DDR VOUT 20K
PCH_GP60 5%
2 CH
1 1 1 1.35V 402
D DDR_FB_OV1_R
1.40V Q20BV D
1 1 0 Q22BV XSTR
6 R165BV
NTJD4001N 6 3 3904DUAL
PCH_GPIO45_R
1 2 PCH_GP45
1 0 1 1.45V 2
IN 38 49
2 Q22BV_Q20BV 10K 5%
1 402 CH
1 0 0 1.50V 5 1 R155BV
1K
FET 5%
0 1 1 1.50V 1 4 2 EMPTY
402
115 V_5P0_STBY\G
0 1 0 1.55V 94
R175BV
91 90 V_5P0_STBY_R175BV V_5P0_STBY\G
77 76 IN 1 2 IN 76 77 80 83 90 91 92 93 94 95 96 115
0 0 1 1.60V 83
93
80
92 20K 5% 1 R170BV
96 95 402 CH 20K 110 115 116
0 0 0 1.65V DDR_FB_OV3 5% 93 94 95 98
90 2 CH V_3P3_STBY\G 77 78 79 80
OUT 402 IN 18 35 36 41
49 51 52 74
Q24BV 1 R168BV 81 82 83 92
NTJD4001N 6 3 10K 102 104 106
Q20BV 5%
PCH_GP60
111 93 91 90 38 29 28 27 26 16 11 IN V_SM R179BV 2 5 3 XSTR 2 CH
49 38 IN 1 2 3904DUAL
PCH_GPIO46_R 402
1 PCH_GP60_R179BV
5
V_SM C140BV 1 C134BV 10K 5%
C 90 38 29 28 27 26 16 11 IN .1UF 470UF 402 CH C
111 93 91 10% 20% 1 R180BV 1 4 FET 4
1 R135BV 2 10V 10V R169BV PCH_GP46
X5R 10K 1 2
ALUM IN 38 52
1K 402 2 RDL 5%
1% 2 CH 10K 5%
DESIGN NOTE: 402 CH
CH 402
402
2 EU6BV DDR VOLTAGE OVERWRITE
RT9199
BV_V_MEM_VTT_REF_PIN3
3 REFEN VIN 1
1 CAD NOTE:
MAXIMIZE GROUND SHAPE
5 NC VOUT 4
V_SM_VTT
R134BV AND VIAS
FOR THERMAL RELIEF OUT 26
29
27 28
1K VCNTL_EU6BV 6 VCNTL
1% 2 C139BV 7 NC 1
CH .1UF 8 NC GND 2
1
402 10% R136BV C137BV 1 C133BV 1 C144BV
2 1 10V R275BV REV=1 1K .1UF 1000UF 1000UF
X5R 1 2 IC 1% 10% 20.0% 20%
402 10V 2.0V 6.3V
0 1A EMPTY 2 X5R 2 ALUM
2 EMPTY
603 CH 1 1 1 603 402 RDL TH
C135BV C141BV C136BV 2
10UF .1UF .1UF
20% 10% 10%
VCC 6.3V 10V 10V
B 2 EMPTY 2 X5R 2 EMPTY CAD NOTE:
B
805 402 402 CAD NOTE:
KEEP CLOSE TO OUTPUT
DUAL SITE
PUT NEAR OUTPUT
OF REGULATOR
1
C228BV
4.7UF
20%
10V
2 EMPTY
805
1
C229BV
4.7UF
10%
10V
2 EMPTY
1206 CAD NOTE:
PLACE 4.7UF CAPS FOR CH B

AT LEFT AND RIGHT ENDS
CAD NOTE: OF VTT ISLANDS
PLACE 4.7UF CAPS FOR CH A
AT LEFT AND RIGHT ENDS
A A
OF VTT ISLANDS
[PAGE_TITLE=VREG: V_SM_VTT]
hc_cdb_mpi.sch_1.91
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

116 115 110 R71BV MODULE NAME REV DATE
81 80 79 78 77 74 52 51 49 41 36 35 18 V_3P3_STBY\G 1 2
106 104 102 98 95 94 93 92 91 83 82
IN
0 5%
402 CH
CLPWROK_R_PULLUPS2
BOM NOTE: 1 R7BV

5.6K
UN-STUFF VREG CIRCUITRY FOR NON-AMT SYSTEM 1%
D V_1P05_ME R620BV R626BV R627BV R697BV
2 1 V_1P05_ME_R695EV 2 1 2 1 1 2 PCH_MEPWROK 1 R6BV 2 CH
112 92 51 41 IN PCH_PWROK_OPAMP_OUTPUT_Q14EV
OUT 37 92 R72BV 33K 402 D
1K 5% 2.49K 1% 82.5K 1% 453 1% 94 83 51 41 18 IN V_3P3_EPW 1 2 PCH_MEPWROK
OUT 37 92
1 R730BV 5%
402 EMPTY 402 EMPTY 402 EMPTY 402 EMPTY 1K 0 5%
1 V_5P0_STBY\G 402 EMPTY
2 CH 1
76
77
80
83
90
92
91
93
94
95
96
115 IN 1% 402
C1BV DESIGN NOTE: C17BV
1.0UF 2 EMPTY BOM NOTE: 116 .1UF
20% 1 402 110 FET_MCH_CLPWROK_PINS2_3 10%
10V C142BV STUFF FOR LMV331 106 3P3EPW RACE CONDITION DEFENSIVE
2 10V
2 EMPTY 5 Q29BV 1UF 104 115 X5R
603 PCH_PWROK_OPAMP_PLUS_Q14EV 1 LMV321 20% 98 102 402
+
V+ 4 16V Q6BV
2 EMPTY 94 95
MBT3904DUAL 3 6
116 115 110 106 3 92 93
93 92 91 83 82 81 R734BV -
V-
IC
805
81 82
51 49 41 36 35 18 IN V_3P3_STBY\G 1 2 PCH_PWROK_OPAMP_MINUS_Q14EV
2 77 78 R5BV
80 79 78 77 74 52 R732BV 49 51 112 92 51 41 V_1P05_ME 1 2 5 2
104 102 98 95 94 20K 1% 2 1 18 35 IN FET_MCH_CLPWROK_PIN5
402 EMPTY 1 R733BV V_3P3_STBY\G IN 36 41 30.1K 1%

9.09K 330 5% 52 74 402 CH 1 R8BV 1
1% 402 EMPTY 79 80 301K C16BV XSTR 1
1% .47UF 4 1 C18BV
2 EMPTY 83 91 10%
402 DESIGN NOTE: 2 CH 6.3V 100PF
402 2 X5R 5%
50V
ME PWROK GENERATION BACKUP CIRCUIT DELAY REQUIREMENTS
402 2 COG
402
8.3 MPS ON RISE/2.8MPS ON FALL
DESIGN NOTE: PCH_MEPWROK BOM NOTE:

OUT 37 92
C PCH ME POWER OK CONTROL EU17BV: E82640-001 - FLATHEADCREEK C
116 115
93 92 91 83 82
110 106
81 V_3P3_STBY\G R41BV E35460-001 - WHALERSCREEK
51 49 41 36 35 18 IN 1 2 V_Q19BV_R
80 79 78 77 74 52 10K 5%
104 102 98 95 94
402 CH
Q19BV
MBT3904DUAL 3 6
R42BV 5 2
92 77 38 PCH_SLP_M_N 1 2 PCH_SLP_Q19BV_P5
115 103 94
IN L51BV
10K 5%
402 CH 1UH
1 XSTR
C108BV 4 1 1 2 V_1P05_ME OUT 41 51 92 112
.1UF
10% EU17BV IND
2 16V APW7153
EMPTY
1 1 1
402
REV=1 C451BV C452BV C453BV 1 R11BV
22.000UF 22.000UF CAD NOTE:
20% 20% 10UF 0OHM
115 96 7 PVDD COMP 10 20%
90 83 80 77 76 IN V_5P0_STBY\G V_1P05_ME_COMP_PIN10
2 6.3V
X5R 2 6.3V
X5R 6.3V
PLACE NEAR PCH
95 94 93 92 91 1 805 805 2 X5R 2
1 R9BV C2BV 6 PVDD FB 9 V_1P05_ME_FB_PIN9 603 SM
10K .1UF
1% 10%
1 1 R453BV
B 1 R10BV 2 2 10V 4 1 C7BV
8 VDD 27.4K B
V_1P05_ME_FB_PIN7_OPT
CH EMPTY
10K R15BV IC C3BV LX 3 1%
V_1P05_ME_SHTDWN_Q2PIN3
402 402 .1UF V_1P05_ME_LX_PIN3
1% 1 5 22.000UF 10% 1 SHDN/RT 2 CH

2 V_1P05_ME_SHTDWN_QPIN1 Q7BV 20% 10V
V_1P05_ME_SHDN_PIN1
402
2 CH 10K 5% 3 2 6.3V 2 X5R
402 402 CH X5R 402 LX 4
6 805
2 GND R12BV
V_1P05_ME_COMP_RC1
2 Q7BV 1 1 2
C455BV
V_1P05_ME_SHTDWN_Q2PIN1
IC 5 PGND EP_GND 11 1000PF 78.7K 1%

1 R50BV 1 R20BV 10% 402 CH DESIGN NOTE:
10K 1 2 1 OF 1 2 50V 1 R452BV
1% X7R C454BV
402 249K 1 2 R12BV = 78.7K FOR 1.05 V OUT
2 CH 340K 1% IC 1%
402 CH
402 R194BV 2 CH 33PF 5%
1 2 E82640-001 402 50V
COG CAD NOTE:
1K 5% 402
402 EMPTY PLACE RESISTOR AND CAP NEAR TO EU17BV
115
92 77 38 PCH_SLP_M_N
103 94
IN
113 112
44 41 40 11
107 106
10
V_1P05_PCH 1 R14BV 2 V_1P05_ME 41 51 92 112
104 103 98 93 51
IN OUT BOM NOTE:
116 0.001 1%
2010 EMPTY
A EMPTY EVERYTHING ELSE ON PAGE FOR NON AMT A
STUFF R14BV FOR NON AMT SYSTEM
[PAGE_TITLE=VREG:V_1P05_ME]

hc_cdb_mpi.sch_1.92 INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

V_SM
111 91 90 38 29 28 27 26 16 11 IN
D
1 C27VR D
1 1
470UF C25VR C26VR
20% 4.7UF .1UF
16.0V 20% 10%
2 ELEC
2 10V
2 10V
RDL EMPTY X5R
805 402
81 80 79 78 77 74 52 51 49 41 36
116
35
115
18
V_3P3_STBY\G
110 106 104 102 98 95 94 92 91 83 82
IN
1 R32VR
16.5K
1%
2 CH
402
SOT 3
V1P05PCH_CNTRL_INPUT D42319-001
4 D Q23VR
93 5 LM358 R33VR
IN + G 7 V_PCH_CORE_OPAMP_OUT_RES 1 2 V_PCH_CORE_OPAMP_OUT
1 1 R34VR 6
-
V 0 5%
C DESIGN NOTE: C20VR 7.87K 402 CH 1 C
.1UF 1% 8 +12V G S
EV ONLY :R34VR 8.25K OHM FOR 1.1V 10% 2 CH FET
2 16V
402 IC 2
X7R
603 U11BV
BOM NOTE:
LPT FAST BOOT : C20VR CHANGE TO 0.1UF

R14VR
1 2 V1P05PCH_CNTRL_INPUT6
R35VR
2 2 1
0
402
5%
CH
C95VR V_1P05_PCH OUT 10 11 40 41 44 51 92 98 103 104
1 .1UF 106 107 112 113 116
C1VR 20% 1K 5%
100PF 25V 402 CH 628955-111
5% 1 Y5V 1 1
2 50V
EMPTY
603
1 C22BV
C21BV C42BV
22UF 22UF
402 820UF 20% 20%
20.0% 6.3V 6.3V
6.3V 2 X5R 2 X5R
ALUM 805 805
2 RDL
BOM NOTE:
B BOM NOTE: PLACEHOLDER

B
FOR NON-AMT : USE 628955-029
C22BV: RUBYCON CAP (A65154-040)
TO BE EOL.
REPLACE WITH 628955-111.
DESIGN NOTE:
V1P05PCH_CNTRL_INPUT
PCH CORE LVR COTNROL OUT 93
115 96 95 V_5P0_STBY\G R54VR

83 80 77 76 IN 1 2 1 R9VR
94 92 91 90 0
10K 5% 5%
402 CH
2 CH
402
V1P05PCH_FET_CNTRL_PINS23
VCC3
A A
1 R12VR
1K
5%
2 CH V1P05PCH_FET_CNTRL_PINS6
402 Q2VR
MBT3904DUAL 3 6
R81VR 5 2
115 110 106 103 81 77 49 IN SLP_S3_N 1 2 V1P05PCH_FET_CNTRL_PIN5
10K 5%
402 EMPTY R13VR 1
1 C6VR 4 1 XSTR
1K .1UF
5% 10%
16V
[PAGE_TITLE=VREG:V_1P05_PCH]
2 CH 2
402 EMPTY
402
hc_cdb_mpi.sch_1.93
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

DESIGN NOTE:
115 96 95 94 93 92 91 90 83 80 77 76 IN V_5P0_STBY\G
+12V 3.3VAUX SWITCH LOGIC
ALWAYS STUFF CIRCUIT VCC3 Q25BV
FDS8958A
1 R116BV 1 R117BV 1 8 V_3P3_PCIVAUX 25 94
D 8.2K 8.2K S1 D1 OUT 20 22
VREG_PCIAUX_NCH 2 7 23 24 D
5% 5% 116 115 94 IN G1 D1
2 2 81 80 79 78 77 74 52 51 49 41 36 35 18 V_3P3_STBY\G 3 S2 D2 6
CH CH
110 106 104 102 98 95 94 93 92 9491 83 82
IN VREG_PCIAUX_PCH 4 5 1 C125BV 1
603 603 IN G2 D2 C124BV
100 96 94 80 77 31 BACKFEED_CUT_N 100UF .1UF
IN VREG_PCIAUX_NCH 20.0% 20%
OUT 94 IC
1 R111BV VCC3 25V 25V
R24BV 2 ELEC
2 EMPTY
4.7K V_5P0_STBY_R117BV 1 2 VREG_PCIAUX_PCH 94 C195BV C52333-001 RDL 603
5% OUT
0 5% 1 2
2 CH Q26BV 402 CH C51BV
402 MBT3904DUAL 3 6 1 2
.1UF 20%
25V
R112BV 5 2 R115BV 2.2UF 10% Y5V
1 2
BACKFEED_CUT_GATE_VAUX_NCHAN BACKFEED_CUT_GATE_VAUX_PCHAN 1 2 16V 603
X5R
4.7K 5% 4.7K 5% 603
402 CH 402 CH
XSTR
4 1
V_3P3_LAN
94 68 67 IN
2 Q12BV
1 R26BV S PMOSFET
C LATCHED_BACKFEED_CUT 10K C
96 80 31 IN 5%
100
1 R110BV 2 CH R23BV
402 SLP_M 1 2 SLP_M_R2Q50BV 1
4.7K D
5% 0 5% G
115 3
2 EMPTY 92 2 R13BV 1 PCH_SLP_M_N_PIN5 Q9BV 402 CH
1 3
402 38 PCH_SLP_M_N 1 C6BV 92
77
IN MMBT3904 .1UF V_3P3_EPW 51
BACKFEED_CUT_SOURCE_GATE_VAUX_FET2 10K 5% XSTR 18
103
402 CH
10% OUT 41
2 10V
1 2 X5R 83
C8BV 402 94
1.0UF
20% DESIGN NOTE:
10V
2 Y5V
603 3.3VEPW SUPPLY CONTROL
115 96 95 94 R184EV DESIGN NOTE: 94 25 24 23 22 20 V_3P3_PCIVAUX

83 80 77 76 V_5P0_STBY\G 1 2 IN
IN VCC3
93 92 91 90 4.7K 5% BOM NOTE:
402 EMPTY STUFF R932EV BY DEFAULT STUFF FOR NON-INTEL
112 98 96 R932EV 1 1 LAN (NO WOL) OR M0 ONLY
44 32 31 30 IN V_5P0_A 1 2
95 89 78 77 4.7K 5% R140BV R139BV
B R22BV 402 CH 0 0 B
94 77 1 2 R126BV 1A 1A
IN BACKFEED_CUT_LAN_N
LANDUAL_PCH_R126BV 1 2 VREG_LANDUAL_PCH 94
4.7K 5% OUT EMPTY EMPTY
402 CH 3 249 1%
CH C86BV 2
805
2
805
100 96 R181BV 402 1 2
77 31 BACKFEED_CUT_N 1 2 BFC_RR_N 5 Q30BV
94 80
IN XSTR V_3P3_LAN 67 68 94
4.7K 5% 1.0UF 20% OUT
402 EMPTY
4
3904DUAL
10V
Y5V
115 R183BV 603
92 91 90 83 80 77 76 V_5P0_STBY\G 1 2 DIS_LANDUAL_PCH 1 C180BV 1 C181BV BOM NOTE:
96 95 94 93
IN 100UF .1UF
4.7K 5% VCC3 Q40BV 20.0% 20% COST REDUCED OPTION
402 EMPTY 6 FDS8958A 25V
ELEC
25V STUFF R140BV AND UNSTUFF Q40BV,
R138BV 1 8 2 RDL 2 EMPTY
FOR NO SLOT/LAN PWR ISOLATION
103 38 SLP_LAN_N 1 2 SLP_LAN_R_N 2 Q30BV S1 D1 603
IN XSTR 94 100 VREG_LANDUAL_NCH 2 G1 D1 7
4.7K 5% 95 89 IN V_3P3_A 3 6
402 CH
3904DUAL 41 32 30 IN S2 D2
1 82 81 78 77 67 49 4 G2 D2 5
102
IC R28BV
1 R193BV 94 68 67 V_3P3_LAN 1 2 V_3P3_EPW 18 41 51 83 92 94
1K +12V VREG_LANDUAL_PCH IN OUT
M137BV 94 IN C52333-001 0 1A
5% EMPTY
1 2 805
2 EMPTY MULTI VCC3
402 R30BV
CH 805 1 R171BV C179BV 81 80 79 78 77 74 52 51 49 41 36
116
35
115
18
V_3P3_STBY\G 1 2 V_3P3_EPW 18 41 51 83 92 94
4.7K 5% 8.2K 1 2
110 106 104 102 98 95 94 93 92 91 83 82
IN OUT
A 5% 0 1A A
.1UF 20% 603 EMPTY
2 CH
25V
603 R131BV Y5V
LANDUAL_PCH_R131BV 1 2 VREG_LANDUAL_NCH
OUT 94 603 116 115 V_3P3_STBY\G R86BV
0 5% 81 80 79 78 77 74 52 51 49 41 36 35 18 IN 1 2 V_3P3_PCIVAUX
OUT 20 22 23 24 25 94
3 402 CH DESIGN NOTE: 110 106 104 102 98 95 94 93 92 91 83 82 0 1A
R182BV
96 94 80 77 31
BACKFEED_CUT_N 1 2 1 Q39BV C87BV 603 EMPTY
IN
GATE_LANVDUAL_NCHAN
MMBT3904
100
402
4.7K 5%
EMPTY 2
XSTR
1 2
3.3VLAN/EPW SWITCH LOGIC
R78BV
.1UF 20%
25V
Y5V
STUFF TO ISOLATE 3.3VAUX (SLOTS) FROM LAN/EPW
94 77 BACKFEED_CUT_LAN_N 1 2 603
IN
4.7K 5%
402 CH
DESIGN NOTE: [PAGE_TITLE=3P3AUX & LAN/EPW]
CLARKSVILLE NEED TO BPAGE DRAWING
SUPPORT WAKE FROM LAN hc_cdb_mpi.sch_1.94
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

CAD NOTE: BOM NOTE:

OVERLAPPING SITE STUFF FOR 10/100 LAN SKUS
EMPTY FOR GB LAN SKUS U7LH VCC
+12V STM1061
D FOR CRB, STUFF U7BV. EMPTY U8BV Vth= 3.0V
1 OUT*
D
U7BV 3 1 R105LH
RT9183 VCC
10K
2
1 1 R91LH VSS
5%
3.3V C8LH 1
2 IN OUT 3 1UF 5% OPT 2 OF 2 2 EMPTY
10% IC
603
GND 2 6.3V 2 EMPTY
EMPTY 603 12V_IC
402
1 EMPTY
OUT 30 32 41 49 67 77 78 81 82 89 94 95 1 R92LH
100 102 909
1%
V_3P3_A 2 EMPTY
U8BV R188EV TPEV_V3P3A_IN6_DP
402
1 C183BV 1 2 OUT
EZ1086C 220UF 0 5%
OUT 2 20% 402 EMPTY
V_5P0_A 3 6.3V VCC
U8LH
STM1061
98 96 95 94 89 78 77 44 32 31 30 IN IN ALUM R190EV
112 OUT 4 2 RDL TPEV_V3P3A_IN6_DN Vth= 3.0V
ADJ/GND 1 2 OUT
1 1 OUT*
0 5%
C182BV
1.0UF
ADJ 1 IC 402 CH VCC 3
20% 2
1 1 R93LH VSS
10V
2 C9LH 1
C Y5V 1UF 5% OPT 2 OF 2 C
603 10% IC
2 6.3V 2 EMPTY
EMPTY 603 VCC_IC
1 R142BV 402
274
1% BOM NOTE: 1 R94LH
2 CH 909
402 STUFF FOR VARIABLE 1%
EMPTY R142BV FOR NON-VARIABLE 2 EMPTY
402
BV_V_STBY_ADJ PWRGD_PS_STM1061
1 1 R141BV
C184BV
.1UF 453
20% 1% U9LH
25V VCC3 1 R100LH
EMPTY 2 2 CH STM1061 0
603 402 Vth= 3.0V
5%
1 OUT* 2 EMPTY
BOM NOTE: 3 402
VCC
STUFF R141BV WITH 453 OHM (A93548-165) FOR VARIABLE 1 1 R95LH
2 VSS
STUFF O OHM (A93549-001) FOR NON-VARIABLE
C10LH PWRGD_PS
89
1UF 1 OUT 77
10% 5% OPT 2 OF 2
81
6.3V IC 103
2 EMPTY 2 EMPTY
402 603 VCC3_IC
B B
1 R96LH
909
1%
2 EMPTY
402 DESIGN NOTE:
DEFENSIVE DESIGN
V_3P3_A
89 82 81 78 77 67 49 41 32 30 IN
102 100 95 94
DESIGN NOTE: 2 1
V_5P0_A Q1BV
96 95 94 89 78 77 44 32 31 30 IN S PMOSFET R146BV
112 98 NON-DECAP SX 0
5%
1 STUFF R159BV & R146BV
2 EMPTY Q21BV & Q1BV EMPTY
Q21BV 1206
110 115 116
S PMOSFET R159BV Q1BV_PIN1 1 2 92 93 94 98
D 77 78 79 80
0
5%
G V_3P3_STBY\G OUT 18 35 36 41
A 3 49 51 52 74 A
EMPTY 81 82 83 91
Q21BV_PIN1 1206 102 104 106
1 2 R132BV
G D V_5P0_STBY\G 115
SLP_SUS_FET2 1 2
OUT 76 77 80 83 90
91 92 93 94 96 103 32 30 IN
3
0 5%
402 CH
R160BV
SLP_SUS_FET 1 2
103 32 30 IN
0 5%
402 CH
[PAGE_TITLE=VREG: 3P3_STBY]
hc_cdb_mpi.sch_1.95
INTEL
2 1
8 7 6 5 4 3 2 1
92 91 90 83
115
80
95
77
94
76
93
IN
V_5P0_STBY\G V_5P0_A IN 30 31 32 44 77 78 89 94 95 96 98 112 MODULE REV DETAILS
BOM NOTE:
1 R187BV 1 R189BV 5VDUAL
IN 31 54 55 56 57 58 59 60 66 84 90 96 98 104
EMPTY R188BV & R259BV FOR NON DEEP SX MODE 4.7K 22K BOM NOTE: 112
5% 5%
R188BV 2 CH 2 CH EMPTY R163BV, R66BV
402 402 BOM NOTE:
104 38 31 OUT SUS_PWR_ACK 1 2 Q32BV_PIN3 STUFF M2BV, R64BV, R65BV
1 R162BV
0 5% 10K STUFF R188BV FOR USB WAKE 54/55
D 402 CH 5%
2 CH
D
Q32BV_PIN6
1 MBT3904DUAL 3 6 BOM NOTE:
C102BV 402
1UF R192BV Q32BV R190BV
20% 5 2 FOR LPT FAST BOOT:
6.3V 1 2 Q32BV_PIN5 Q32BV_PIN2 1 2 SUS_PWR_ACK_R
2 EMPTY CHANGE R189BV TO 22K, R192BV TO 0-OHM
603 0 5% 1 10K 5% EMPTY R163BV & R66BV, STUFF M2BV, R64BV & R65BV
402 CH 402 CH
M2BV XSTR 1 R163BV
1 R259BV 4 1 10K
10K 1 5%
10K 5% C20BV
5%
CH .1UF 2 EMPTY
2 CH 10% 402
402 10V
402 2 1 R66BV 2 EMPTY
0 402
5%
R65BV 2 EMPTY
402
38 31 IN SUS_WARNB 1 2 Q32BV_PIN4 BOM NOTE:
103
1 R64BV
0 5% 5V_DUAL 3
402 CH EMPTY R164BV FOR
1K 95 94 89 78 77 44 32 31 30 IN V_5P0_A USB WAKE S4/S5 D
5% 112 98 96
2 CH
402 BOM NOTE: 1 R153BV
+12V 8.2K VREG_5VDUAL_PCH 1
FOR CORSAIR POWER SUPPLY FIX 5%
100 96 31 IN G S Q34BV
C STUFF R65BV, EMPTY R66BV 2 CH PMOSFET
2 D32396-001 C
603
VREG_5VDUAL_PCH 89 78 77 44 32 31 30 IN V_5P0_A
1 R100BV Q23BV_PIN6 1 2 112 98 96 95 94
8.2K OUT 31 96 100
5% 98 104 112
BOM NOTE: 0 5%
2 CH 402 EMPTY1
C90BV
5VDUAL OUT
59
31
60
54
66
55
603 R164BV .1UF 56 57 58
FOR EV: STUFF R103BV , EMPTY R164BV, R283BV 84 90 96
20%
FOR CRB: STUFF R177BV, R178BV, R164BV 5VDUAL_NCH 16V
EMPTY R103BV, R268BV, OUT 96 2 EMPTY
402
BOM NOTE:
ALWAYS STUFFED 3
100
77 31 BACKFEED_CUT_N STUFF FOR WAKE FROM
D Q35BV
94 80
IN
S4, S5 SUPPORT. BV_5VDUAL_MBT3904DUAL2 1 R104BV 2
IF STUFFED, EMPTY R177BV, R174BV
10K 5%
1 R178BV 402 CH 96 5VDUAL_NCH 1 2 VREG_5VDUAL_NCH 1
1 IN G S
DESIGN NOTE: R103BV 30K 5% FET
4.7K M1BV 402 CH 2 1
5% 10K 1
DEFENSIVE DESIGN C101BV R133BV
CH Q23BV 5% 1UF VCC 51
DEFAULT EMPTY (R105BV)
2
402 MBT3904DUAL 3 6 EMPTY 10%
10V
CAD NOTE: 5%
402 2 EMPTY CH
94 1 R106BV 2 5 2 2 402 0.1 INCH COPPER ON 805
B 31 IN LATCHED_BACKFEED_CUT BV_5VDUAL_MBT3904DUAL5
DRAIN AND SOURCE 2 B
80 10K 5%
100
402 CH
1 XSTR
4 1
R178BV
4.7K
Q18BV_PIN3
5%
EMPTY
402
2
BV_5VDUAL_BACKFEED_CUT_L
BOM NOTE: 3
Q18BV
Q18BV_PIN1 FET
STUFF FOR WAKE FROM S3 ONLY
IF STUFFED EMPTY R105BV, R103BV
78 IN SLP_SUS 1 R38BV 2 1
2
0 5%
402 EMPTY
BOM NOTE: 1
C67BV
EMPTY IF .1UF
DESIGN NOTE: 20%
WAKE FROM STBY IS NOT SUPPORTED 25V
2 EMPTY
DEFENSIVE DESIGN 603
A A
[PAGE_TITLE=VREG: USB/5VDUAL PCH/NCH]

hc_cdb_mpi.sch_1.96
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

D
D
C C
B B
A A
hc_cdb_mpi.sch_1.97
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

C79BU
1 2
CAD NOTE:
.1UF 20% EMI CAPS BOARD GENERAL DCPL CAPS
25V PLACE CLOSE BP AUDIO CONN
EMPTY C104BU
603 VCC VCC3 CAD NOTE:
AUD 60 59 58 57 56 55 54 31 IN 5VDUAL 1 2
C86BU 112 104 98 96 90 84 66 BP USB
1 2 PLACE NEAR THE JA1LN
D 0.1UF 20%
16V VCC3
Y5V D
112 96 95 0.1UF 20% 402 5VDUAL
44 32 31 30 IN V_5P0_A 16V
Y5V C109BU
C288BU
OUT 31 54 55 56 57 58 59 60 66 84 90
94 89 78 77 1 2 1 2 96 98 104 112
402
VCC
.1UF 10%
1 C169BU 0.1UF 20% 10V
22UF DESIGN NOTE: 16V X5R
20.0% Y5V 402
25V C178BU 402
GNR BULK DCPL C110BU
ELEC 1 2 1 2 C15BU
2 RDL C102BU 1 2
"THMNT ALUM ELEC" 106 104 103 98 93 92 51 44 41 40 11 10 IN V_1P05_PCH 1 2
116 113 112 107 0.1UF 20% 0.1UF 20% .1UF 20%
16V 16V 25V
0.1UF 20% Y5V Y5V Y5V
16V 402 402 C106BU 603
-12V Y5V 1 2 C112BU C8BU
402 1 2 1 2
C73BU
VCC3
C15EV 0.1UF 20% .1UF 20%
2 1 113 112 107 106 104 103 98 93 92 16V 0.1UF 20% 25V
CAD NOTE:
CAD NOTE: 40 11 10 IN V_1P05_PCH 1 2 C107BU Y5V 16V Y5V
51 44 41 1 2 402 Y5V 603
.1UF 20% 116 C115BU 402
25V PWR CONN 0.1UF 20% C7BU
EMPTY
AZ HDR EMI CAPS 16V 1 2 C116BU 1 2
603
VCC3 PLACE NEAR J7AU Y5V 0.1UF 20% 1 2
402 16V .1UF 20%
0.1UF 20% Y5V 25V
C 16V 402 0.1UF 20% Y5V C
C25BU Y5V 16V 603
1 2 402 Y5V
402
VCC3 VCC3 1
C5BU
2
.1UF 20%
25V
EMPTY .1UF 20% DESIGN NOTE:
VCC VCC3 603 25V
C70BU 2 2 Y5V
C85BU C92BU 603
1 2
1
C69BU
2 1
.1UF
10%
16V
X7R 1
.1UF
10%
16V
X7R
STITCHING CAPS
0.1UF 20% 402 402
16V .1UF 20%
Y5V 25V
402 EMPTY
603 C117BU
116 115 110 V_3P3_STBY\G 1 2 V_3P3_STBY\G 116
81 80 79 78 77 74 52 51 49 41 36 35 18 IN 18 35 36 41 49 51 52 74 77 78 79 80 81 82
106 104 102 98 95 94 93 92 91 83 82
IN 83 91 92 93 94 95 98 102 104 106 110 115
0.1UF 20%
16V
Y5V
VCC 402
+12V 1
C48BU
VCC3 1UF
VCC 10%
B +12V 6.3V VCC VCC3 B
2 X5R
402 C65BU
VCC 2 5VDUAL 1 2
1 C90BU 1 C91BU C149BU 66 60 59 58 57 56 55 54 31 IN
C243BU 0.1UF 100UF 2 1 2 112 104 98 96 90 84
.1UF 20% 20% 2 C80BU
10% 16V 16V C19BU .1UF 0.1UF 20%
2 10V 1 Y5V ALUM .1UF 10% .1UF 20% 16V
C159BU 2 X5R 402 2 RDL 20% 16V 25V C63BU Y5V
.1UF 402 1 25V 1 X7R EMPTY 1 2 402
10% Y5V 402 603 CAD NOTE:
16V 603 0.1UF 20% C66BU
1 X7R 16V
402 GNR DCPL 1 2
Y5V
402
VCC3 0.1UF 20%
C77BU 16V
1 2 Y5V
402
.1UF 10%
10V
X5R
402
C95BU 116 115 110 106 104 102 V_3P3_STBY\G C67BU 5VDUAL
1 2 1 2
79 78 77 74 52 51 49 41 36 35 18 BI BI 31 54 55 56 57 58 59 60
98 95 94 93 92 91 83 82 81 80 66 84 90 96 98 104 112
.1UF 10% 0.1UF 20%
10V 16V
X5R Y5V
VCC3 VCC3 CAD NOTE: 402 402
C118BU
A STITCH CAPS FOR PCIE CLOCKS 1 2 A
C164BU
1 2
.1UF 10%
VCC3 10V V_CPU_VCCIO_RIGHT
.1UF 10% IN 10 11 107 113
2 2 10V X5R
C61BU C62BU X5R 402
.1UF .1UF 402
10% 10% 1
VCC 16V 16V C68BU
1 X7R 1 X7R VCC3 4.7UF
402 402 10%
6.3V
C56BU 2 EMPTY
1 2 C49BU 603
112 104 98 96 90 1 2
57 56 55 54 31 5VDUAL
84 66 60 59 58
IN
0.1UF 20% 0.1UF 20%
16V 16V
Y5V Y5V
402 402 [PAGE_TITLE=VREG: DECOUPLING AND STITCHING]
hc_cdb_mpi.sch_1.98
INTEL
2 1
8 7 6 5 4 3 2 1
MODULE REV DETAILS

V_3P3_PORT80
99 IN
D 1 1 1 1 D
R91BU R103BU R104BU R106BU
10K
5% 10K 10K 10K
5% 5% 5%
EMPTY
99 V_3P3_PORT80 U2BU 402 EMPTY EMPTY EMPTY
IN 2 402 402 402
MAX6958 2 2 2
V_3P3_EC 1 R79BU 2 V_3P3_PORT80
REV=1 LED_SEG0 105 104 103 102 100 IN OUT 99
16 VP DIG0/SEG0 4 99 .002 1%
OUT
LED_SEG1 2010 CH
DIG1/SEG1 5 99 VCC3 1 1 1
OUT C43BU C47BU C42BU
SMB_DATA_EC 1 6 LED_SEG2
0.1UF
20%
0.1UF
20%
10UF
20%
104 102 BI SDA DIG2/SEG2 OUT 99
1 R89BU 2 16V 16V 6.3V
SMB_CLK_EC 2 Y5V 2 Y5V 2 X5R
104 102 BI 2 SCL DIG3/SEG3 7 LED_SEG3 OUT 99 .002 1% 402 402 603
2010 EMPTY
SEG4 11 LED_SEG4 OUT 99
9 INPUT1 SEG5 12 LED_SEG5 OUT 99

DESIGN NOTE: 13 LED_SEG6
SEG6 OUT 99
10 INPUT2
14 LED_SEG7
C PIN 9 AND 10 ARE SEG7 OUT 99
C
NO CONNECT FOR 6958 SEG8 15 LED_SEG8 99
OUT
SEG9 3 TP_LED_SEG9
8 GND
IC
LED_SEG3
99 IN
LED_SEG2
99 IN
LED_SEG1
99 IN
99 IN LED_SEG0
B B
5
3
8
5
3
8
5
3
8
5
3
8
DS1EV DS2EV DS3EV DS4EV
D24357-001
DP
CT
DP
CT
DP
CT
DP
CT
COM
COM
COM
COM
DIGIT0 DIGIT1 DIGIT2 DIGIT3
G
G
C
D
C
D
C
D
C
D
A
B
A
B
A
B
A
B
E
F
F
7
6
4
2
9
10
7
6
4
2
9
10
7
6
4
2
9
10
7
6
4
2
9
10
1
LED_SEG8
A 99 IN A
LED_SEG7
99 IN
LED_SEG6
99 IN
LED_SEG5
99 IN
99 IN LED_SEG4
99 IN LED_SEG3
99 IN LED_SEG2 [PAGE_TITLE=PORT 80 DISPLAY]
99 IN LED_SEG1
99 IN LED_SEG0 BPAGE DRAWING
hc_cdb_mpi.sch_1.99
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-100
8: @HC_CDB_MPI_LIB.HC_CDB_MPI(SCH_1):PAGE100
7 6 5 4 3 2 1
MODULE REV DETAILS

105 104 103 102 100 99 IN V_3P3_EC MODULE NAME REV DATE
EC MODE SELECTION TABLE 102 V_3P3_A

77 67 49 41 32 30 IN
MD2 MD1 MODE 95 94 89 82 81 78
1 R221BU 1 R222BU
3K 10K
D 0 1 ADVANCED (SINGLE CHIP MODE) - DEFAULT 5% 5%
2 CH 2 EMPTY D
1 0 N/A (FLASH MEMORY PROGRAM/ERASE) SW_ON_N 402 402
113 100 64 50 38 IN
116
1 1 EMULATION
103 100
EV_SWITCH_ON_N_EC
IN 50 EV_SWITCH_ON_N 1 R196BU 2 EV_SWITCH_ON_N_EC 100 103
IN OUT
0 5%
402 CH
1 R208BU 2
DESIGN NOTE: 116 113 100 64 50 38 OUT SW_ON_N SW_ON_N_EC
IN 103
SMC MODE SELECTION PIN
0 5%
402 EMPTY
R26BU 1 R209BU 2
104 103 102 100 99 IN V_3P3_EC 1 2 77 37 OUT KBRST_N KBRST_N_EC
IN 104
105 0 5%
10K 5% J1BU 402 CH
603 CH 1X3HDR
BOM NOTE: J1BU_1 1
103 MSEL_MD1_EC 2 R203BU
J1BU: STUFF 1-2 OUT 3 LATCHED_BACKFEED_CUT_EC
96 94 80 31 LATCHED_BACKFEED_CUT 1 2 103
OUT 0 5%
IN
HDR 402 EMPTY
C C
R73BU R204BU
104 103 102 100 99 IN V_3P3_EC 1 2 96 94 80 77 31 OUT BACKFEED_CUT_N 1 2 BACKFEED_CUT_N_EC
IN 103
105 10K 5%
0 5%
J3BU 402 EMPTY
603 CH 1X3HDR
BOM NOTE: J3BU_1 1 R205BU
MSEL_MD2_EC 2 PCH_SYSPWROK PCH_SYSPWROK_EC
103 OUT 113 82 81 38 OUT 1 2 IN 103
J3BU: STUFF 2-3 3 0 5%
402 EMPTY
HDR
R206BU
96 31 VREG_5VDUAL_PCH 1 2 VREG_5VDUAL_PCH_EC 103
OUT 0 5%
IN
402 EMPTY
105 104 103 102 100 99 IN V_3P3_EC

MULTI-BIOS SELECTION TABLE
B B
2 2 2 2 2 SEL1 (J7BU) SEL0 (J28BU) BIOS IMAGE
DESIGN NOTE: R368EV R192BU R167BU R181BU R184BU 0 0 IMAGE 0
1K 1K 1K 1K 1K
5% 5% 5% 5% 5%
PMC_GPIO PULL HIGH
CH CH CH CH CH
0 1 IMAGE 1
DISABLE KSC TIMEOUTS ON BOOT SEQUENCE 402 402 402 402 402
1 1 1 1 1 1 0 IMAGE 2
BIOS_SEL2_R
PMC_GPIO
BOM NOTE: BIOS_SEL0_R 1 1 IMAGE 3
EC_THERM_STRAP BIOS_SEL1_R
J9EV 1-X DEFAULT, 1-2 FOR DISABLE 1 J28BU
1 J7BU 1X2HDR
1 J6BU 1X2HDR HDR
103
100
1X2HDR
HDR DESIGN NOTE:
HDR 2
2
103
100
PMC_GPIO BIOS_SEL2 - ENABLE/DISABLE

103 100 OUT BIOS_SEL0 OUT 104
2
BIOS_SEL1 OUT 104
103 100 OUT EC_THERM_STRAP
BIOS_SEL2 OUT 103
2 2 2 2
2 R143BU
A R194BU R188BU R189BU A
DESIGN NOTE: R109BU 10K
10K 5% 10K 10K
10K 5% 5% 5%
5% CH
EC_THERM_STRAP - CPU THERMAL MONITOR STRAP CH 402 CH CH
CH 402 402 402
ENABLE PECI MONITORING BY 1-X 402 1 1 1 1
1
BOM NOTE:
J2BU 1-X DEFAULT, 1-2 FOR DISABLE
BPAGE DRAWING
[PAGE_TITLE=MULTIBIOS SUPPORT AND EC STUFFING] hc_cdb_mpi.sch_1.100
INTEL DOCUMENT_NUMBER
<DOCUMENT_NUMBER>
PAGE
100
REV
1.0
2 1
CR-101
7 6 5 4 3 2 1
MODULE REV DETAILS

.
D
D
C C
B B
A A
hc_cdb_mpi.sch_1.101
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-102
7 6 5 4 3 2 1
MODULE REV DETAILS

103 102 100 99 V_3P3_EC MODULE NAME REV DATE
TPS3808 PROGRAMMABLE DELAY 105 104
IN
R113BU C16BU DELAY 1

C18BU
0.1UF DESIGN NOTE:
STUFF EMPTY 300MS 20%
16V
2 V_3P3_EC 99 100 102
Y5V J5BU DEFAULT: NORMAL (1-2) OUT 103 104 105
D EMPTY EMPTY 20MS (DEFAULT) 402 REMOTE (1-X) 1 R86BU
1-0 WHEN PROGRAM EC. 100K D
EMPTY STUFF - VARY 1.25MS - 10S 5%
2 CH
U11BU U11BU U11BU U11BU 402
J5BU
74HC04 74HC04 74HC04 74HC04 1X2HDR
105 104 103 102 100 99 V_3P3_EC R116BU
IN 1 2 SMC_INT_CLK1 1 2 SMC_INT_CLK2 3 4 SMC_INT_CLK3 5 6 SMC_INTCLK_N 9 8 SMC_INTCLK_J 2 1 SMC_INITCLK
OUT 103
1M 5%
402 CH IC IC IC IC HDR
R114BU VCC=14 VCC=14 VCC=14 VCC=14
GND=7 GND=7 1
100K C17BU GND=7 GND=7
U3BU 5% VCC=V_3P3_EC VCC=V_3P3_EC 4.7UF VCC=V_3P3_EC VCC=V_3P3_EC
CH U11BU 20%
TPS3808G30 402 3 6.3V
74HC04 Q1BU 2 X5R
REV=1 R115BU FET 402
R117BU
6 VDD RST# 1 SMC_RST_N_D 1 2 11 10 SMC_RST 1
SMC_INT_CLK4 1 2
100 5% 2
402 CH IC 100K 5%
402 CH DESIGN NOTE:
1 1 R113BU VCC=14
C14BU 100K 5 2
0.1UF 5% SENSE GND GND=7 SPARE GATE
10% 3 U11BU
16V 2 EMPTY Q2BU 74HC04
2 X5R 402 FET R118BU
402 103 NMI_GATE 1
4 3 IN 1 2 INVD2 13 12 TP_INVD2
C PS2_CT_R CT MR# 2 C
100 5%
1 OF 1 SMC_RST_N 103
402 CH IC
1 OUT VCC=14
C16BU IC
0.1UF GND=7
10%
16V
2 EMPTY
402
105 104 103 102 100 99 V_3P3_EC 1 R214BU 2 V_3P3_STBY\G 116

18 35 36 41 49 51 52 74 77 78 79 80 81
OUT IN 82 83 91 92 93 94 95 98 104 106 110 115
0 5%
1206 CH
1 R215BU 2 V_3P3_A 30 32 41 49 67 77 78 81 82 89 94 95 100

IN
0 5%
1206 EMPTY
B B
U13BU
AT24C16
3 A2
2 A1
1 A0 103 102 100 99
V_3P3_EC 105 104 103 102 100 99
V_3P3_EC
105 104
IN IN
SMB_CLK_EC 6 5 SMB_DATA_EC 1 R42BU 1 R46BU 1 R53BU R96BU
104 99 SCL SDA 99 104 10K 10K 10K 1
BI 7 BI 10K
H8S_EEPROM_WP WP 5% 5% 5%
V_3P3_EC R48BU 5%
105 104 103 102 100 99 2 EMPTY 1 2 EMPTY 2 EMPTY
IN 8 4 402 10K EC_BRD_ID2 402 402 2 EMPTY
VCC GND
REV_FAB_ID1 5% 103 IN 402
103 IN EC_BRD_ID1
1 R170BU 2 IC 2 CH 103 IN
10K C45BU
.1UF REV_FAB_ID0 402 EC_BRD_ID0
5% 103 IN 103 IN
10%
2 EMPTY
1 10V 1 R49BU 1 R90BU 1 R151BU
402 X5R 10K 10K 10K
402 1 R45BU 5% 1 R47BU 5% 5%
10K EMPTY 10K CH CH
5% 2 5% 2 2
402 402 402
1 R171BU 2 CH 2 CH
A 100 402 402 A
5% DESIGN NOTE:
2 CH
402 EEPROM FOR EC RAM BACK-UP
[PAGE_TITLE=MICROCONTROLLER 1 OF 3
INTEL
2 1
CR-103
7 6 5 4 3 2 1
MODULE REV DETAILS

R174BU
105 104 103 102 100 99
V_3P3_EC 1 2 MODULE NAME REV DATE
IN
0 1A
V_3P0_BAT_VREG R161BU 603 CH
89 79 52 51 50 41 IN 1 2
U1BU
0 1A
603 EMPTY
R4F2113
D Y1BU
100 MSEL_MD1_EC 9 MD1 PA2/KIN10#/PS2AC 39 PA_MSCLOCK
20.000MHZ IN MSEL_MD2_EC 25 38 BI D
1 2 SMC_EXTAL_EC 100 IN MD2 PA3/KIN11#/PS2AD PA_MSDATA
BI
V_BAT_EC 26 VBAT
SMC_XTAL_EC 143 XTAL Mode Selection PA4/KIN12#/PS2BC 37 PA_KBCLOCK
SM
144 35 BI
XTAL EXTAL PA5/KIN13#/PS2BD PA_KBDATA
BI
1 1 103 IN SMC_INITCLK_R 11 NMI PS2
C6BU C57BU 8 34 REV_FAB_ID1
18PF 18PF 103 102 IN SMC_RST_N RES# PA6/KIN14#/PS2CC BI 102
5% 5% 103 102 NMI_GATE 66 PD0/AN8 PA7/KIN15#/PS2CD 33 REV_FAB_ID0 102
50V 50V OUT TP_U1BU_64 64 BI
2 COG 2 COG PD2/AN10
603 603 P95/IRQ14# 19 TP_U1BU_19
110 106 93 81 77 49 SLP_S3_N 50 PF0/PWMU0A/IRQ8# P94/IRQ13# 20 TP_U1BU_20
IN 4 21 TP_U1BU_21
BOM NOTE: 103 115 OUT PCH_RSMRST_N_EC P45/PWMU3B/TCMCKI2/TCMMCI2 Misc. P93/IRQ12#
79 78 RSMRST_PWRGD_N 51 PG7/EXIRQ15#/SCLD
J18EV: STUFF 0-1 OUT 65
100 OUT SW_ON_N_EC PD1/AN9
103 PWRGD_3V_EC 137 P41/TMO0/TCMCKI0/TCMMCI0 P60/KIN0# 78 EC_BRD_ID0 102
SMC_RST_N
OUT 102 103 OUT 62 79 EC_BRD_ID1 BI
103 IN VR_READY_PWRGD_PS PD4/SSO P61/KIN1# BI 102
EC_THERM_STRAP 72 P74/AN4 P62/KIN2# 80 EC_BRD_ID2
J18EV 1 100 IN DDR_THERM_ALERT_N_EC 70 81 TP_U1BU_81 BI 102
1X2HDR
103 IN P72/AN2 Platform Power P63/KIN3#
77 38 LPCPD_N 132 P83/LPCPD# P64/KIN4# 82 TP_U1BU_82
HDR IN 18 83 TP_U1BU_83
KBC_DISABLE_N P96/PHI/EXCL P65/KIN5# DESIGN NOTE:
TP_U1BU_24 24 P90/IRQ2# P66/KIN6# 84 TP_U1BU_84
2 J14BU 1
93 85 TP_U1BU_85 DEFENSIVE DESIGN
1X2HDR
PC1/TIOCB0/WUE9# P67/IRQ7#/KIN7#
103 OUT SPI_SI_EC_R 116 PB4/DSR#/FSIDO
HDR SMB_DATA_THRM 41
C 65 17 BI PA0/KIN8#/SDA1 C
103 IN SPI_SO_EC_R 115 PB5/DTR#/FSIDI P27 96 TP_U1BU_96
2 TP_U1BU_22 22 97 TP_U1BU_97 R193BU
P92/IRQ0# P26 107 82 81 11 VR_READY 1 2
100 EV_SWITCH_ON_N_EC 52 PG6/EXIRQ14#/SDAD P25 98 TP_U1BU_98 113 110
IN VR_READY_PWRGD_PS
IN 99 TP_U1BU_99 0 5% OUT 103
104 103 P24 402 EMPTY
100 99 V_3P3_EC P23 100 TP_U1BU_100
102
IN 1R44BU2 10 Keyboard 101 TP_U1BU_101 R195BU
105
115 94 92 77 38 IN PCH_SLP_M_N R43BU PCH_SLP_M_EC_N PH0/IRQ6# P22 95 89 81 77
PWRGD_PS
1 2
94 38 IN SLP_LAN_N 1 2 402 1K 5% CH SLP_LAN_EC_N 63 PD3/AN11 P21 102 TP_U1BU_102 IN
1K 5% TP_U1BU_92 92 PC2/TIOCC0/TCLKA/WUE10# P20 103 TP_U1BU_103 10K 5%
1 R152BU 103 402 CH 402 CH
10K IN R217BU TP_U1BU_43 43 PF7/PWMU5A/EXRTS P17/WUE7# 104 TP_U1BU_104
5% 96 38 31 SUS_WARNB 1 2 SUS_WARNB_EC 49 PF1/PWMU1A/IRQ9# ME PM P16/WUE6# 105 TP_U1BU_105 1 R216BU
IN 106 TP_U1BU_106 20K
2 CH 0 5%
P15/WUE5# 5%
402 103 IN 402 CH
107 TP_U1BU_107
103 102 IN
NMI_GATE P14/WUE4# CH
SPI_CS0_N_EC_R 113 108 TP_U1BU_108 2
103 OUT PB7/RTS#/FSISS P13/WUE3# 402
100 PCH_SYSPWROK_EC 60 PD6/SSCK P12/WUE2# 109 TP_U1BU_109
OUT 88 110 TP_U1BU_110
100 OUT
LATCHED_BACKFEED_CUT_EC PC6/TIOCA2/WUE14# P11/WUE1#
100 PMC_GPIO 87 PC7/TIOCB2/TCLKD/WUE15# P10/WUE0# 112 TP_U1BU_112
IN 59
BOM NOTE: 100 IN BIOS_SEL2 PD7/SCS
100 OUT VREG_5VDUAL_PCH_EC 57 PG1/EXIRQ9#/TMIY/SCLA L_AD<3..0> BI 38 77
EV: R11BU EMPTY, R99EV STUFF. CRB: DELETE R99EV AND STUFF R11BU. R202BU P30/LAD0 121 0
95 32 30 OUT SLP_SUS_FET2 1 2 SLP_SUS_FET2_EC 89 PC5/TIOCB1/TCLKC/WUE13# LPC P31/LAD1 122 1
CAD NOTE:
0
402
5%
EMPTY P32/LAD2 123 2
P33/LAD3 124 3
B PLACE R11BU NEAR AT EC 103
SPI_CLK_EC_R 114 PB6/CTS#/FSICK P34/LFRAME# 125 L_FRAME_N 38 77
B
BI DDR_THERM_N_EC 46 126 IN
103 OUT PF4/PWMU2A/EXDSR Battery Mgmt. P35/LRESET# PLTRST_N_EC
IN 103
100 BACKFEED_CUT_N_EC 44 PF6/PWMU4A/EXCTS P36/LCLK 127 CK_P_33M_EC_R 103
OUT 128 IN
R201BU P37/SERIRQ SER_IRQ
BI 37 77 79
SLP_SUS_FET 1 2 SLP_SUS_FET_EC 91 PC3/TIOCD0/TCLKB/WUE11# P82/CLKRUN# 131 TPM_CLKRUN_N 77 103 SLP_LAN_EC_N
95 32 30 OUT OUT OUT
EC_PECI
R11BU H_PECI_EC
0
402
5%
EMPTY
1 2 103 SUS_WARNB_EC
10 BI 140 134 OUT
43.2 1% 112 107 106 104 PECI Thermal Mgmt. P85/RxD1/IRQ4# EC_PROG_RX_N
IN 105
402 CH
1
51 44 41 40 11 10 IN
V_1P05_PCH 141 PEVREF P84/TxD1/IRQ3# 133 EC_PROG_TX_N
OUT 105 1
C98BU 17 98 93 92 BI SMB_CLK_THRM 40 PA1/KIN9#/SCL1 P51/FRxD 15 EC_SCIF_RXD_TRANSC
IN 105 1 C183BU
65 116 113 2 16 C184BU .1UF
DESIGN NOTE: 47PF TP_U1BU_2 P43/TMI1/TCMCKI1/TCMMCI1 P50/FTxD EC_SCIF_TXD_TRANSC
OUT 105 .1UF 10%
5% 86 CPU_FAN_CTRL_EC 5 P46/PWMU4B 10%
2 50V OUT 136 RS232 10V 2 10V
C98BU EMPTY PAD PLACEHOLDER EMPTY 86 IN CPU_FAN_TACH P40/TMI0/TCMCYI0 2 EMPTY
EMPTY
402
402 PH1/EXIRQ7# 12 ALS_INTR_N 65 402
TP_U1BU_58 58 OUT
PG0/EXIRQ8#/TMIX/SDAA
REV=1 1 OF 2 IC R147BU
R1BU SPI_SI_EC 1 2 SPI_SI_EC_R
17 DDR_THERM_N 1 2 DDR_THERM_N_EC 103 CAD NOTE: 83 OUT IN 103
OUT IN 0 5%
0 5% PLACE 6677EV AND R678EV NEAR TO EC. OVERLAP R677EV AND R678EV R148BU 402 CH
402 CH 83 IN SPI_SO_EC 1 2 SPI_SO_EC_R OUT 103
R25BU R677EV
1 0 5%
17 DDR_THERM_ALERT_N 1 2 DDR_THERM_ALERT_N_EC 103 CK_P_33M_EC 2 402 CH
A IN OUT 44 IN R150BU 116 A
0 5% 0 5% 103 PWRGD_3V_EC 1 2 PWRGD_3V 13 37 38
402 CH 402 CH IN OUT 77 81 82
DESIGN NOTE: 0 5%
CK_P_33M_EC_R 103 402 EMPTY
OUT R112BU
DDR_THERM_N/DDR_THERM_ALERT_N PROGRAM AS OD/HI-Z OUTPUT
EC 102 IN SMC_INITCLK
100
1 2 SMC_INITCLK_R
OUT 103
SPI_CS0_N_EC_R R119BU SPI_CS0_N_EC
CH
402
EC 103 1 2 83 5% R160BU
R132BU BI BI
PLTRST_N PLTRST_N_EC 0 5% 116 78 38 30 OUT PCH_RSMRST_N 1 2 PCH_RSMRST_N_EC
IN 103
114 82 79 77 67 66 35 BI 1 2 BI 103 402 CH 0 5%
0 5% DESIGN NOTE: 402 EMPTY
402 CH
1 SPI_CLK_EC
R146BU SPI_CLK_EC_R
STUFF R160BU FOR MULTI-BIOS SUPPORT
C181BU 83 BI 1 2 BI 103
.1UF
10% 0 5%
2 10V
EMPTY
402
402 CH
[PAGE_TITLE=MICROCONTROLLER 2 OF 3]
INTEL
2 1
CR-104
7 6 5 4 3 2 1
MODULE REV DETAILS

CAD NOTE: VCC3 MODULE NAME REV DATE
CAP NEED TO PLACED CLOSE TO BUFFER OUTPUT PIN

DESIGN NOTE:
104 H_PROCHOT_N_EC
IN C36BU V_3P3_EC 99 100 102 103 104 105
U4BU 1 2 74LVC1G06 IS OPEN DRAIN IN
R223BU V_3P3_EC
0 74LVC1G06 0.1UF 20%
105 104 103 102 100 99 IN
5% REV=1 16V
D Y5V VCC3
CH 1 NC VCC 5 402 1 R124BU D
402 4.7K
2 5% 1 R125BU 1 R127BU 1 R129BU
A R169BU 2 CH 4.7K 4.7K 4.7K
1 R190BU 100 402 5% 5% 5%
3 GND Y 4 H_PROCHOT_N 10 107
1.50K 1% 2 CH 2 CH 2 CH
1 OUT 1%
402 402 402
1 R191BU CH
R10BU 1 OF 1 2 CH 402 1 R126BU
402 1.50K C51BU 1 R128BU
100K IC 1 1% U1BU VCC3_U1BU_73 1 2 4.7K
5% C50BU 5% 4.7K
CH 47PF 2 CH
R4F2113 .1UF 10% 2 CH
5%
5% 402
10V 2 CH
402 50V 402
2 2 P75/AN5 73 X5R 402 402
NPO
603 102 99 SMB_CLK_EC 14 P52/SCL0 SM BUs P70/AN0 68 EC_5VDUAL 104
BI 17 Power 69 RSMRST_PWRGD_EC_N IN
102 99 BI SMB_DATA_EC P97/IRQ15#/SDA0 Meas. P71/AN1 IN 104
49 38 SML1CLK_PCH 55 PG3/EXIRQ11#/SCLB P73/AN3 71 V_1P05_PCH_EC 104
BI 56 74 EC_12V IN
49 38 BI SML1DATA_PCH PG2/EXIRQ10#/SDAB P76/AN6 IN 104
100 KBRST_N_EC 135 P86/SCK1/IRQ5# P77/AN7 75 EC_5V 104
OUT FRONT_FAN_TACH 138 IN
86 IN P42/TCMCYI1
PE5/ETRST# 27 DBG_PE5
PE4/ETMS 28 DBG_PE4
Debug PE3/ETDO 29 DBG_PE3
Docking PE2/ETDI 30 DBG_PE2
Interface PE1/ETCK 31 DBG_PE1
PE0/ExEXCL 32 DBG_PE0
C P91/IRQ1# 23 TP_U1BU_23 C
100 BIOS_SEL0 48 PF2/TMOY/IRQ10#
R207BU
IN 45
FP_RST_N 1 2
86 OUT FRONT_FAN_CTRL_EC PF5/PWMU3A/EXDTR
116 113 64 50 49 38 10 IN VCC1 1 V_3P3_EC 99 100 102 103 104 105
0 5%
BIOS_SEL1 47 36 IN
402 CH 100 IN PF3/TMOX/IRQ11# VCC2
FP_RST_N_EC 94 86
R130BU PC0/TIOCA0/WUE8# VCC3
78 38 32 30 SLP_SUS_N 1 2 SLP_SUS_N_EC 61 PD5/SSI VCC4 142
IN
10K 5% C29BU
402 13 VCL_U1BU 1 2 116 115 110 106 102 98
104 IN CH R108BU VCL 83 82 81 80 79 1 R110BU 2
1 2 SMC_RUNTIME_SCI_N_EC 119 V_3P3_STBY\G
0 5%
PB1/LSCI 0.1UF 20%
49 41 36 35 18 IN
49 37 SMC_RUNTIME_SCI_N IO_PME_N_EC 129 P80/PME# 78 77 74 52 51 1K 5%
OUT R27BU
402 CH
130 7
16V 95 94 93 92 91
A20GATE_EC P81/GA20 VSS1 Y5V 402 CH
77 49 IO_PME_R_N 1 2 402
OUT
Power and Ground

0 5% TP_U1BU_90
402 CH R131BU 90 PC4/TIOCA1/WUE12# VSS3 42
77 37 OUT A20GATE 1 2 104 OUT RSMRST_PWRGD_EC_N
0
402
5%
CH
Misc. Signal VSS5 95
R210BU TP_U1BU_120 120 PB0/LSMI#
96 38 31 SUS_PWR_ACK 1 2 SUS_PWR_ACK_EC 118 PB2/RI#/PWMU0B VSS7 111
OUT 117 1
0 5% 104 OUT H_PROCHOT_N_EC PB3/DCD#/PWMU1B C60BU
402 EMPTY SLP_S4_N_EC 54 PG4/EXIRQ12#/SDAC VSS9 139 .1UF
10%
R211BU 104 EC_SPI_OE_N_R 53 PG5/EXIRQ13#/SCLC
90 77 38 SLP_S4_N 1 2 OUT 3 2 10V
IN 86 IN REAR_FAN_TACH P44/TMO1/PWMU2B/TCMCYI2 X5R
402
B 0 5% 86 REAR_FAN_CTRL_EC 6 P47/PWMU5B R220BU B
402 CH OUT 77 V_AVREF1_EC V_3P3_EC
AVREF1 1 2
IN 99 100 102 103
0 5%
104 105
402 CH
AVCC1 76 V_3P3_EC 99 100 102 103 104 105 VCC
IN
67 1
SLP_SUS_N_EC AVSS1 C41BU 1 R197BU
104 OUT 0.1UF
20% 1K
16V 1%
2 Y5V 2 CH
1 402 EC_5V 402
C182BU 104 OUT
.1UF
10% 1 1 R198BU
10V C54BU 1K
EC_SPI_OE_N_R 2 EMPTY REV=1 2 OF 2 IC .1UF 1%
104 402 10%
IN 10V 2 CH
V_3P3_EC 99 100 102 103 104 105
2 X5R 402
IN 402
1 V_1P05_PCH 1 R168BU 2
107 106 103 98 93 92 51 44 41 40 11 10 IN
1 R159BU 116 113 112 100 1%
10K V_3P3_EC 402 CH
R158BU 5% 105 104 103 102 100 99 IN
10K CH 96 90 84 66 60 59 58 57 56 55 54 31 5VDUAL
5% 402 112 98
IN
2 1 C28BU 2 104 V_1P05_PCH_EC
A 2 2 2 2 2 OUT +12V A
CH
402
PCH_SPI_OE_N OUT 83 22UF C32BU C22BU C35BU C23BU C24BU C27BU 1 R111BU
20% 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1 1K
2 10V 20% 20% 20% 20% 20% 20% C59BU 1%
3 TANT 16V 16V 16V 16V 16V 16V .1UF
Q3BU 2 SM 1 Y5V 1 Y5V 1 Y5V 1 Y5V 1 Y5V 1 Y5V 10% 1 R199BU 2 CH
1 R153BU 2 FET 402 402 402 402 402 402 104 EC_5VDUAL 402
1 2 10V 3.01K OUT
X5R 1% R120BU
0 5% 2 402 1 1
2 CH C55BU 1K
1 402 CH 104 EC_12V 402 .1UF 1%
OUT 10%
R200BU 2 CH
R154BU 1 1 2 10V
X5R 402
10K C58BU 1K
.1UF 1% 402
5% 10%
EMPTY 10V 2 CH
402 2 X5R 402
2 402
EC_SPI_OE_N
OUT 83
[PAGE_TITLE=MICROCONTROLLER 3 OF 3] BPAGE DRAWING DOCUMENT_NUMBER PAGE REV

INTEL
2 1
CR-105
7 6 5 4 3 2 1
MODULE REV DETAILS

V_3P3_EC
D
104 103 102 100 99 IN J20BU/J23BU CONFIG
1-2* FULL SERIAL FUNCTION(SCIF) D
2-3 EC PROG(SCI)
C173BU
1 2
* = DEFAULT
1 R162BU 0.1UF 10%
10K 16V C174BU
5% 1 R163BU X5R 1 2
2 CH 10K 402
402 5% 1 R164BU 22UF 20%
2 CH 10K 1 R165BU 6.3V
5% 10K X5R
402 U8BU 805
2 CH 5%
402 2 CH 105 EC_U8BU_C1_P 1 C1+ VCC 16
402
OUT J23BU
C78BU 1X3HDR
3 2 1 2
105 IN EC_U8BU_C1_N C1- V+ VP_U8BU_2 1 EC_SCIF_HDR_TXD_TRANSC 105
C81BU 2 TX_OUT IN
0.1UF 10% 1 2 OUT 105
105 EC_U8BU_C2_P 4 C2+ V- 6 VN_U8BU_6 3 PA_COM_TXD2
OUT 16V
IN 105
X5R
5 402 0.1UF 10%
105 IN EC_U8BU_C2_N C2- 16V HDR
X5R
103 EC_PROG_RX_N 12 R1OUT R1IN 13 PA_COM_RXD2 402 105
OUT 9 8 IN J20BU
C 103 OUT EC_SCIF_RXD_TRANSC R2OUT R2IN EC_SCIF_HDR_RXD_TRANSC
IN 105 1X3HDR SERIAL PORT A C
103 EC_PROG_TX_N 11 T1IN T1OUT 14 PA_COM_TXD2 105 1 EC_SCIF_HDR_RXD_TRANSC
IN 10 7 OUT OUT 105
103 IN EC_SCIF_TXD_TRANSC T2IN T2OUT EC_SCIF_HDR_TXD_TRANSC
OUT 105 2 RX_IN 105
GND 15 3 PA_COM_RXD2
IN
1 OF 1 OUT 105
J21BU
REV=1 IC
HDR SERIAL PORT
2X5HDR_10
1 P1
C166BU 2 P2
EC_U8BU_C1_N 1 2 EC_U8BU_C1_P 3
105 OUT IN 105 P3
4
EC_U8BU_C2_N 0.1UF 10% 1 C168BU 2 EC_U8BU_C2_P 5
P4
105 OUT 16V IN 105 P5
X5R 6 P6
402 0.1UF 10% 7
16V P7
X5R 8 P8
402 9 P9
KEY
EMPTY
B B
693286-006
RX_IN FB5BU
105 1 2
OUT
FB
693286-006
FB4BU
105 TX_OUT 1 2
IN
FB
1 1
C96BU C120BU
470PF 470PF
10% 10%
50V 50V
2 X7R 2 X7R
402 402
A CAD NOTE: A
COM-PORT CONNECTOR (J28EV, SERIAL PORT) PLACED
ON WEST EDGE OF BOARD.
[PAGE_TITLE=EC: SERIAL PORT]

INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-106
7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE:
STUFF R123LB FOR LPT, EMPTY FOR INTERPOSER WITH CPT.
D
R123LB V_REFEN3_1P5_PCH D
1 2 106
OUT
0 5%
Q5LB_PIN3 402 EMPTY
R102LB 1
116 V_3P3_STBY\G 1 2 Q4LB_PIN3 3 C66LB
81 80 79 78 77 74 52 51 49 41 36 35 18 IN Q5LB .1UF
115 110 104 102 98 95 94 93 92 91 83 82 2.2K 5% R120LB 20%
FET 16V
402 CH 3 1 2 1 2 Y5V
R105LB 20K 5%
Q5LB_PIN1
2 402
115 110 103 93 81 77 49
SLP_S3_N 1 2 Q4LB_PIN5 5 Q4LB 402 CH
IN XSTR
10K 5% 3904DUAL
402 CH Q7LB_PIN3
4
Q4LB_PIN6
6 3
Q7LB R124LB
R119LB R121LB FET 1 2 V_1P5_PCH
107 104 103 98 93 92 51 44 41 40 11 10
V_1P05_PCH 1 2 Q4LB_PIN2 2 Q4LB 1 2 1 OUT 36 37 40 41 44 51 66 106 114 115
116 113 112
IN XSTR Q7LB_PIN1 10K 5%
10K 5% 20K 5% 2 805 EMPTY
3904DUAL
402 CH 402 CH A98003-001
1
C C
VCC
1
R278BV
5.1K
5% 1
C60BV
CH 1UF
402 10%
R277BV 2 6.3V
VCCIN_VR_ON 1 2 VCCIN_VR_ON_POK 2 X5R
110 107 OUT 402 VCC3
0 5%
402 EMPTY EU10BV
B VCC3 APL5930 1 B
C64BV
R32BV 1UF
6 VCNTL VIN 5 10%
1 2 6.3V
EP 9 2 X5R
22K 5% 7 POK 402
402 CH
V_1P5_PCH OUT 36 37 40 41 44 51 66 106 114 115
R279BV VOUT 3
106 V_REFEN3_1P5_PCH 1 2 V_REFEN3_U14LB_PIN8 8 EN VOUT 4
IN
1K 5%
402 CH R280BV 1 C62BV 1 C63BV R146EV TPEV_V1P5_IN10_DP
1 GND FB 2 V_1P5_VR_FB 1 2 22UF 22UF 2 1
OUT
1
20%
EMPTY
8.66K 1% 20% 5% 0
SYM OPT 1 6.3V 6.3V
402 CH 2 X5R 2 X5R
EMPTY 402
REV=1 IC 805 805
MULTI
M3BV
1 R281BV C61BV R156EV TPEV_V1P5_IN10_DN

10K 1 2
1% 2 1 OUT
402
2 CH 100PF 5% 5% 0
R155EV 402 50V EMPTY 402
TPEV_V1P5_AVMC EMPTY
1 2 402
IN
2
28.7K 1%
402 EMPTY
A A
[PAGE_TITLE=VREG: V_1P5_PCH]

INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-107
7 6 5 4 3 2 1
R7VR2
1
107 10 IN H_VIDSCK_VR
54.9 1%
MODULE REV DETAILS
402 CH EU1VR VCC MODULE NAME REV DATE
V_CPU_VCCIO_RIGHT
107 10 IN H_VIDSOUT_VR 1R19VR
2 IN 10 11 98 113
ISL95818
110 1% REV=1 R142VR
402 CH 107 10 BI H_VIDSOUT_VR 40 SDA VDDP 29 VCCIN_VDDP 2 1
R40VR 107 10 H_VIDALERT_N_VR 1 ALERT* G23026-002 R143VR 1A 0
107 10 IN H_VIDALERT_N_VR 1 2 BI
VCC 107 10 BI H_VIDSCK_VR 2 SCLK VDD 19 VCCIN_VDD 2 1 CH 805
90.9 1%
402 EMPTY 5% 1
D 107 IN VR_VERSION_SEL 37 SELVR12 CH 805 2
R83VR 2
C17VR C67VR D
107 VR_VERSION_SEL 1 2 R108VR 1UF
OUT 1 2 ADDR 39 ADDR 1UF 10%
10K 5% 10% 10V
1 J1VR 10V 1
1X2HDR
402 EMPTY 3.24K
402
1%
CH 1 X5R
X5R
402
402
HDR R109VR
1 2 PROG1 21 PROG1 R144VR
2 BOM NOTE: 590.0 1% VIN 20 2 1 VREG_12V_POWER 89 108 109 110 111
IN
TO DISABLE LL CHANGE R109VR TO 7.87K 402 EMPTY C87VR 1A 0
2 1 CH 805
35 PROG2 .22UF 10% 603 16V X7R AU1_PWM3
PWM3 28
OUT 108
NTCP 107
IN R10VR
1 2 BOOT_2
36 PROG3 BOOT2 34
IN 110
1 21K 1%
2 402 CH J5VR
R84VR 1X2HDR
R116VR
27.4K RT3VR BOM NOTE: 1 2 1 2
1% THRMSTR
THERMISTOR VALUE SHOULD BE 470K 86.6K 1%
CH 402 EMPTY HDR R124VR
402 470K 1 2
2 1 D83604-001 UGATE2 33 CPU_VREG_UGATE2 110
102K 1% OUT
NTCP
402 CH
VREG_SW2_OUT
C NTCN 107 IN 7 NTC PHASE2 32
IN 110 C
1
R91VR R125VR CPU_VREG_LGATE2
3.83K 104 10 OUT H_PROCHOT_N 1 2 VCCIN_VRHOT 6 VR_HOT* LGATE2 30
OUT 110
1% 0 5% R126VR
CH 113 110 103 82 81 11 OUT
VR_READY 402 CH 1 2 VR_PGOOD 4 PGOOD
402 R127VR 0 5% VSSP2 31
2 104 103 98 93 92 51 44 41 40 11 10 V_1P05_PCH 1 2 402 CH 3 VR_ON
116 113 112 106
IN
VCC3 10K 5% R128VR
402 EMPTY 1 2 5 IMON BOOT1 22 BOOT_1 109
VCCIN_VSS_SENSE_IMON
IN
R158VR 110K 1%
603 CH
C86VR
22K 5% 1 2
402 CH
110 107 106 VCCIN_VR_ON 2200PF 10%
IN 50V
X7R CPU_VREG_UGATE1
J2VR R132VR 402 UGATE1 23
OUT 109
VCCIN_VR_ON 106 107 110 1 2 38 SLOPE
1X2HDR OUT VREG_SW1_OUT
1 2 2K 1% PHASE1 24
IN 109
R130VR R131VR 402 CH
HDR 1 2 1 2 8 VW CPU_VREG_LGATE1A
169K 1% 8.06K 1% LGATE1A 26
OUT 109
B 2
C66VR
1 402 CH 402 EMPTY B
C85VR
1 2 C79VR CPU_VREG_LGATE1B
1 2 11 FB2 LGATE1B 27 109
.01UF 10% VCCIN_FB2
OUT
25V X7R 402 1000PF 10%
50V 33PF 5%
EMPTY 50V
402 COG VSSP1 25 ISUMP 108 109 110
402 IN
2 2
1 R153VR
C76VR C77VR 2.67K
DESIGN NOTE:
VCCIN_COMP 9 COMP .033UF .47UF 1%
10% 10% 2 CH
REFER TO LAST PAGE FOR INTERSIL VR (ISL95818) VBOOT TABLE C75VR 16V 6.3V 402
1 X7R 1 X5R 1 R148VR
ISUMP 18 .1UF
10% 402 402 11K 2
R134VR C60VR R145VR 16V 1% C14407-005
1 2 1 2 1 2 X7R RT5VR
402 1 R147VR 2 CH THRMSTR
2K 1% 536 1% 0 402
402 CH 330PF
50V
5% 402 CH 5% UNKNOWN
C78VR COG C74VR R146VR 2 CH 1
1 R133VR 2 402 10 FB ISUMN 17 1 2 1 2 402 ISUMN 107 108 109
VCCIN_FB
IN 110
2
845 1%
1
174.0K 1% R135VR C61VR 1800PF 5%

1500PF 402 CH 1 2 25V 402 CH
1 2
COG 25V COG
603 5% 3.83K 1% 603
C59VR 402 CH 1500PF25V 5% BOM NOTE:
1 2 EMPTY
R136VR 603 R137VR ISEN3 12 ISEN3
A 1 2 1 2
IN 108 RT5VR 10K, C14407-005 A
1.0PF 25% C70VR
50V 2 1
COG 3.65K 1% 20 1%
R138VR 402 603 CH 402 CH
.22UF 10% 603 16V X7R
111 110 109 108 11 10 V_CPU_CORE 1 2 VCCIN_VCC_SENSE 15 VSEN ISEN2 13 ISEN2 110
IN IN
10 1% R139VR J3VR C63VR C71VR
402 CH 1X2HDR 1 2 16 RTN 2 1 ISUMN 107 108 109 110
10 IN VCC_SENSE 1 2 OUT
1 2 .1UF 10% .22UF 10% 603 16V X7R
0 5% 41 GND_EP ISEN1 14 ISEN1 109
R140VR 402 CH 10V IN
HDR EMPTY C72VR C73VR
402 2 1 2 1
IC
10 1% R141VR C18VR
402 CH 1 2 10% .22UF .1UF 10% 402 16V X7R
10 VSS_SENSE 1 2 VCCIN_VSS_SENSE
IN 16V
0 5% X7R
CH 2 1000PF 10% 603
402 C65VR 50V
BOM NOTE:
1000PF
10%
50V
EMPTY
402 [PAGE_TITLE=VCORE VREG]
DEFAULT :J3VR [0-1]
1 X7R BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
402
INTEL
2 1
CR-108
7 6 5 4 3 2 1
MODULE REV DETAILS

D VREG_12V_POWER
111 110 109 107 89 IN D
1 1
R87VR 1
C233VR
1
C7BC
1
C8BC 1
C39VR
1
C12VR C9BC C24VR 1 C56VR
C46VR 2 1 4.7UF 4.7UF 4.7UF 10UF 10UF .01UF .01UF .01UF
VREG_SW3_C47VR 10% 10% 10%
1 2
0 5%
BSZ065N03LS 10%
16V
10%
16V
10%
16V
10% 10% 25V 25V 25V
5 2 X5R 2 EMPTY 2 EMPTY 2 16V
2 16V 2 EMPTY 2 X7R 2 X7R
10% .1UF 402 CH X5R X5R 402 402 402
16V VREG_SW3_CR3VR
D Q4VR 805 805 805 805 805
VCC X7R CAD NOTE:
603
R86VR 1 PHASE RESISTORS: PLACE ALL 0 OHM R8VR
2 U4VR GATE RESISTORS CLOSE TO FET 2 1 4
1 S BSZ065N03LS
2 5% C47VR 0 5% CPU_VREG_UGATE3_Q4VR G IC 5
402 CH ISL6208 .22UF 402 CH 1 Q17VR D
10%
REV=1.0
25V 2
R1VR VREG_12V_POWER_R86VR 5 VCC BOOT 1 2 X7R 3 L5VR
1 2 805
R230VR .37UH
0 5% VREG_12V_POWER_FCCM
6 FCCM UGATE 8 CPU_VREG_UGATE3 1 2 CPU_VREG_HS_GATE3 4 1 2
402 CH G S
0 5% IC EMPTY
107 IN
AU1_PWM3 2 PWM PHASE 7 BOM NOTE: 402 CH 1
2
3 GND LGATE 4 CHANGE R230VR TO A93550-473 3
E48017-001
C 9 GND L3VR C
1 OF 1
.36UH
IC VREG_SW3_OUT 1 2 V_CPU_CORE_R3PI 1 R3PI 2 V_CPU_CORE 111
10 11 107
OUT 109 110
1 .002 1%
BSZ0901NSI 5 BSZ0901NSI 5 IND 2512 CH
D Q35VR D Q36VR R231VR
BOM NOTE: 2.2 1 CAD NOTE:
1 5%
CR2VR EMPTY R232VR PLACE R232VR AND
CHANGE U4VR TO E37835-001 4 MBR140SFT1G 805 0OHM R233VR NEAR INDUCTOR
S SM 4 2 1
G IC
ISL6208CR 2 EMPTY G S
IC CPU_VREG_SNUB3
1 1 1 SM R233VR
2 2 C229VR 2 0OHM
R154VR 4700PF
CPU_VREG_LGATE3 1 2 CPU_VREG_LGATE3_C16VR 3 3 20%
50V
0 5%
CH
2 EMPTY SM
402 2 603 V3P 2
C45VR
4700PF
10%
50V
1 EMPTY
603
R6VR R902VR
B 1 2 1 2 1 R56VR 2 V3N B
0 5% 10K 1% 0 5%
402 CH 603 CH 402 EMPTY
2
C48VR
4700PF
10% 1
50V
1 EMPTY R115VR
603 10
1%
CH
402
2
110
ISUMN 107
OUT 109
ISEN3 107
OUT
1
R117VR
3.65K
1%
A CH A
402
2
110
ISUMP 107
OUT 109
[PAGE_TITLE=VCORE VREG ]
INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
CR-109
7 6 5 4 3 2 1
MODULE REV DETAILS

111 110 108 107 89 VREG_12V_POWER MODULE NAME REV DATE
IN
R82VR
CAD NOTE:
BSZ065N03LS
1 1 1 1
107 OUT
BOOT_1 2 1VREG_SW1_OUT_C907VR
GATE RESISTORS CLOSE TO FET
1
C223VR C11VR
1
C21VR
1
C1BC C2BC
4.7UF
C3BC C14VR 1 C15VR
10UF 10UF 4.7UF .01UF .01UF .01UF
0
402
5%
CH 1
BSZ065N03LS 4.7UF
10% 10% 10% 10% 10%
16V
10% 10% 10%
C907VR Q11VR 5 5 2 16V 16V 16V 2 2 25V
2 25V
2 25V
.22UF 2 16V X5R 2 X5R 2 EMPTY EMPTY EMPTY X7R X7R
D 10% D D Q6VR X5R 805 805 805 805 402 402 402
805
25V D
2 X7R
805 R11VR
CPU_VREG_UGATE1 R224VR 2 1
107 1 2 4 4
IN CPU_VREG_HS_GATE1 G S
IC 0 5% G S
IC L6VR
0 5% CPU_VREG_GATE2
.37UH
402 CH 1 402 CH 1
2 2 1 2
3 3
EMPTY
BOM NOTE: E48017-001
L1VR
CHANGE R224VR TO A93550-473 .36UH
107
VREG_SW1_OUT 1 2 V_CPU_CORE_R1PI 1 R1PI 2 V_CPU_CORE 10 11 107
OUT OUT 108 110 111
1 IND .002 1%
BSZ0901NSI 5 1 2512 CH
BSZ0901NSI 5 R225VR CAD NOTE:
D Q33VR D Q34VR 2.2 R226VR
5% 0OHM
1 EMPTY
1 PLACE R226VR AND
R120VR NEAR INDUCTOR
CR3VR
2
805 R120VR
4 MBR140SFT1G
4 SM 0OHM
G S SM CPU_VREG_SNUB1
2
R2VR IC 2 EMPTY G S
IC 1
CPU_VREG_LGATE1A
1 2 1 1 C221VR
C 107 IN CPU_VREG_LGATE1_C12VR
2 4700PF SM C
0 5% 2 20% R900VR 2
402 CH
3 3 50V V1P 1 2 1 R121VR 2 V1N
2 EMPTY
603 10K 1% 0 5%
2 603 CH 402 EMPTY
C50VR
4700PF
10%
50V
1 EMPTY 1
603
R112VR
10
1%
BOM NOTE: CH
CPU_VREG_LGATE1B R3VR 402
107 1 2 CPU_VREG_LGATE1_C13VR 1 2 110
IN ISUMN
0
402
5%
CH
CHANGE Q33VR & Q34VR TO G21871-001 R119VR
OUT 107
108
3.65K
1%
CH ISEN1
402 OUT 107
2 2
C49VR ISUMP 110
107
4700PF OUT 108
10%
50V
1 EMPTY
B 603 B
A A
[PAGE_TITLE=VCORE VREG]
INTEL
2 1
CR-110
7 6 5 4 3 2 1
MODULE REV DETAILS

D 1
1 1 1 1 C53VR
1 C5BC
C37VR 1 C6BC C52VR
1 10UF D
C16VR C4BC 4.7UF 4.7UF C228VR 10UF 10%
.01UF .01UF .01UF 10% 10% 4.7UF 10% 16V
111 109 10% 10% 10% 16V 10% 2
107 89 VREG_12V_POWER 16V 2 16V X5R
108
IN 2 25V
2 25V
2 25V 2 EMPTY 2 EMPTY 2
16V X5R 805
X7R X7R EMPTY 805 805 X5R 805
402 402 402 805
CAD NOTE:
R85VR BSZ065N03LS BSZ065N03LS
BOOT_2 2 1VREG_SW2_C44VR GATE RESISTORS CLOSE TO FET
5 Q7VR
107 OUT D L7VR
0 5%
402 CH 1 5 .37UH
C44VR
.22UF D Q14VR R18VR 1 2
10% 2 1
25V 4 EMPTY
2 X7R G S
805 R227VR 0 5% CPU_VREG_GATE3 IC
CPU_VREG_UGATE2 1 2 CPU_VREG_HS_GATE2 4 402 CH 1
107 IN G S 2
0 5% IC 3
BOM NOTE: 402 CH 1 L2VR
2 E48017-001 .36UH
CHANGE R227VR TO A93550-473 3 1 2 V_CPU_CORE_R2PI 1 R2PI 2 V_CPU_CORE 10 11 107
OUT 108 109 111
.002 1%
107 VREG_SW2_OUT 1 IND 2512 CH
OUT
1 R229VR
C 5 0OHM 1 C
BSZ0901NSI 5 BSZ0901NSI R228VR
D Q31VR D Q32VR 2.2 R234VR CAD NOTE:
1 5%
SM 0OHM
PLACE R229VR AND
CR1VR EMPTY 2 R234VR NEAR INDUCTOR
MBR140SFT1G 805
SM 4 2 SM
4 2 EMPTY G S CPU_VREG_SNUB2 R901VR 2
G S IC 1 V2P 1 2 1 R105VR 2
R4VR IC 1 C225VR
V2N
107 CPU_VREG_LGATE2 1 2 CPU_VREG_LGATE2_C14VR 1 2 4700PF 10K 1% 0 5%

IN 2 20% 603 CH 402 EMPTY 1
0 5%
3 3 50V
402 CH 2 2 EMPTY
C54VR 603 R104VR
4700PF 10
10% 1%
50V
1 EMPTY CH
603 BOM NOTE: 402
2 ISUMN 109
R5VR 1 OUT 107
1 2 CPU_VREG_LGATE2_C15VR CHANGE Q31VR & Q32VR TO G21871-001 108
R101VR
0 5% 3.65K
402 CH 2 1% ISEN2
C68VR OUT 107
4700PF CH
10% 402
50V 2
1 EMPTY 109
B 603 ISUMP 107 B
OUT 108
VCCIN_VR_ON
OUT 106 107 110
V_3P3_STBY\G 92 93 94 95 98 102 104
IN 18 35 36 41 49 51 52 74
77 78 79 80 81 82 83 91
106 110 115 116
VCCIN_VR_ON
1 R70BV OUT 106 107 110
+12V 22K
R119BV 116 5% 1 R76BV
V_CPU_VCCIO_R119BV 1 2 V_3P3_STBY\G 18 35 36 41 49 51 52 74 77 78 79 80 81 82 2 CH VCC3 22K
IN 83 91 92 93 94 95 98 102 104 106 110 115 402
10K 5% 5%
Q16BV 402 CH 1 R67BV 2 CH
MBT3904DUAL 3 6 8.2K Q15BV_PIN3_2 402
5% 1 R73BV
R123BV 5 2 R120BV 2 CH Q15BV
Q33BV_PIN3_2
1 2 SLP_S3_R120BV 1 2 SLP_S3_N 49 77 81 93 103 106 115
10K
V_CPU_VCCIO_R123BV
IN 402 MBT3904DUAL 3 6 5%
10K 5% 10K 5% 2 CH Q33BV
402 CH 402 CH R69BV Q15BV_PIN5 5
VCC3
R276BV 2 402 MBT3904DUAL 3 6
EN_12V_Q15BV
XSTR 1 2
4 1 1 2
10K 5% R75BV Q33BV_PIN5 5 2
47K 1% 1 2
EN_3V_Q33BV
402 CH
402 CH
4 1 XSTR
A R130BV 1 10K 5% A
1 2 VR_READY 11 81 82 103 107 113 C13BV 402 CH
GSVTT_PWROK_BJT
OUT 0.1UF 4 1 XSTR
100 5% 1 R68BV 10% 1
402 CH 750 16V C15BV
R21BV 5% 2 X5R .1UF
1 2 H_PWRGD 10 38 113
402 1 R74BV 10%
Q13BV H_PWRGD_R21BV
OUT 2 CH 4.7K 2 10V
MBT3904DUAL 3 6 100 5% 402 5% X5R
402 EMPTY 402
2 CH
R127BV 5 2 402
1 2 V_CPU_VCCIO_R127BV
10K 5%
402 CH
4 1 XSTR
R129BV
1 2 V_CPU_VCCIO_R129BV
DESIGN NOTE:
10K 5%
402 CH
SEQUENCING CIRCUIT [PAGE_TITLE=VCORE VREG]
INTEL
2 1
CR-111
7 6 5 4 3 2 1
MODULE REV DETAILS

111 110 109 108 107 11 10

V_CPU_CORE
IN
V_SM OUT 11 16 26 27 28 29 38 90 91 93 111
1 1 1 1 CAD NOTE:
C3VR C4VR C5VR C9VR
22.000UF 22.000UF 22.000UF 22.000UF
D 20% 20% 20% 20% PLACE ALL 0805 CAPS INSIDE
6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R D
805 805 805 805 CPU SOCKET CAVITY
29 28 27 26 16 11 IN V_SM
111 93 91 90 38
108 107 11 10 IN
V_CPU_CORE
111 110 109 1 1 1 1
C69MY C99VR C103VR C102VR 1 C12BV 1 C197BV 1 C5BV 1 C198BV 1 C48BV
22.000UF 22.000UF 22.000UF 22.000UF 560UF 1000UF 560UF 1000UF 1000UF
1 1 1 1 1 1 20% 20% 20% 20% 20% 20.0% 20% 20.0% 20.0%
C131VR C132VR C133VR C101VR C100VR C108VR 6.3V 6.3V 6.3V 6.3V 2.50V 2.0V 2.50V 2.0V 2.0V
22.000UF 22.000UF 22.000UF 22.000UF 22.000UF 22.000UF 2 EMPTY 2 EMPTY 2 2 EMPTY EMPTY EMPTY EMPTY ALUM EMPTY
20% 20% EMPTY 805 2 2 2 2 2
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V 6.3V 6.3V 805 805 805 RDL RDL RDL RDL RDL
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
805 805 805 805 805 805
CAD NOTE: CAD NOTE:
DUAL FOOTPRINT DUAL FOOTPRINT
1 1 1 1 1
C130VR C125VR C124VR C105VR C104VR DESIGN NOTE:
22.000UF 22.000UF 22.000UF 22.000UF 22.000UF
20% 20% 20% 20% 20% 1 THIS CIRCUIT MOVE FROM PAGE 90
6.3V 6.3V 2 6.3V
2 6.3V
2 6.3V C150VR 1
2 X5R 2 X5R X5R X5R X5R 22.000UF 1 1
C152VR 1 C154VR
805 805 805 805 805 20% C151VR C153VR 22.000UF
6.3V 22.000UF 22.000UF 22.000UF
2 20% 20%
C EMPTY 20% 20% 6.3V 1 1 1 1 1 C
805 2
6.3V
X5R 2
6.3V
EMPTY 2 6.3V
X5R
2 X5R C65BV C55BV C56BV C57BV C58BV
22.000UF 22.000UF 22.000UF 22.000UF 22.000UF
1 1 805 805 805 805 20% 20% 20% 20% 20%
1 C119VR C118VR 6.3V 6.3V 6.3V 6.3V 6.3V
C120VR 22.000UF 22.000UF 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY 2 EMPTY
22.000UF 20% 805 805 805 805 805
20% 20%
6.3V 6.3V
2 6.3V
X5R 2 X5R 2 X5R
805 805 805
107
111 110
11 10 IN
V_CPU_CORE
109 108
1 C23VR 1 C30VR 1 C35VR 1 C55VR 1 C62VR 1 C91VR 1 C83VR 1 C82VR

470UF 470UF 470UF 470UF 470UF 470UF 470UF 470UF
20% 20% 20% 20% 20% 20% 20% 20%
B 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V B
EMPTY EMPTY ALUM ALUM EMPTY ALUM ALUM ALUM
2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL
111 93 91 90 38 29 28 27 26 16 11 IN
V_SM
1 1 1 1
108 107 11 10 IN
V_CPU_CORE C65MY
22.000UF
C66MY
22.000UF
C67MY
22.000UF
C68MY
22.000UF
111 110 109 20% 20% 20% 20%
DESIGN NOTE: 6.3V 6.3V 6.3V 6.3V
1 1 2 2 2 2
C115VR C114VR 1 C117VR
1
C116VR
X5R
805
X5R
805
X5R
805
X5R
805
22.000UF 22.000UF 22.000UF 22.000UF CAPS FOR DIMM
20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R
CAD NOTE: 805 805 805 805
PLACE CAPS AT DESIGN NOTE:

TOP SOCKET EDGE CAPS FOR V_SMVREG(EU2BV)
1
C98MY
22.000UF
111 93 91 90 38 29 28 27 26 16 11 IN
V_SM 20%
6.3V
2 X5R
A 805 A
110 109 108 107 89 VREG_12V_POWER

IN 1 C42MY 1 C103MY 1 C102MY
560UF 1000UF
1 C101MY 1 C74MY 1 C73MY 1 C72MY 1 C71MY 1 C70MY
1000UF 1000UF 560UF 560UF 560UF 560UF 560UF
1 C80VR 1 C81VR 1 C90VR 20% 20.0% 20.0% 20.0% 20% 20% 20% 20% 20%
1 1 1 390UF 390UF 390UF 2.50V 2.0V 2.0V 2.0V 2.50V 2.50V 2.50V 2.50V
C230VR C231VR C232VR 20% 20% 20% 2 EMPTY EMPTY ALUM ALUM EMPTY EMPTY EMPTY
2.50V
4.7UF 4.7UF 4.7UF 16V 16V 16V RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 EMPTY
2 EMPTY
20% 20% 20% RDL RDL
ELEC ELEC ELEC
2 16V
2 16V
2 16V 2 RDL 2 RDL 2 RDL
X5R X5R X5R
1206 1206 1206
[PAGE_TITLE=CPU DECOUPLING]
INTEL
2 1
CR-112
7 6 5 4 3 2 1
MODULE REV DETAILS

C133BU MODULE NAME REV DATE
V_1P05_PCH 1 2
106 104 103 98 93 92 51 44 41 40 11 10 IN
116 113 112 107
0.1UF 20%
16V
Y5V
402
VCC3 VCC3 C134BU 104 103 98 93 92 51 44 41 40 11 10 V_1P05_PCH
1 2
116 113 112 107 106
IN
D
0.1UF 20% D
16V
Y5V
C906BU 402
C157BU 1 2
2 1 C144BU
C135BU 1 2
1 2
0.1UF 20%
0.1UF 20% 16V
16V Y5V 0.1UF 20%
0.1UF 20% 16V
Y5V 402 16V C160BU Y5V
402 Y5V V_1P05_ME 1 2
402
92 51 41 IN
402
1UF 10% C146BU
C136BU 6.3V 1 2
1 2 X5R
VCC VCC3 402
0.1UF 20% VCC 0.1UF 20%
16V
16V Y5V
Y5V 402
C902BU C908BU 402
1 2 1 2
0.1UF 20% 0.1UF 20% C900BU

16V 16V 1 2
Y5V Y5V
402 402 0.1UF 20%
16V
C137BU Y5V
1 2 402
C 0.1UF 20% C138BU C
16V 1 2 C901BU
1 2
Y5V
402 0.1UF 20%
16V 0.1UF 20%
Y5V 16V
C904BU 402 Y5V
1 2 402
VCC3
0.1UF 20% C905BU
16V 1 2
Y5V
402 0.1UF 20%
VCC VCC3 16V
Y5V
402
C140BU C175BU
1 2 1 2
C129BU
1 2
1.00UF 20% 0.1UF 20%
VCC3 6.3V 16V
0.1UF 20% X5R Y5V
16V 402 402
Y5V
V_1P05_PCH 116 402
IN 10 11 40 C111BU
104 103 98 93 92 51 44 41 40 11 10 IN V_1P05_PCH VCC VCC3 41 44 51 92 93 98 103 104 106 107 112 113 1 2
B 116 113 112 107 106 C130BU 0.1UF 20%
B
1 2
16V
Y5V
C31BU C38BU 0.1UF 20% 402
1 2 1 2 C251LB 16V
1 2 VCC Y5V
402
0.1UF 20% 0.1UF 20%
16V 16V .1UF 10%
10V C999BU
EMPTY EMPTY 1 2
402 402 X5R
VCC3 402 0.1UF 20%
C34BU C39BU
1 2 1 2 16V VCC3
Y5V
402
0.1UF 20% 1UF 10%
16V 6.3V
Y5V X5R
402 402 C40BU C152BU
1 2 1 2
VCC
C37BU 0.1UF 20%
1 2 .1UF 10%
10V 16V
X5R Y5V C147BU
1UF 10% 402 402 1 2
6.3V
X5R C153BU
402 C44BU 1 2 0.1UF 20%
1 2 16V
59 58 57 56 55 54 31 IN
5VDUAL Y5V
104 98 96 90 84 66 60 .1UF 10% 0.1UF 20% 402
10V 16V
X5R Y5V
A 402 402 C155BU A
1 2
C154BU
1 2
C126BU 0.1UF 20%
1 2 0.1UF 20% 16V
16V Y5V
Y5V 402
0.1UF 20% C132BU 402
16V V_5P0_A 1 2
96 95 94 89 78 77 44 32 31 30 IN
Y5V 98
402 0.1UF 20%
16V 104 103 98 93 92 51 44 41 40 11 10 V_1P05_PCH
Y5V 116 113 112 107 106
IN
402
[PAGE_TITLE=TEST SITE CAPS AND STICHING CAPS]

INTEL
2 1
CR-113
7 6 5 4 3 2 1
MODULE REV DETAILS

BOM NOTE: V_1P05_PCH 10 11 40 41 44 51 92 93 98 103 MODULE NAME REV DATE
IN 104 106 107 112 116
EMPTY FOR HSW
V_CPU_VCCIO_RIGHT VCC3
98 11 10 IN R25PR 1
113 107 110 38 10 IN H_PWRGD 1 2 XDP_PWRGD OUT 113
1K 1% R22PR
CAD NOTE: 402 CH 51
1% 1 R126PR
PLACE TCK/TDI/TMS 1 R4PR CH 249
D 1K 402
1
1
TERMINATION NEAR CPU 1%
1% 2 D
2 EMPTY
R98PR R94PR R96PR R97PR 2 EMPTY 402
51 51 51 51 402 H_TDO OUT 10 113
5% 5% 5% 5%
CH CH EMPTY EMPTY 1 R23PR R129PR
825 1
402 402 402 402 100
1%
CAD NOTE: 1%
2 EMPTY
2
2
PLACE TRST* TERMINATION 402 2 EMPTY
402
H_TCK TERMINATION PLACE NEAR CPU WITHIN 1.1 INCH
ANYWHERE ON ROUTE. CAD NOTE:
H_TDI 10 113
H_TMS
OUT CAD NOTE:
OUT 10 113
H_TCK 10 113 PLACE TDO TERMINATION
H_TRST_N
OUT
OUT 10 113 NEAR XDP CONNECTOR
DESIGN NOTE:
ODT AVAILABLE. DEFENSIVE DESIGN TERMINATION SITES
82 37 10 PLTRST_CPU_N 1 R95PR 2 H_CPURST_XDP_R_N 113

IN OUT
C 1K 5% C
R29PR 402 CH
116 100 64 50 38 OUT SW_ON_N 1 2 XDP_SW_ON_N
IN 113 R15PR
113 11 XDP_PWR_DEBUG1 2 PWR_DEBUG 10 11
0 5% IN OUT
402 CH 0 5%
402 CH
R27PR XDP_VR_READY
110 107 103 82 81 11 OUT
VR_READY 1 2 IN 113
0 5%
402 EMPTY C72PR 20%
R19PR 0.1UF 16V
100 82 81 38 PCH_SYSPWROK 1 2 Y5V
OUT 402
0 5% J2PR
402 CH
XDP_ALT2
V_CPU_VCCIO_RIGHT 43 55
113 107 98 11 10 IN VCC_OBS_AB TCK1
44 VCC_OBS_CD TCK0 57 H_TCK 10 113
52 H_TDO
OUT
TDO IN 10 113
10 H_PREQ_N 3 OBSFN_A0 TRSTn 54 H_TRST_N 10 113
IN H_PRDY_N 5 56 H_TDI OUT
10 IN OBSFN_A1 TDI OUT 10 113
B 0 9 OBSDATA_A_0 TMS 58 H_TMS 10 113 B
11 OUT
1 OBSDATA_A_1
2 15 OBSDATA_A_2 HOOK0 39 XDP_PWRGD 113
17 41 XDP_SW_ON_N IN
3 OBSDATA_A_3 HOOK1 OUT 113
HOOK2 45 XDP_PWR_DEBUG 11 113
21 47 OUT
10 BI TPEV_HSW_XDP_MBP_0 OBSFN_B0 HOOK3 XDP_VR_READY
OUT 113
10 TPEV_HSW_XDP_MBP_1 23 OBSFN_B1 ITPCLK/HOOK4 40 CK_XDP_BCLK_DP 44
BI 27 42 IN
4 OBSDATA_B_0 ITPCLK*/HOOK5 CK_XDP_BCLK_DN
IN 44
5 29 OBSDATA_B_1 RESET*/HOOK6 46 H_CPURST_XDP_R_N 113
33 48 FP_RST_N IN
14 10 BI HSW_PCUDEBUG_<7..0> 6 OBSDATA_B_2 DBR*/HOOK7 OUT 10 38 49 50 64 104 116
7 35 OBSDATA_B_3
GND 1
SMB_DATA_MAIN 51 7 1
116 81 77 29 28 27 26 BI SDA GND C71BU
116 81 77 29 28 27 26 SMB_CLK_MAIN 53 SCL GND 13 0.1UF
BI 4 19 20%
14 10 BI TPEV_HSW_PCUSTB_0_DP OBSFN_C0 GND 16V
14 10 TPEV_HSW_PCUSTB_0_DN 6 OBSFN_C1 GND 25 2 Y5V
BI 10 31 402
14 10 BI HSW_PCUDEBUG_<8> OBSDATA_C_0 GND
14 10 HSW_PCUDEBUG_<9> 12 OBSDATA_C_1 GND 37
BI 16 49
14 10 BI HSW_PCUDEBUG_<10> OBSDATA_C_2 GND
14 10 HSW_PCUDEBUG_<11> 18 OBSDATA_C_3 GND 59
BI 2
GND
14 10 TPEV_HSW_PCUSTB_1_DP 22 OBSFN_D_0 GND 8
BI 24 14
14 10 BI TPEV_HSW_PCUSTB_1_DN OBSFN_D_1 GND
14 10 HSW_PCUDEBUG_<12> 28 OBSDATA_D_0 GND 20
BI 30 26
A 14 10 BI HSW_PCUDEBUG_<13> OBSDATA_D_1 GND A
14 10 HSW_PCUDEBUG_<14> 34 OBSDATA_D_2 GND 32
BI 36 38
14 10 BI HSW_PCUDEBUG_<15> OBSDATA_D_3 GND
GND 50
GND_XDP_PRESENT* 60 PRIVACY_MSR_EN_N 14
OUT
1 OF 1
BOM NOTE:
REV=1 EMPTY
STUFF FOR CRB BOARD

INTEL
[PAGE_TITLE=PRIMARY XDP] hc_cdb_mpi.sch_1.113
Mon Apr 16 13:58:10 2012 CONFIDENTIAL <DOCUMENT_NUMBER> 113 1.0
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1
.
CR-114
7 6 5 4 3 2 1
DESIGN NOTE:
MODULE REV DETAILS
J89LB MODULE NAME REV DATE
MINI_PCIE
OVERLAP RES WITH X1 PCIE (R123CV TO R126CV)
R125CV 51 44 41 40 37 36 V_1P5_PCH 48 +1.5V USB_D+ 38 USB_WLAN_R_DP 114
1 2 115 106 66
IN 6 36 USB_WLAN_R_DN
BI
25 IN HSO5_R_R_DP +1.5V USB_D- BI 114
0 5% 28 +1.5V
R123CV 402 EMPTY 115 114 66 V_3P3_MINI_PCIE SMB_DATA 32
36 IN HSO4_WLAN_DP 1 2 HSO_WLAN_R_DP
OUT 114 IN 41 30
D +3.3VAUX SMB_CLK SMB_DATA_RESUME 20 22 23 24 25 38 66 81
0 5% 39 +3.3VAUX PERST* 22 IN
402 CH
R124CV 10V C150LB 402 52 +3.3VAUX W_DISABLE* 20 D
HSO4_WLAN_DN HSO_WLAN_R_DN HSO_WLAN_R_DP 1 2 W_DISABLE_R583EV.1
36 IN 1 2 OUT 114 114 IN 24 +3.3VAUX
SMB_CLK_RESUME
IN 20 22 23 24 25 38 66 81
.1UF 10% 2 16
R126CV 0 5%
X5R +3.3VAUX UIM_VPP
HSO5_R_R_DN 402 CH UIM_RESET 14
25 IN 1 2 C151LB HSO_WLAN_DP
114 HSO_WLAN_R_DN 10V 1 2 402 HSO_WLAN_DN 33 PETP0 UIM_CLK 12 PLTRST_N

0 5% IN 31 10 IN 35 66 67 77 79 82 103
402 EMPTY .1UF X5R 10% PETN0 UIM_DATA
114 HSI_WLAN_R_DP 25 PERP0 UIM_PWR 8 R257LB
OUT HSI_WLAN_R_DN 23
R129CV 114 OUT PERN0 1 2 V_3P3_MINI_PCIE
66 114 115
25 HSI5_R_R_DP 1 2 44 CK_WLAN_100M_DP 13 REFCLK+ IN
OUT IN CK_WLAN_100M_DN 11 10K 5%
R127CV 0 5% 44 IN REFCLK- 402 EMPTY
402 EMPTY 114 66 WLAN_CLKREQ 7 CLKREQ*
36 OUT HSI4_WLAN_DP 1 2 HSI_WLAN_R_DP
IN 114 IN WAKE_N 1
38 25 24 23 22 20 OUT WAKE*
0 5% 66 49 GND 43
402 CH
R128CV HSI_WLAN_R_DN 114 IN
WPAN_LED_HDR 46 LED_WPAN* GND 37
HSI4_WLAN_DN 1 2 WLAN_LED_HDR 44 35
36 OUT IN 114 114 IN LED_WLAN* GND
0 5% 42 LED_WWAN* GND 29
R130CV 402 CH 27
25
HSI5_R_R_DN 1 2 GND V_3P3_MINI_PCIE
OUT TP_COEX2 5 COEX2 GND 21 115 114 66
0 5% TP_COEX1 3 15 IN
402 EMPTY COEX1 GND
GND 9
TP_BT_RF_KILL 51 RESERVED GND 50 1
37 CLINK_RST_WLAN_N 49 RESERVED GND 40 R258LB
IN CLINK_DATA_WLAN 47 34
C 37 IN RESERVED GND 10K C
37 CLINK_CLK_WLAN 45 RESERVED GND 26 5%
IN 19 18 CH
RESERVED/UIM_C4 GND
17 4 402
RESERVED/UIM_C8 GND 2
WLAN_CLKREQ 66 114
53 MECH_53 OUT
54 MECH_54
55 MECH_55
56 MECH_56
REV=1 CONN
R210LB
1 2
0 1A
603 CH
L3LB
USB_WLAN_DN 2 3 USB_WLAN_R_DN
60 BI BI 114
90OHM
ACM2012 EMPTY
L3LB
60 USB_WLAN_DP 1 4 USB_WLAN_R_DP 114
B BI BI B
90OHM
ACM2012 EMPTY
R212LB 6.0V CR11LB
TVS6V
1 2
0 1A
603 CH
6 1
CAD NOTE:
DO NOT CHANGE TO 402 V_3P3_MINI_PCIE
115 114 66 5 2
OVERLAPPING FOOTPRINTS IN
4 3
EMPTY
D51601-002
J12BU
PCIE_MINI_CLIP
V_3P3_MINI_PCIE
OUT 66 114 115
A 1 A
1 C228LB
NC 0.1UF
J11LB 2 NC 20%
16V
R229LB 1X2HDR
REV=1.0
2 Y5V
V_3P3_MINI_PCIE 1 2 402
115 114 66 IN WLAN_LED_HDR_PWR 1 2 WLAN_LED_HDR OUT 114 HDR
220 5%
402 CH HDR
J90LB
R592LB 1X2HDR
1 2 1 2 WPAN_LED_HDR
220 5%
WPAN_LED_HDR_PWR
OUT 114 [PAGE_TITLE= HALF LENGTH MINI PCI-E]
402 CH HDR BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
2 1
CR-115
7 6 5 4 3 2 1
MODULE REV DETAILS

D L3BV
1UH D
BOM NOTE:
1 2 V_3P3_MINI_PCIE
OUT 66 114
FOR LPT, STUFF R154BV & EMPTY R124BV. EU3BV IND
RT8015A
1 1
REV=1 C98BV C97BV 1 1 R148BV
22.000UF 22.000UF C112BV
20% 20% 0OHM
92 91 90 83 80 77 76 IN V_5P0_STBY\G 8 VDD COMP 10 V_3P3_STBY_COMP_PIN10
6.3V 6.3V 10UF
96 95 94 93 1 R45BV 2 X5R 2 X5R 20%
2
92 91 83 V_3P3_STBY\G 1 805 805 2 6.3V
52 51 49 41 36 35 18 10K C110BV 6 PVDD FB 9 X5R SM
82 81 80 79 78 77 74
IN 1% .1UF
V_3P3_STBY_FB_PIN9
603
104 102 98 95 94 93 1 R191BV1 R43BV 10% 4 1 1 R151BV
2 CH
R46BV 10V IC C113BV 1 7 PVDD
116 115 110 106 10K 10K 402 2 EMPTY 100UF
1 C93BV 3
27.4K
5% 1% 1 2 5 C92BV LX 1%
V_MINI_PCIE_EN_Q10PIN6
402 Q10BV 20% .1UF V_3P3_STBY_LX_PIN3
R154BV 2 EMPTY 2 CH
V_MINI_PCIE_EN_Q10PIN5
6.3V
22.000UF 10% V_3P3_STBY_SHDN_PIN1 1 SHDN/RT 2 CH R149BV
SLP_WLAN_N 1 2 10K 5% 3 2 20% 10V
38 IN 402 402 402 CH X5R 6.3V 2 402
1 R150BV 1 2
49
10K 5% 6 1206 2 X5R
X5R
402 LX 4 221K 698K 1%
402 CH Q10BV 805
2
V_3P3-STBY_FB_PIN7_OPT
GND
V_3P3_STBY_COMP_RC1
V_MINI_PCIE_EN_Q10PIN2 2 1% CAD NOTE: 402 CH

3 1
103 R124BV
Q31BV IC
5 11 C94BV 2 CH
PLACE RESISTOR AND CAP NEAR EU3BV
77 38 IN PCH_SLP_M_N 1 2 PCH_SLP_M_N_Q10BVPIN1 1 1 R44BV 1 PGND EP_GND 1000PF 402
MMBT3904 10K 10%
94 92
10K 5% XSTR R152BV 1 OF 1 50V C95BV
1% 1 2 1 2
402 EMPTY 1 2
2 CH
2 X7R
10K 340K 1% 402
5% 402
402 CH IC 33PF 5%
50V
C 2 CH COG C
402 402
R204BV CAD NOTE:
PLACE IN CRB PORCH
+12V
116 115 110 106 104 VCC3

81 80 79 78 77 74 52 51 49 41 36 35 18 IN
V_3P3_STBY\G 1 R88CV
102 98 95 94 93 92 91 83 82 22K
5%
1 R87CV 2 EMPTY
B 4.7K 402 1 R120CV B
5% 0
3 3
2 CH R119CV Q3CV 1A
402 Q2CV FET 2 CH
Q1CV_PIN3 1 5
2 Q2CV_PIN5
XSTR 1 603
3 10K 5% Q3CV_PIN1
3904DUAL 2
R4CV 402 CH
V_1P5_PCH 1 2 Q1CV_PIN5 5 Q1CV 4 V_3P3_BG
114 106 66 51 44 41 40 37 36 IN OUT 41 51
XSTR
1K 5% 3904DUAL 1 R91CV
402 CH 10K
4 5%
1 R73CV 1 R90CV
2K 51 2 EMPTY
5% 5% 402
Q1CV_PIN6_PIN4
2 CH 2 EMPTY
402 805
Q4CV_PIN3
3
6 Q4CV
R66CV R89CV FET
SLP_S3_N 1 2 Q1CV_PIN2 2 Q1CV 1 2 1
110 106 103 93 81 77 49 IN Q4CV_PIN1
XSTR 10K 5% 2
10K 5% 3904DUAL 402 CH A98003-001
402 CH
1
A DESIGN NOTE: A
LPT EV ENG EXP

CAD NOTE:
PUT INSIDE CRB AREA
[PAGE_TITLE=MINI PCIE VREG]

INTEL
2 1
CR-116
7 6 5 4 3 2 1
113 100 64 50 38 OUT SW_ON_N MODULE REV DETAILS

1 MODULE NAME REV DATE
R247LB
0
5% 116 115 110
R662LB 116 CH 81 80 79 78 77 74 52 51 49 41 36 35 18 IN V_3P3_STBY\G
116 OUT TPEV_XDP_PWRGD_3V 1 2 V_3P3_STBY\G
IN 18 35 36 41 49 51 52 74 77 78 79 80 81 82 402 106 104 102 98 95 94 93 92 91 83 82
1K 5% 83 91 92 93 94 95 98 102 104 106 110 115 2 1 R56LB
1 M313LB 402 EMPTY 20K
D 0 TPEV_XDP_TESTIN_N 116 5%
BOM NOTE: 5% IN
2 CH D
EMPTY M313LB & R662LB 2 EMPTY
R173EV
402
402 J4LB PCH_JTAG_RST_R
116 38 IN
XDP_PCH_HASWELL 2 1 PCH_GP49 37 52
0
IN
5% R172EV
USB_OC0_R_N R271EV CH 402 2 1 SATA4GP
36 IN 37 49 66
IN USB_OC1_R_N R268EV
2 1 PCH_NOA_0 9 NOA_0 NOA_13* 30 PCH_NOA_13
R171EV 5%
36 IN 2 1 5%
CH
0
402 PCH_NOA_1 11 NOA_1 NOA_12* 28 PCH_NOA_12
1 2 CH 402
0
PCH_GP37 BOM NOTE:
USB_OC2_R_N R241EV 0 IN 37 52 J13LB
36 IN 2
5%
1 CH 402 PCH_NOA_2 15 NOA_2 NOA_11* 18 PCH_NOA_11
R170EV 0 5% 1X3HDR
USB_OC3_R_N R220EV 5% 0 17 NOA_3 NOA_10* 16 2 1 402 CH R176EV PCH_GP36 37 52 DEFAULT JUMPER OPTION IS PIN 1-2
36 IN 2 1 CH 402 R219EV PCH_NOA_3 PCH_NOA_10
2 1 IGC_EN_N IN J13LB_PIN1 1
36 USB_OC4_R_N 5% 0 R215EV 2 1 PCH_NOA_4 27 NOA_4 NOACLK1 4 PCH_NOA_NCLK1 5% 0 R182EV IN 38 52 2
IN CH 402
R214EV 2 1 5% 0
29 NOA_5 5 CH 402
2 1 2X4_POWER_DETECT
35 89
36 USB_OC5_R_N
CH 402 PCH_NOA_5
NC 5% 0 IN 3
IN R213EV 2 1 CH
5% 0
402 PCH_NOA_6 33 NOA_6 5% 0 CH 402
USB_OC6_R_N 2 1 5% 0
36 IN CH 402 PCH_NOA_7
35 NOA_7 NOACLK2 6 PCH_NOA_NCLK2 CH 402 R175EV 1 HDR
IO_PME_N 5%
CH
0
402
PCH_NOA_8 10 NOA_8 NC 3 2 1 PCH_SMI_N 38 49 C75LB
49 36 IN SATA0GP R158EV
PCH_NOA_15
IN 1.00UF
49 37 1 2
PCH_NOA_9 12 NOA_9 NOA_15* 36 R174EV 5% 0 20% 1 R87LB
IN NOA_14* 34 PCH_NOA_14 2 1 CH 402
PCH_GP18
IN 38 6.3V 10K
R160EV 2 EMPTY 5%
SATA1GP
0 5%
CH 1 2
40 1P05V_CORE 5%
0
402
52 49 37 IN 402
2 CH
42 NC XDP_PRESENT* 60 CH 402
SINAI_JTAG_VREF 0 5% 402
116 IN 402 CH R360LB
45 NC 3P3V_SUS 43 110 115 116
PROC_VTT_V_3P3_STBY 1 2 V_3P3_STBY\G
IN 18 35 36 41 49 51 52 74 77 78 79
47 NC 3P3V_SUS 44
0 5% DESIGN NOTE: 80 81 82 83 91 92 93 94 95 98 102 104 106
402 CH
C 113 81 77 29 28 27 26 SMB_DATA_MAIN 51 SDA GND 1 DEFENSIVE DESIGN C
BI "NO CONNECT"
113 81 77 29 28 27 26 BI SMB_CLK_MAIN 53 SCL GND 2
GND 7 R325LB
116 TPEV_XDP_PWRGD_3V 39 RSMRSTB GND 8 1 2
IN TPEV_H_CPURST_XDP_HDR
116 IN 46 PCH_PWROK GND 13 0 5%
TPEV_XDP_DBR_N 48 DBR*/SYSRESET GND 14 402 CH
116 OUT
116 OUT TPEV_XDP_TESTIN_N 41 BP_PWRGD_RST GND 19
V_1P05_PCH C290LB
GND 20 103 98 93 92 51 44 41 40 11 10 IN 2 1
116 113 112 107 106 104
116 38 PCH_JTAG_TDO 52 TDO GND 25
IN PCH_JTAG_TDI
U4CV .1UF 10%
116 38 OUT 56 TDI GND 26
10V
116 38 OUT PCH_JTAG_TMS 58 TMS GND 31 DESIGN NOTE: 74AUP1G17 X5R
116 PCH_FILTER_TCK 57 TCK GND 32 402
OUT
PCH_JTAG_RST_R 1
R512LB
2
PCH_TRST 54 NC GND 37 PCH JTAG 1 NC VCC 5
116 38 OUT GND 38
R336LB
0 5% 21 NC GND 49
116 PCH_FILTER_TCK 1 2 TPEV_SCMT_TRGR1_TCK 2 A PCH_JTAG_TCK_FILTER 38
402 EMPTY 22 NC GND 50 IN OUT
0 5% R370LB
23 NC GND 59 402 EMPTY 3 GND Y 4 1 2
24 NC 1 R134LB TPEV_SCMT_TRGR4_TCK
143 1% 1 R149LB
55 NC 51 1 OF 1 51 1
5%
402 EMPTY
5%
C143LB
REV=1 IC 0.1UF
REV=1 CONN 2 CH 2 CH 20%
402 402 16V
2 EMPTY
402
B B
CAD NOTE:
PLACE R149LB CLOSE TO PCH

98 95 94 93 92 91 83
52 51 49 41 36 35 18 V_3P3_STBY\G
82 81 80 79 78 77 74
IN DESIGN NOTE:
116 115 110 106 104 102
J8PR
1X3HDR
R149LB TO CHANGE TO 1KOHM WHEN 74AUP1G17 IS USED
1 R269LB
116 IN TPEV_XDP_DBR_N
FP_RST_N
1
2
(R370LB AND R336LB AND U4CV IS STUFF)
1 R364LB 1 R148LB 113 104 64 50 49 38 10 OUT
200 10 XDP_DBRESET_N 3
1% 200 200 IN
1% 1%
2 CH 2 CH 2 CH HDR
402
402 402 BOM NOTE:
116 38 PCH_JTAG_TDO XDP_DBR/FP_RST HEADER: DEFAULT JUMPER (0-1)
IN
116 38 PCH_JTAG_TDI R244LB
IN 103 78 38 30 IN
PCH_RSMRST_N 1 2 TPEV_XDP_PWRGD_3V
OUT 116
116 38 PCH_JTAG_TMS
IN 1K 5%
SINAI_JTAG_VREF 402 CH
116 OUT R246LB TPEV_H_CPURST_XDP_HDR
103 82 81 77 38 37 13 IN
PWRGD_3V 1 2 OUT 116
A 1 R363LB 1 R362LB 1K 5% A
1 R361LB 402 CH
100 100
1% 100 1%
1%
113 112 107 106 104 R681LB 2 CH
2 2 CH 106 104 103 98 93 92 51 44 41 40 11 10 V_1P05_PCH
51 44 41 40 11 10 V_1P05_PCH 1 2 402 CH 402 116 113 112 107
IN
103 98 93 92
IN 402
116 0 5%
402 CH 1
C239LB
.1UF
10%
10V
2 X5R
402
CAD NOTE:
PLACE R364LB, R361LB, R148LB, AND R362LB CLOSE TO PCH [PAGE_TITLE= PCH XDP]
PLACE R269LB AND R363LB CLOSE TO PCH XDP CONNECTOR BPAGE DRAWING DOCUMENT_NUMBER PAGE REV
INTEL
2 1
CR-117
7 6 5 4 3 2 1
MODULE REV DETAILS

BOM STUFFING INFO MODULE NAME REV DATE
NOTE: THIS PAGE CONTAINS SPECIAL BOM STUFFING CHANGES ON SPECIFIC BUILD
PLEASE REFER TO WORK ORDER NUMBER (WO#) FOR RESPECTIVE INFORMATION
D
AFFECTED D
WO# DESCRIPTION REFDES
ISL95818 BOM STUFFING TABLE

REV 1.0 REV 1.0
REFDES (1.75VBOOT) REV 2.0 (1.70VBOOT)
R119VR 3.65K 3.65K 3.65K
R128VR 22.10K 110K 22.10K
R124VR 0.00K 102K 0.00K
R10VR 24.90K 21.00K 11.50K
10.00K 10.00K
R132VR (EMPTY) 2.00K (EMPTY)
C C
R108VR 0.00K 3.24K 0.00K
10.00K 10.00K
R130VR 169K
(EMPTY) (EMPTY)
R145VR 1.05K 536OHM 1.05K
R131VR STUFF EMPTY STUFF
C85VR STUFF EMPTY STUFF
R116VR 9.09K EMPTY 54.90K
R109VR 590OHM EMPTY 590OHM

B B
R83VR 10.00K EMPTY 10.00K
C86VR 0.01UF 2200PF 0.01UF
C75VR - 0.1UF -
C78VR - 1500PF -
R133VR - 174K -
ISL95818 REV 01 (G23026-001) TABLE (1.75VBOOT) ISL95818 REV 02 (G23026-002) TABLE ISL95818 REV 01 (G23026-001) TABLE (1.70VBOOT)
C61VR - EMPTY -
J1VR J5VR MODE VBOOT R116VR R10VR J5VR VBOOT J1VR J5VR MODE VBOOT
0-1 1-2 VR12 0V N/A 28.7K 0-1 0V 0-1 0-1 VR12 1.10V
0-1 0-1 VR12 1.1V N/A 24.9K 0-1 1V 0-1 1-2 VR12 1.00V
A A
1-2 0-1 VR12.5 1.75V N/A 21.0K 0-1 1.75V 1-2 0-1 VR12.5 1.75V
1-2 1-2 VR12.5 1.0V 86.6K 21.0K 1-2 1.85V 1-2 1-2 VR12.5 1.70V
(DEFAULT) (DEFAULT)
BOM NOTE:
ERB STUFFING : 1.1V
J1VR HAS NO STUFFING EFFECT FOR REV 02 VBOOT DEFAULT MUST BE 1.7V
MPI STUFFING : 1.75V
DEFAULT CONFOG IS 1.75V ABOVE TABLE IS BASE ON REV1.0 ISL95818 (G23026-001)
DESIGN NOTE: TABLE OF VBOOT VS JUMPER STUFFING FOR EACH REV ARE TO BE UPDATE
TABLE OF VBOOT VS JUMPER STUFFING FOR EACH REV ARE TO BE UPDATE
ABOVE TABLE IS BASE ON REV1.0 ISL95818 (G23026-001)
[PAGE_TITLE=BOM STUFFING INFO]

INTEL
8 7 6 5 4 3 2
CUSTOM TEXT BPAGE
1

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CR-1 :

COMPONENT/FUNCTION COMPONENT/FUNCTION PAGE # COMPONENT/FUNCTION REVISIONS

[43. PCH 6] [91. VREG: V_SM_VTT] BOM_RELEASE_DATE PB_NUMBER

MODULE REV DETAILS

MODULE REV DETAILS

BPAGE DRAWING DOCUMENT_NUMBER PAGE REV

MODULE REV DETAILS

BPAGE DRAWING DOCUMENT_NUMBER PAGE REV

PCH MODULE REV DETAILS

[PAGE_TITLE=GPIO, IRQ, IDSEL MAP]

MODULE REV DETAILS

MODULE REV DETAILS

DDID_TXD[2] B17DDI3_TX2_DP OUT 65

MODULE REV DETAILS

MODULE REV DETAILS

11 10 V_CPU_VCCIO_RIGHT CAD NOTE: DESIGN NOTE: MODULE REV DETAILS

HSW_CFG_RCOMP H_PWRGD 10 38 110 113

0 1A A29 VCC VCC J28 R163CV 10K 5%

MODULE REV DETAILS

MODULE REV DETAILS

MODULE REV DETAILS

ENG FEATURE: NOA STRAPS

MODULE REV DETAILS

36 6 DMI_IT_MR_1_DP 19 C6+ C7+ 22 DMI_IT_MR_0_DP 6 36

REMOVE THIS FOOTPRINT FROM THE SECONDARY SOLDERPASTE LAYER

Vinafix [PAGE_TITLE=DMI LAI]

MODULE REV DETAILS

111 93 91 90 38 29 28 27 26 16 11 V_SM 1 R1UB 2

MODULE REV DETAILS

[PAGE_TITLE=DIMM VREFS & THERMAL SENSOR] BPAGE DRAWING

MODULE REV DETAILS

116 115 V_3P3_STBY\G

MODULE REV DETAILS

BOM NOTE: BOM NOTE: C92281-003

VCC3 +12V +12V

21 IN EXP_A_TX_1_C_DP B19 HSOP1 RSVD A19 TP_3G16RSVD_A19

C53BU CAD NOTE:

MODULE REV DETAILS

[PAGE_TITLE=PCI EXPRESS X16 COUPLING]

MODULE REV DETAILS

ATX EXPANSION SLOT 4

PLACE NEAR SLOT +12V

MODULE REV DETAILS

ATX EXPANSION SLOT 5

C J17BU +12V VCC3 C

MODULE REV DETAILS

ATX EXPANSION SLOT 6 1

J13BU +12V VCC3

[PAGE_TITLE=PCI EXPRESS X1 #3]

+12V MODULE REV DETAILS

C1CV PCI EXPRESS

C2CV B8 3.3V JTAG5 A8 TP_PCIE_JTAG5_4

36 22 HSI8_DP 1 R46CV 2 EXP_B_RX_0_DP

8 89 A8/A7 DQ52 164 52

136 DM4 DQ15 36 15

DO NOT PUNCH VIA.

4 137 DQS4 DQ2 15 2

PLACE BETWEEN CHA & CHB.

26 GND VDD 100

38 GND VDD 112

44 GND VDD 118

48 GND VDD 123

49 GND VDD 124

179 GND NC 122