SMALL PROJECTS 1. 2. 3. 4. 5. 6. 7. Design and layout a 3-input NAND gate, a 3-input NOR gate.

Design and layout the circuit doing function: Y = ( A + B)C + D . Design and layout a half adder Design and layout a full adder. Design and layout an 8-bit ripple adder. Design and layout a simple differential amplifier. Design and layout a 6- Transistor SRAM Cell.

VLSI Lab Tutorial 1

Cadence Virtuoso Schematic Composer Introduction 1.0 Introduction The purpose of the first lab tutorial is to help you become familiar with the schematic editor, Virtuoso Schematic Composer. You will create a schematic and a symbol for a static CMOS inverter. After completion of this tutorial, you should be able to: - Insert instances into your design - Connect instances together using wires - Change instance properties - Name nets - Add pins to your design - Create and edit a symbol cell view - Check and save your design 2.0 Getting Started Please refer Basic Linux Command Manual and Basic Spice manual in advance.

Design flow

3.0 Online Documentation Note that this tutorial and the following series cover only the very fundamental concepts of creating CMOS schematics, symbols and layouts, simulating circuits, performing layout verification and parasitic extraction from layout using cadence. Please refer to the online documentation for additional information. To access the online documentation, type openbook in any LINUX window or click on help in the upper right corner of any cadence window. In the online documentation more detailed information can be found under the Custom IC and Deep Submicron Design category. Under Design entry there are the Virtuoso Schematic Composer Tutorial and Virtuoso Schematic Composer User Guide you may find helpful.

4.0 Virtuoso Schematic Composer Basics The Virtuoso Schematic Composer is used to create the schematic of your design. In the schematic, it will contain devices (transistors) connected together with nets (wire connections).

4.1 Launch Virtuoso Schematic Composer Enter icfb in a terminal window command prompt. In a minute or so, a window should appear with the title icfb at the top. This window is known as the Command Interpreter Window (CIW). It is the main control window for the schematic composer software. Various properties can also be changed in this window.

The CIW displays a running history of the commands that you execute and their results. It also shows status and error messages from the schematic composer software.

When commands are run, the CIW will display prompts for action.

4.2 Setup User Preferences Select Options User Preferences from the top menu and a window named User Preferences appears. Check the boxes named Scroll Bars and Infix. Turning on Infix limits the number of mouse clicks required to execute certain commands as you will learn later in tutorial. Drag the Undo Limit slider 10. Click OK to exit.

4.3 Library Manager The Library Manager allows you to manage (create, copy, move delete) libraries. It is recommended that all changes in the libraries be done here to preserve the integrity of all the files associated with the design. To run Library Manager, click on Tools Library Manager. Cadence uses the term library to refer to both reference libraries, which contain defined components for a specific technology and design libraries, in which you create your own designs. The designs are called cells. Each cell can have multiple representations, such as a symbol or a schematic. These representations are cellviews. There should be several libraries already present in the Library column. Click on any of the libraries. It will list more cells on the Cell column that belongs to this library. You should see a library called gpdk. This will probably be the most often used library for the course, as you will find later on. The cellviews associated with the cell will appear in the View column if you click on any of the cells listed. The pathnames of these libraries are defined in the cds.lib file. The paths can be altered manually with a text editor if required. It is also possible to open designs from the library manager. To do this, right click on the cell view and select Open from the menu that appears or simply double click on the cellview name.

4.4 Creating a New Library To create a new library, click on File New Library (you can do this in either the icfb window or the Library Manager). A new window appears and enter Tutorial in the Name field. Click on Attach to and existing techfile and click OK. The technology file (techfile) stores all the instances, processes and rules files required for schematic and layout design.

A new window should appear asking for a Technology Library. Select gpdk and click OK.

4.5 Creating a New CellView To create a new cell view, click on File New Cellview (you can do this in either the icfb window or the Library Manager). A window appears and select tutorial for the Library Name field, and type in inverter for the Cell Name. The View Name should be schematic and the Tool field should be Composer Schematic. Click OK when done.

A new window named Virtuoso Schematic Editing: tutorial inverter schematic should appear. This is the schematic window or cellview. Note that the last parts of the window name correspond to the library (tutorial) and the cellview (inverter) that you are currently working on.

Take a look at the command menu on top and the icons on the left. Clicking on the top (drop down) menu will reveal more command options. If there is an arrow to the right of the command option in the drop down menu, it means that there are more options under it. Click on the command option to reveal more options.

Next to certain command options, there are some letters next to it. These are bindkeys (or more commonly known as hot-keys) that invoke the command using simple key presses. They will become handy when you get more familiar with the schematic editor and the bindkeys. The icons on the left correspond to several most frequently used commands such as add instance, change instance properties, add wire, zoom in, zoom out, undo, delete etc. By placing the mouse cursor on top of the icon, the name of the icon appears. A pop up menu appears when you place the cursor on any empty portion of the schematic and press the middle mouse button. The right mouse button repeats the last executed command.

5.0 Drawing a schematic for a CMOS Inverter Now you are ready to draw the schematic of a CMOS inverter as shown below in the illustration. From the figure, you can see that the inverter consists of two transistors (one n-type and one p-type), Vdd and Ground. These are known as instances.

5.1 Adding Instances To add a transistor to your schematic, click on the instance icon. A new window named Add instance appears. There are several other ways to bring up this window. One way is to press the middle mouse button within the cellview, then select Add Instance when the pop-up menu appears. The other way is to select Add Instance from the top menu. In this new window, click on the Browse button just below the Help button. Another new window named Library Browser appears, very similar to the Library Manager window.

In the new window, click on the gpdk library, then select the nmos cell and choose symbol for the cellview. Now move the mouse cursor back to the schematic window and you will find a symbol representing an n-type transistor attached to the cursor. You can rotate or flip the instance (sideways or upside down) by clicking the Rotate, Sideways and Upside Down buttons in the window before placement. If you have accidentally chosen the wrong instance, press the Esc key or click the Cancel button on the Add Instance window.

Move the cursor to a desired location on the schematic window and click the mouse button to put the transistor in place. If you find out that the windows are blocking your view, simply click and drag on the title bar of the window to move them away and continue with the placement. After the placement of the n-type transistor, it will continue to prompt you to add another instance (same instance by default). This will allow you to place multiple instances onto your cellview. Return to the Library Browser and under the same library, select pmos cell and choose symbol for the cellview. Place a p-type transistor in the schematic window. As an exercise, continue to add the remaining instances (VDD and GND) into your cellview from the basic library. Press the Esc key to stop adding more instances. You can simply click and drag the instance around to re-position them on your cellview.

5.2 Editing Instance Properties To modify the properties of an instance, such as the width and length of the n-type transistor, select the n-type transistor and click the Property icon on the left or selecting Edit Properties Objects from the drop down menu. A new window the named Edit Object Properties appears. The Library Name, Cell Name and View Name are displayed near the middle section. Ensure that these values correspond to the right instance before modifying the properties. For the Instance Name field, it can be changed to any value for easy identification between instances. For the CDF Parameters edit the Width to 1u M and the Length to 180n M (u represents micrometers and n represents nanometers). Use the Tab key or mouse to move between fields and do not press the Enter key unless you are done. To edit the properties for another instance, click on the instance and the Edit Object Properties window will be updated to the new instance. Now, change the properties of the p-type transistor such that the width is 2u M (such that the ratio of pmos to nmos is the "rule of thumb = 2") and the length is 180n M.

After done editing, click OK or press Enter to quit. Note that other instance properties can be edited in the same manner.

5.3 Displaying Instance Properties It is possible to make the instance properties that you specified above visible in the schematic. This provides a quick view to the property values that you entered for each instance.

To change the display options, click on Edit Component Display. A new window will appear. In the schematic, click on a component that you want to display values for. In the Component Display window, check the boxes as indicated in the figure below.

Note that when you check the library box, it will cause all symbols from the same library to display the same way so you dont have t repeat this step for each symbol. Also, checking on the Instance Name box under Instance Labels will cause the reference name for the symbol to appear.

5.4 Deleting Instances To delete an instance, click on the instance to be deleted. A box around the instance indicates that the instance is selected. Click the delete icon on the left side of the schematic window or press the Delete key to delete. To delete multiple instances, you can first select multiple instances by pressing the shift key while selecting the instances with the mouse or by holding the left mouse button down and dragging a box, then execute the delete command as above Another way is to execute the delete command, the select the instances that are to be deleted. Note that the delete command will remain active until you cancel the command by pressing the Esc key. This is also true for most other commands.

5.5 Adding Pins To add pins (used to connect your current design to external circuits), either click on the Pin icon, or select Add Pin from the drop down menu. A new window names Add Pin appears. Type In for the Pin Names field. Select input for the Direction tab. Leave other settings at their default state.

Move the mouse cursor back to the schematic window and you will find a symbol representing a pin attached to the cursor, similar to the placing of an instance. You can rotate or flip the symbol (sideways or upside down) by clicking the Rotate, Sideways and Upside Down buttons in the window before placement. As an exercise, add an output pin named Out.

5.6 Adding Wires To add wires to connect the instances together, click on the Wire (narrow) icon on the left. Alternatively, click the middle mouse button within the cellview and select Wire (narrow) in the pop-up. You might have noticed that there is a similar icon named Wire (wide). It is used to create buses. More information regarding creating buses will be discussed further in the next tutorial.

A new window named Add Wire appears. Leave the Draw Mode as route unless you absolutely need t draw non-rectilinear wires. Click on the wire starting point (for example, at the red boxes indicating an instance pin). Move the mouse cursor and click again for each wire segment. You might notice that as you move the mouse cursor, a small diamond shape appears over the connection object closet to the pointer. To end the wire, press s to snap to the nearest object that shows a diamond shape. Another way is to click a schematic pin, an instance pin, or another wire or double click on a new wire endpoint. Finish up the schematic by connecting the instances together with wires. You should now have a schematic similar to the one in the diagram.

5.7 Naming Nets You might have noticed that in the schematic, the input pin is not connected to the schematic. By naming the net (or wire), it is possible to indicate that there is an electrical connection between other nets or pins. This could help in reducing the amount of wire cluttering that makes the schematic hard to read. To name a net, select Add Wire Name from the drop down menu or select Add Name from the pop up menu. A new window named Add Wire Name appears. Type In for the Names field and move the mouse cursor to the net that is to be named In. It is possible to add several names to different nets at one time. To do this, simply type the names separated by a space in the Names field and the names will be added in order when you click on the various nets.

5.8 Checking and Saving a Schematic Once you think that your schematic is complete, you will need a run a check on it. This check only checks for very rudimentary problems (such as unconnected pins or dangling wires) and for many more subtle or obscure problems that may cause trouble later on in programs that try to use your schematic. To check your schematic, click on the Check and Save icon. The results of the check are displayed in the CIW. If everything goes well, you should see a message in the CIW: Schematic check completed with no errors. tutorial schematic inverter saved.

As an exercise, delete a wire segment from your schematic and do a check. A window named Schematic Check will appear indicating the number of errors and warnings found. Click Close. In the cellview, flashing markers highlight the area that is causing the errors or warnings. To understand the cause of errors, select the drop down menu item Check Find Marker. A new window appears showing the list of errors and warnings. Clicking on a particular error and warning from the list will highlight the markers that correspond to that particular error or warning highlighted on the schematic. Click Delete to remove the marker from the cellview There might be situations, for example, where you do not need to use a certain pin on an instance and would just want to leave it floating. The checker will indicate a warning that the pin is floating. To ignore the warning and to prevent it from appearing repeatedly, select the warning from the list and click Ignore. That particular warning will not appear in the next check. To make the warning reappear, click Restore All in the same window. Fix the schematic, do a check and save it.

6.0 Creating and Editing a Symbol for a Schematic At this point, you should have a schematic of a CMOS inverter that passes the check without the errors. You will now generate a symbol for the inverter. From your cellview of your inverter schematic, select Design Create Cellview From Cellview from the drop down menu. A new window named Cellview from the Cellview appears. The window shows entries for the active design, so Library Name should be set to tutorial, Cell name to inverter, and From View Name to schematic. Check to make sure that to View Name is set to symbol and all the above information is correct the click OK. The Symbol Editor window appears, displaying the inverter symbol generated by the schematic composer software. This symbol is functional and can be readily used, but the shape is a simple rectangle and not the conventional inverter symbol.

Note that the icons on the left are slightly different than the ones in the schematic editor window. To draw the new shape, select Add Shape Polygon. Point to the first point of the polygon, followed by the next point until your original starting point and form a triangle. Add a small circle at the apex of the triangle at the output end by selecting Add Shape Circle. Point and click to define the center of the circle and move to size the circle by moving the mouse. Carefully delete the inner box. Do not delete the outside box that runs through the pin squares. Select the top and bottom sides of the outside box and move them out to the points on the triangle (click and drag), so that the entire triangle is inside the box. This box determines the boundaries of the symbol (i.e., determines what area you click on the schematic to select the symbol). The final results should like this.

Check and save the symbol by using the Design Check and Save command from the drop down menu. If you take a look at the inverter cell in the tutorial library, you can see that it now has a schematic cellview and a symbol cellview. Close the Symbol Editor.

Now you have completed a discrete CMOS inverter design, with its own symbol, and the instance parameters as specified. The next step is to perform a simulation on the inverter to verify that it works and to evaluate its performance.

VLSI Lab Tutorial 2

Simulation Using Spectre 1.0 Introduction The purpose of the second lab tutorial is to help you in simulating your inverter design that you designed in the first lab tutorial. You will perform transient analysis and dc analysis for your inverter. We will use a simulator called spectre for our analysis. Upon completion of this tutorial, you should be able to: Simulate your schematic using spectre. Perform transient analysis and dc analysis.

2.0 Schematic to be simulated Use the schematic from Tutorial 1. The schematic consists of one nmos transistor and one pmos transistor (see Tutorial 1), a gnd and a vdd symbol and then an input port IN and and output port OUT. We are now going to add input, output ports (if not added before). You can place these either by pressing the PIN button on the left or by going to Add Pin... Make sure you choose input for IN:

and output for OUT:

Your final schematic should look like this:

Check and save and make sure you don't get any errors or warnings. Assuming there are no errors we are now ready to start simulation!

3.0 SIMULATION In the Virtuoso Schematic window go to Tools Analog Environment. There is going to be another "What's New" pop-up window that you can read and close or minimize. The design should be set to the right Library, Cell and View.

First we need to choose the simulator, we will choose Spectre. Go to Setup Simulator/Directory/Host, and choose Spectre in the pop-up window, then click OK:

Go to Setup Model Libraries and choose (you can type directly or use Browse) the library and then click Add (this is important, don't forget to do it), which adds the models for the NMOS and PMOS, then OK.

First we will perform a transient simulation to see that our inverter works correctly. In the schematic window go to Tools Analog Environment. The design should be set to the right Library, Cell and View. We first need to set up the right simulator (spectre), and then set the two model library files for the nmos and pmos (please revisit Tutorial 1 for the details). We also need to set up inputs and power supply since we don't have explicit voltage sources. Go to Setup Stimuli. Initially you have the Inputs chosen; you should have only one (IN). Click on Enabled, Function pulse, Type Voltage, Voltage1 0, Voltage2 5, Rise time 0.1n, Fall time 0.1n, Pulse width 1n, Period 2n, Source type pulse, and click on Apply. The input should turn from OFF to ON. CAUTION Cadence is very fragile concerning this dialog box, make sure you enter the numbers exactly as above (i.e. no space between the digit and n, etc.). If you get syntax errors later in simulation they are most likely because of this.

Now we need to setup the global sources (power supply). Click on the Global Sources, you should have only one (vdd!). Click on Enabled, Function dc, Type Voltage, DC voltage 5, Source type dc, and click on Apply. The vdd! should turn from OFF to ON. Click OK.

Now you need to choose the type of simulation, go to Analyses Choose... In this case we will choose tran which is the default, 4n as the Stop time (2 periods) and moderate as the accuracy default.

Now go to Outputs Save All and click on allpub for signals to save (default) and all for device currents. Click OK. CAUTION In general, once you have a big schematic, you will want to only save a few signals for simulation, and this will make your simulation faster. For small circuits as we have now it doesn't make a big difference though. Now we can finally simulate! Click on the Netlist and Run button (looks like a green light) on the right or go to Simulation Netlist and Run. Click OK on the Welcome to Spectre window which should start the simulation. In case you have errors you will need to go back and correct them. This can be tricky! You may need to do Simulation Netlist Recreate if you change the schematic. CAUTION Each time you change the schematic you have to do Check and Save!. Assuming there are no errors you can now admire the simulation results. Go to Results Direct Plot Transient Signal which will pop-up your schematic window. Now you have to click on the signals you want to see. Since this is a transient analysis we want to see the input and output voltages. In order to do this you have to click on the input and output nets, then the ESC key. You should finally get the desired simulation results, 2 periodic signals as expected from an inverter.

We are now almost done, before we finish let's try to also plot the VTC for the inverter. For this we first need to replace the IN pin by another vdc power supply from the analogLib library as in Tutorial 1. Change its DC voltage property to 5

Check and Save (make sure you get no errors). Now go to Analyses -> Choose, dc and Component Parameter, Select Component, then the voltage source in the schematic, and then choose 0 as Start, 5 as Stop and 0.2 as step.

Now click on the old tran analysis and then go to Analyses Delete so that you are left with only one Analysis.

Finally do Netlist and Run. If you don't have any errors you can now go to Results Direct Plot DC and click on the output net and the ESC key to get an inverter VTC.

It is a good idea to save your state before exiting the simulator in case you want to redo some of the simulations you can start by loading a saved state. Congratulations, this is the end of Tutorial 2.

VLSI Lab Tutorial 3

Virtuoso Layout Editing Introduction
1.0 Introduction The purpose of this lab tutorial is to guide you through the design process in creating a custom IC layout for your CMOS inverter design. The layout represents masks used in wafer fabs to fabricate a die on a silicon wafer, which then eventually are packaged to become integrated circuit chips. Upon completion of this tutorial, you should be able to: . More information can be found in the online documentation under the Custom IC and Deep Submicron Design category. Under Custom IC Layout, there is the Layout section that you may find helpful. Create a mask layout of the CMOS inverter that you have designed earlier. Check that your layout satisfies the design rules of a 0.18 micron process technology using DRC. Extract a netlist including parasitic resistances and capacitances from the layout. Check that your layout passes the automatic verification against the inverter schematic created earlier.

2.0 Inverter Layout Overview The pictures on the facing page present an inverter layout very similar to the one you are about to create. The only significant difference should be the transistor widths. The inverter you create should have transistor widths matching the values you determined in the tutorial 1. This layout is in the style of standard cells used for automated placement and routing of random logic. This does not, however, mean that this style of layout is bad for custom layout. It has some very useful features. In particular, It is designed so that the multiple instances of the cell can be connected together by abutment (i.e., placed immediately to the left and right of each other). The power, ground, input and output connections line up and will be connected. The layout lends itself to a left to right signal flow in the metal layer (used for the input and output) as well as vertical signal flow for short distances in polysilicon.

If other types of logic cells have the same layout spacing between power and ground, then cells of various types can be chained together easily.

2.1 Design Rules Design rules are a set of rules (usually supplied by the manufacturer) that specify a minimum size or spacing requirements between the layers of the same type or of different types. This provides a safety margin for various process variations, to ensure that your design will still have reasonable performance after your circuit is fabricated. Note that the technology file you specified in the first tutorial (gpdk) defines the design rules that will be used to check your design. It also defines how the drawing layers are translated into masks for the IC. The design rule file used is divaDRC.rul. The following section will discuss about more common design rules.

2.2 Mask Layers The mask layers are the various layers shown in the above diagram and are used to define the location and size of the devices and nets. Each layer can be treated as an individual layer meaning that two different layers have no electrical connection between them even though they happen to overlap. The layers are typically in different colors and shading (displayed in the layer selection window (LSW)-refer to section 3.2) and are defined by the display.drf file. If the layers display the same color, you need the display.drf file. The file display.drf can be found in packages/cadence/cells/generic/gpdk_MIET_2.0. copy this file to your Cadence running directory using the following command and exit and run icfb again: cp /packages/cadence/cells/generic/gpdk_MIET_2.0/display.drf ./ Diffusion areas for source, drain and substrate contacts Rectangles on the active layer are used to define the region where doping is to be applied to the substrate (except under the polysilicon gate) to form the source and the drain of each transistor. For an NMOS transistor, the doping will be n+. For a PMOS transistor, this doping will be p+. It will be shown later how the type of doping is actually specified. Rectangles on the poly layer are used to define the strips of polysilicon used to form the gate of each transistor and to provide short distance connections between transistors in the inverter.

The intersection of an active and poly region defines the channel of a transistor. Since the minimum size of active is 0.40 and poly is 0.18, this means that the minimum transistor width must be 0.40 and the minimum length must be 0.18. Note that in some cases, it may not be possible to draw an active area as a simple rectangle. The area may have to be one width at the source and drain to accommodate the required clearance around the source and drain contacts. It then may need to be notched to obtain the necessary transistor width for the intersection with poly. The active layer is also used to define regions that must be doped to allow a substrate or well contact. In p- substrate, the doping must be p+ type. In an N-well (where PMOS transistors are placed), the doping must be n+ type. Rectangles on the nplus and pplus layers are used to control the type of dopant applied to each diffusion area.

*Note: in gpdk technology, active layer is called oxide, nplus is called Nimp, and pplus is called Pimp. These are the layer names you will finding the LSW window (3.2). 2.3 N-well Regions PMOS transistors must be located in substrate with N type doping. In an N-well process, the substrate for the PMOS transistors is formed by diffusing N-type dopant into regions of the normally p-type substrate. Rectangles in the nwell layer, define these regions in which PMOS transistors can be placed.

2.4 Contacts 0.20u x 0.20u squares drawn on the contact layer will cause metal plugs to be source, drain, and substrate or well contacts. 0.20u x 0.20u squares drawn on the contact layer will cause the metal plugs to be placed into contact with the poly areas to form poly contacts. Metal placed on layer metal1 will connect with these contacts.

2.5 Metal power ground and signal routing layers Rectangles on the metal1 layer define regions of aluminum to be placed in the first metal layer. In this case metal1 is used for all inputs and outputs to the inverter. A 0.20 x 0.20 square on contact provides a metal plug to connect routing on layer metal1 to polysilicon routing below on the poly layer.

In the 0.18 gpdk process, there are several other metal layers available (metal2, metal3, and so on). We are not going to use in this layout since it is not needed. However, in larger more complex layouts, both layers will be needed. Often it is a wise practice to route all signals horizontally on one layer and vertically on another layer. To connect the metal1 layer to the metal2 layer, a square on via1 is used. You can connect other metal layers together using the appropriate via layers. For example, to connect the metal2 layer to the metal3 layer, a square on via2 is used.

3.0 Virtuoso Layout Editing To start the Virtuoso Layout Editor, we need to create a new cellview from the library manager. In the new window that appears, set Library Name to Tutorial and type in inverter as the Cell Name. In the View Name field, type in the layout and press the tab key. The Tool field should change to Virtuoso. Click OK to continue. Two windows will appear. One is called the Layer Selection Window (LSW). The LSW allows you to choose the layer on which you create objects, set which layers are selectable and set layer visibility. Note that the technology file that you entered in the first tutorial (gpdk) defines the layers and colors that will be available to you in the LSW. The other window is the layout window (Virtuoso Layout Editing) where you perform the place and the route of the inverter layout.

3.1 Setting up the Environment Before you start doing your layout, you need to setup the grid size of the cellview so that each grid will correspond to a dimension that will make the layout process easier and allow for a more compact design. To set up a display environment, select Options Display. The Display Option window will appear. In the window, change Minor Spacing to 0.1 and Major Spacing to 0.1. Change both X Snap Spacing and Y Snap Spacing to 0.01. The Spacing can be changed according to your requirement. Leave the other settings at their default setting. However, take note that those options will allow you to change the display of the cellview if need arises. Please refer to the online documentation if you need further information. The settings can be saved and loaded back using the Save To and Load From buttons at the bottom of the window. You can choose to save or load settings to either the cellview, library of the cellview, technology of the cellview, or a specified file. If you are saving to a file, the settings from both the Layout Editor Options and Display Options windows will be saved. Click OK when done. Back in the layout window, select Options Layout Editor. The Layout Editor Option window will appear. Options here allow you to change the editing commands of the editor and change how the cursor behaves.

In the Layout Editor Option window, uncheck the Gravity On box. This will prevent the cursor from being attracted to other objects already drawn in the cellview. Experiment on your own. If you feel that you are comfortable with this function or find it useful in certain situations, you can turn it on. Click OK when done.

3.2 Layer Selection Window (LSW) The Layer Selection Window (LSW) lets you to choose the layer on which you create objects (called the entry layer). It also controls which layers are selectable or visible. To change the LSW to make the layers selectable or visible, move the cursor over the layer and click using the middle button. It will toggle layer visibility and also automatically makes invisible layers not selectable. The text layer color disappears to show the layer is invisible. The layer name turns gray to show the layer is not selectable. Every time after you have selected a layer, select Window Redraw to see the effect of any LSW changes you have made. This will allow you to make several changes in the LSW before taking time to redraw the cellview, especially in complex designs. To make the layers visible, click on the AV (All visible) button. The colored squares showing the layer color reappear, and the shading on the layer name disappears. Use the left mouse button to select layers for entry in the LSW. The abbreviation dg after each layer name means drawing. For drawing active regions, we select the oxide layer in LSW. Pimp layer represents pplus and Nimp layer represents nplus. Contact loses is Cont.

If the layers in LSW display the same color, you need the display.drf file. The file display.drf can be found in packages/cadence/cells/generic/gpdk_MIET_2.0. copy this file to your Cadence running directory using the following command and exit and run icfb again: cp /packages/cadence/cells/generic/gpdk_MIET_2.0/display.drf ./

3.3 Creating Shapes and Objects Most of the layers that you will draw will be rectangles or polygons that are rectilinear in shape. The sizes of the objects depend on the design and the design rules.

3.3.1 Creating rectangles To create rectangles, select a layer from the LSW, then select Create Rectangle or click on the Rectangle icon on the left. In the new window that appears, type the net name you want the rectangle to be associated with. You can choose to leave it blank and name the net later. Note that assigning names to the nets aid in the future layout verification processes. However, ensure that the net names on the layout matches that ones in the schematic, otherwise the LVS program (refer to section 4.3) will fail to match nets.

3.3.2 Creating Polygons Another way creating objects is to create polygons. Select a layer from the LSW, then select Create Polygon or click the Polygon icon on the left. In the new window that appears, type the net name you want the polygon to be associated with. You can choose to leave it blank and name the net later. Set Snap Mode to Orthogonal. The snap mode controls the way segments snap to the drawing grid as you create the polygon by placing its vertices. Point and click on the first point of the polygon. The CIW will prompt for the second point of the polygon. Move the cursor to click on a second point. The layout editor will create a solid line parallel to either the Y-axis or the X-axis. Continue to click on a third point that is orthogonal to the solid line. The layout editor will create two solid lines at right angles to each other between the points you entered. You will also see two dashed lines at right angles to each other between the points you entered. The dashed lines show how the layout editor would finish the polygon if you click twice on this point you entered. If you have made a mistake in one of the points while creating a polygon, you can hit the Backspace key to undo them.

3.3.3 Creating Pins

To create pins, select Create Pin. In a window that appears, change the Mode to shape pin. A new window named Create Shape Pin will replace the previous window. Enter the pin net name in the Terminal Names field. Make sure that the names exactly match the schematic (case sensitive). If you are not sure about the names of the pin nets, open the schematic and check the net properties. Turn on the Display Pin Name option if you would like the pin names to be displayed on the layout cellview. Click the Display Pin Name Option button to change the display properties of the pin names. Select the I/O type accordingly. For power and ground pins, select inputoutput. Move the cursor to where you want to place the pin and click.

3.4 Selecting Objects for Edit To edit an object, first you need to select it. There are two selection modes: full and partial. Press the F4 key to toggle between the modes and the mode is displayed in the status banner of the layout window (top).

3.4.1 Selecting Objects To select an object, set the selection mode and click To deselect all objects, click in an empty part of the design. To select one or several objects at a time, press the Shift key while selecting. To deselect one or several objects after they have been selected, press the Ctrl key and select.

3.4.2 Editing Objects There are several functions that are often used to edit objects. They include: move, copy, delete, stretch and merge. Should you require more advanced editing methods, please refer to the Editing Objects section in the Virtuoso Layout Editor User Guide.

3.4.3 Moving Objects

To move the object, you cab select Edit Move from the drop down menu or use the Move icon on the left. The Move window appears. After you have selected the object, the CIW will prompt you for a reference point for the move. Click on the reference point for the move, and drag the pointer to the destination point. The object will be moved with respect to the reference point. Note that in the Move window, there is a Change To Layer option. This will allow you to move and change the object from one layer to another without having to redraw the object. Check the box to enable the Change To Layer function and move the object as usual. You can rotate or flip the object (sideways or upside down) by clicking the Rotate, Sideways and Upside Down buttons in the Move window before placing the object.

3.4.4 Copying Objects To copy an object, select Edit Copy or use the copy icon after you have selected the object. After the copy window appears, select the object to be copied. The CIW will ask you for a reference point (start point) for the copy. Click on the reference point for the copy and drag the pointer to the destination point. The object will be copied with respect to the reference point. To copy and paste multiple copies of the object, type in the number of copies in either the Rows or Columns fields and place the objects in the cellview as usual. Note that in the Copy window, there is Change To Layer option. This will allow you to copy and change the object from one layer to another without having to redraw the object. Check the box to enable the Change To Layer function and copy the object as usual. You can rotate or flip the object (sideways or upside down) by clicking the Rotate, Sideways and Upside Down buttons in the Copy window before placing the object

3.4.5 Deleting Objects To delete an object, select Edit Delete or press delete key.

3.4.6 Stretching Objects To stretch an object, select Edit Stretch from the drop down menu or use the Stretch icon on the left. Click on the reference point for the stretch and drag it to

the destination point. The object will be stretched with respect to the reference point.

3.4.7 Merging Objects You can use the merge function to merge two objects of the same layer. To merge objects, select the objects to be merged, then select Edit Merge.

3.4.8 Saving the Design To save the design, select Design Save or click on the Save icon on the left.

4.0 Layout Verification After you have completed the layout, you need to perform layout verification to ensure that the layout does not violate any design rules. 4.1 Design Rule Check (DRC) DRC checks your layout against physical design rules defined in the divaDRC.rul file. It will display error information if it finds any part in the layout that violates the design rules. Note that this is only a physical design check and does not verify the actual performance or functionality of the layout design. To run DRC, select Verify DRC from the drop down menu. Check the Rules File and the Rules Library fields are correct in the DRC window. Click OK to start. If there are any errors, it will be reported in the CIW. A blinking polygon, called an error marker, appears in the cellview at the location of the error. To view the errors and get a brief description of the error, select Markers Explain and click on the ant error marker. The marker will be highlighted indicating it is selected. A window named marker test will appear that contains information about the cellview that contains the error and the rule is violated. To quit the Explain command, press the Esc key. To remove the markers, select Verify Markers Delete All. The Delete All Markers window appears. Click OK to remove the Markers. If any errors are reported, make changes to the layout and re-run the DRC until all errors are fixed.

For large complex designs, it is better to run an incremental DRC. This means that the system will keep track of any changes you have made since the last DRC and it will check only the changes made. This will make DRC run faster as it does not have to check every part of the design. To turn on the incremental DRC, set the checking limit to incremental in the DRC window.

4.2 Connectivity Extraction Before performing a Layout Versus Schematic (LVS) check, you need to extract the connectivity from the layout cellview by running the Extract program. The Extract program uses rules defined in the divaEXT.rul file to recognize devices and establish electrical connections or nets. It will create an extracted cellview that shows the nets. To run the Extract program, select Verify Extract. In the Extractor window, select flat as the Extract method. A flat extract method is used because parasitic capacitance values can vary between different instances of the same cell, thus each cell must be extracted. Turn on Join Nets with Same Name. This will merge nets with the same names while suppressing warning messages about different nets that have the same name. To select the types of parasitics that are to be extracted, click the Set Switches button in the Extractor window. In the Set Switches window that appears, select the type of parasitics that are to be extracted (typically parasitic capacitances). Click OK when done selecting. Click OK or Apply in the Extractor window to create the extracted views. The extraction rules appear in the CIW as the extract program executes. When the extraction is complete, a message saying that the extracted cellview is saved will be shown. To view the extracted cellview, select File Open from the CIW. It should be under the same library and cell name. Select the extracted view name and click OK. The extracted cellview appears on top of the layout cellview. Notice that the extracted cellview is similar to the layout, but the gates now have symbols at one end. Displayed next to the symbols are the gate width and length. To display the electrical connections, open the Display Options window and select Nets. Click Apply when done.

Extracted View

4.3 Layout Versus Schematic (LVS) Software. As the name implies, the LVS program performs a comparison of the schematic to the physical layout. It will use both the extracted view and the schematic view of the layout. If you did not create an extracted view, LVS will not work. To run LVS, select Verify LVS If a LVS Form Contents Different window appears, click OK to continue. In the LVS window, fill in the schematic and extracted fields either with Browse or Sel by Cursor button. If you choose to use the Sel by Cursor button, click on the button, and then simply click in any area of the schematic or extracted cellview window. Note that if both the schematic and extracted cellview are opened before the LVS window, the fields should already be fitted automatically. Check to ensure that they are correct. Make sure that specified Rules File is divaLVS.rul and Rules Library is gpdk. Turn off the Correspondence File option. The purpose of the correspondence file is to allow the user to identify schematic/layout nodes that should be mapped to each other. Mainly you would do this if LVS has trouble matching the schematic and layout on its own.

Click Run to start LVS. When the save cellview window appears, click OK to save. The LVS job runs in the background and might take a couple of minutes to complete, depending on the complexity of the design. When the job is finished, a dialog box named Analysis Job Succeeded will appear. Note that this only means that the LVS program was executed successfully and does not mean that the layout matches the schematic. To view the LVS results, click Output in the LVS window. A text window listing the output from the LVS run appears. Scroll down until the section that compares the layout and the schematic is displayed. In that section, it will report whether the two designs match and provide a list of the numbers if instances and nets. If LVS verifies that the layout matches schematic, it will report: The net-lists match Otherwise, it will report:

The net-lists failed to match If the layout fails to match the schematic, the errors on the layout must be corrected.

4.4 Displaying the Errors Make sure that the extracted cellview is opened before you continue. To display the errors, click the Error Display button at the bottom of the LVS window. In the LVS Error Display window that appears, click the First button in the Display field. The error messages will be displayed below the Display field. In addition, the geometries in the extracted layout that do not match anything in the schematic will be highlighted in the color specified in the Error Color field. To clear the markers, click on the Clear Display button in the LVS Error Display window. If the layout matches the schematic, a netlist can be extracted from the layout to examine the performance of the design. Otherwise, errors on the layout must be corrected, followed by a DRC run on the corrected layout, a re-extraction of the layout and a LVS run. Repeat until that final layout matches the schematic.

4.5 Probing the Schematic and Layout If the layout fails to match the schematic, probing can be used to aid in finding the error. Note that this is just a tool to aid in the troubleshooting process and does not automatically locate or fix the errors. To probe a design, click the Probe Form button in the LVS Error Display window. Make sure that the schematic cellview cellview is opened before you continue (for cross probing). In the Probing window that appears, change Probing Method to cross probe and click on the Add Device or Net button. Point to a device or net in either the extracted or schematic cellview. The corresponding device or net that LVS has compared with will be highlighted in the other cellview. Alternatively, enter the name of the device or net in quotes in the CIW and they will be highlighted in both cellviews. A single probe can be performed in a similar fashion by selecting the Probing Method of single probe. This is useful in locating the errors when given a device or net name LVS. To remove the markers, click on the Remove All button in the Probing window.