is selected.

It also determines where the DK will load its value from in the Gapture-lJR state and values will be driven to output pads or core logic. Three instructions are required to be supporr-, *
BYPASSThis

instruction places the bypass register in the DR chain so that the path fi TDO involves only a single flip-flop. This allows specific chips to be tested in a s-cn. without having to shift through the lengthy shift register stages in all the chips. This ir represented with all 1's in the IR.

SAMPLE/PRELOADThis instruction places the boundary scan registers (i.e., at the chip'--the DR chain. In the Capture-DR state, it copies the chip's I/O values into the DRs. T-be scanned out in successive Shift-DR states. New values arc shifted into the DRs, hi. onto the I/O pins yet. EXTESTThis instruction allows for the testing of off-chip circuitry. It is similar r< PRELOAD, but also drives the values from the DRs onto the output pads. By drivr pattern onto the outputs of some chips and checking for that pattern at the input of : -the integrity of connections between chips can be verified. In addition to these instructions, the following are also recommended (others can be defined * IHTESTThis instruction allows for single-step testing of internal circuitry via the bour..:..- * registers. It is similar to EXTEST, but also drives the chip core with signals from the DK than from the input pads. * RUNBISTThis instruction is used to activate internal self-testing procedures within n Note that the instruction encodings are not part of the specification (except that BYPASS is . component designer must document what encodings were selected for each instruction. A typical IR bit is shown in Figure 12.26. Observe that it contains two flip-flops. The Clock.? flops of each bit arc connected to form a shift register. They are loaded with a constant value from i input in the Capture-IR state, and then are shifted out in the Shift-IR state while new values arc -r The constant value is user-defined, but must have a 01 pattern in the least significant two bits s< integrity of the scan chain can be verified. In the Update-IR state, the contents of the shift -. copied in parallel to the IR output to load the entire instruction at once.This prevents the IR fror;. tarily having illegal values while new instructions are shifted in. On reset, the IR should be asynchr loaded with an innocuous instruction such as BYPASS that does not interfere with the normal hr h n core logic.

A minimal implementation of a 3-bit control register is shown below. Notice the instruction rdefinitions. This implements the six registers required for a 3-bit instruction. The instruction is dc, produce mode_in, mode_out, and bypass signals to control the data registers, as will be discussed in tresections.

Test Data Registers

f

- Test data registers are used to set the inputs of modules to be tested ynd collect the results of running k. The simplest data register configuration consists of a boundary scan register (passing through all I/O and a bypass register (1 bit long). Figure 12.27 shows a generalized view of the data registers in :;h an internal data register has been added.This register might represent the scan chain within the chip BILBO signature register. Thus, boundary scan elegantly incorporates other built-in test structures. A -tiplexer under the control of the TAP controller selects which data register is routed to the TDO pin. '">.en internal data registers are added, the 1R decoder must produce extra control signals to select which cc is in the DR chain for a particular instruction.