CONTENTS

Chapter 1 Chapter 2 2.1 INTRODUCTION IC DESIGN FLOW Analog/Full custom flow 1 4 5 5 6 6 6 7 8 9 9 10 10 10 10 10 10 11 11 12 16 17 17 17

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2.1.1 Specification 2.1.2 Schematic 2.1.3 Simulation 2.1.4 Layout 2.1.5 Tape out 2.2 Digital/ASIC/Semi custom flow

2.2.1 Specification 2.2.2 Micro architecture 2.2.3 HDL 2.2.4 System verification 2.2.5 Synthesis 2.2.6 Static time analysis 2.2.7 Automatic place and Route 2.2.8 Transistor/Layout GDS 2.2.9 Post layout stage 2.2.10 Tape out Chapter 3 Chapter 4 4.1 FABRICATION PROCESS LAYOUT VERSUS SCHEMATIC Project description

4.1.1 Layout versus schematic 4.1.2 Importance of LVS

4.1.3 LVS Rule Deck 4.2 Chapter 5 5.1 5.2 5.3 5.4 5.5 5.6 Chapter 6 Chapter 7 Chapter 8 8.1 Scope of project IMPORTANT SVRF COMMANDS Layer operations: Dimension check operations Layer operations: Auxiliary operations Connectivity Extraction commands Layout database specification commands LVS specification commands Unit specification commands LVS RULE DECK PROCEDURE TO RUN LVS RULE DECK LVS ERRORS LVS errors categorization

19 20 22 23 23 27 28 31 36 37 56 70 71 71 71 71 72 72 72 73 73 75 75 76 78 80 81
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8.1.1 Bad component 8.1.2 Incorrect instance 8.1.3 Incorrect port 8.1.4 Incorrect nets 8.1.5 Property errors 8.1.6 Softcheck errors 8.2 Error illustrations

8.2.1 Port error 8.2.2 Instance error 8.2.3 Net error 8.2.4 Softcheck error 8.2.5 Bad component error 8.2.6 Property error Chapter 9 CONCLUSION

FUTURE SCOPE OF THE PROJECT TOOL ENVIRONMENT REFERENCES

82 83 84

LIST OF FIGURES
Fig 1.1 Fig 2.1 Fig 2.2 Fig 2.3 Fig 2.4 Fig 4.1 Fig 5.1 Fig 5.2 Fig 5.3 Fig 6.1 Fig 6.2 Fig 6.3 Fig 6.4 Fig 6.5 Fig 7.1 Fig 7.2 Fig 7.3 Fig 7.4 Fig 7.5 Fig 7.6 Fig 7.7 Fig 7.8 Fig 7.9 Fig 7.10 Moores law Analog Design Flow Implementation of LVS checks in Analog Design Flow Digital Design Flow Implementation of LVS checks in Digital Design Flow Block diagram of LVS Rule Deck AND operation NOT operation OR operation Inverter Schematic and Layout LVS report for an inverter BJT (PNP) schematic and layout NOR schematic and layout NAND schematic and layout Opening the terminal Commands used in terminal to open IC STUDIO IC STUDIO tool opened to draw schematic and Layout Schematic of D flip flop drawn using IC STUDIO tool Simulation result of d flip flop Generating the SPICE netlist for D flip flop Schematic Options to be customized to create netlist Options to be customized to create netlist Layout of D flip flop drawn using IC STATION tool The pop up window which is to be customized when Calibre tool is selected
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3 5 7 9 11 19 24 26 26 41 41 42 42 43 57 58 59 60 61 62 63 64 65

66

Fig 7.11 Fig 7.12 Fig 7.13 Fig 8.1 Fig 8.2

Adding the SPICE netlist to run LVS Rule Deck Adding the LVS Rule Deck file LVS report Layout containing the port errors Layout which uses metal2 and a single VDD/VSS to avoid port errors

67 68 69 74

75

Fig 8.3

Layout of NOR gate containing missing port, Instance, net and softcheck errors 77 78 79 80

Fig 8.4 Fig 8.5 Fig 8.6

LVS check results for above erroneous NOR Gate A simple PMOS containing BAD component error LVS result showing property error in PMOS device

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