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Lecture 4

Crystallographic Planes
Unit cell: Si lattice constant = 5.431 5 x 1022 atoms/cm3
View in <111> direction

View in <100> direction

View in <110> direction

Professor N Cheung, U.C. Berkeley

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Lecture 4

Crystallographic Notation
Miller Indices
Notation (hkl) {hkl} [hkl] <hkl> Interpretation crystal plane equivalent planes crystal direction equivalent directions

h: inverse x-intercept k: inverse y-intercept l: inverse z-intercept

(Intercept values are in multiples of the lattice constant; h, k and l are reduced to 3 integers having the same ratio.)

Professor N Cheung, U.C. Berkeley

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Lecture 4

The pn-Junction Diode

Id Vd

Id

p-type

n-type
depletion region: n & p << | ND NA |

Vd

Negligible current flow (< 1nA/cm2) for Vd <0 (i.e., reverse biased pn diode) If the p-side is maintained at a relatively negative electrical potential than the n-side, one can achieve electrical isolation
Professor N Cheung, U.C. Berkeley

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Lecture 4

Device Isolation Methods

(1) pn-junction isolation:
Cross-Sectional View: device area 1 p n Top View: p n p
Professor N Cheung, U.C. Berkeley

device area 2 p

depletion region

p p

p p

The substrate is biased to ensure that Vd is always 0 V.

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Lecture 4

(2) Oxide isolation:

device area 1 SiO2 n p SiO2 p device area 2 SiO2

(3) Silicon-on-Insulator substrate:

device area 1 Si Si device area 2

dielectric substrate (e.g. SiO2, Al2O3 )

Professor N Cheung, U.C. Berkeley

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Lecture 4

Electrical Contacts to Si
(1) Schottky (rectifying) contacts:
V
Al SiO2
depletion region

I conducting V
SiO2

n-type Si

non-conducting

Majority carriers cannot move easily from the metal into the n-Si, due to a large potential barrier. For the same metal, this potential barrier is smaller for contacts to p-type Si.

I
Al SiO2 p-type Si SiO2

V V
Professor N Cheung, U.C. Berkeley

moderately conducting
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Lecture 4

The depth of the depletion region ( xd ) decreases with increasing dopant concentration. For very high doping, xd is small enough (<10nm) to allow quantum tunneling of carriers.

(2) Tunneling ohmic contacts:

V
Al SiO2
n+

SiO2 n-type Si

ND 1020 cm-3

V
Al SiO2
p+

SiO2 p-type Si

NA 1020 cm-3

V
Professor N Cheung, U.C. Berkeley

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Lecture 4

Planar Technology
starting substrate Si wafer

*planar processing steps

monolithic integration of multiple devices

n-channel MOSFET

*sequence of additive and subtractive steps with lateral patterning

e.g. oxidation deposition ion implantation
Professor N Cheung, U.C. Berkeley

e.g. etching

e.g. lithography

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Lecture 4

Process Flow Example #1

Suspended Beam Array
Doped oxide (PSG) deposition (CVD) (blanket addition) Anchor patterning (litho. & etch) (patterned subtraction) Poly-Si deposition (blanket addition) Poly-Si beam patterning (litho. & etch) (patterned subtraction) Selective etch of PSG (blanket subtraction)

PSG = PhosphoSilicate Glass (mixture of Phosphorus oxide and Silicon Oxide)

Professor N Cheung, U.C. Berkeley

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Lecture 4

Process Flow Example #2

Hinged Structure
3 Lithography steps: 1) Hinge pattern out-of-plane movement 2) Staple anchor pattern 3) Staple pattern

Top view of masks

Cross-sectional views

Professor N Cheung, U.C. Berkeley

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Lecture 4

Process Flow Example #3

Al contact to n+ Si

Professor N Cheung, U.C. Berkeley

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Lecture 4

Process Flow Example #3 - cont

Professor N Cheung, U.C. Berkeley

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Lecture 4

Process Flow Example #3 - cont

Professor N Cheung, U.C. Berkeley

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Lecture 4

N-channel MOSFET
Schematic Cross-Sectional View

Layout (Top View) 4 lithography steps are required: 1. active area 2. gate electrode 3. contacts 4. metal interconnects

Professor N Cheung, U.C. Berkeley

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Lecture 4

Process Flow Example #4

Simple nMOSFET Process Flow
Read Jaeger (textbook) Chap 1 for narrative description
1) Thermal oxidation (~10 nm pad oxide) 2) Silicon-nitride (Si3N4) deposition by CVD (~40nm) 3) Active-area definition (lithography & etch) 4) Boron ion implantation (channel stop implant)

Professor N Cheung, U.C. Berkeley

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Lecture 4

Process Flow Example #4 - cont

5) Thermal oxidation to grow oxide in field regions 6) Si3N4 & pad oxide removal 7) Thermal oxidation (gate oxide) 8) Poly-Si deposition by CVD 9) Poly-Si gate-electrode patterning (litho. & etch) 10) P or As ion implantation to form n+ source and drain regions
Professor N Cheung, U.C. Berkeley

Top view of masks

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Lecture 4

Process Flow Example #4 cont.

Top view of masks

11) SiO2 CVD 12) Contact definition (litho. & etch) 13) Al deposition by sputtering 14) Al patterning by litho. & etch to form interconnects

Professor N Cheung, U.C. Berkeley

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