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l03 Cmos Gates
l03 Cmos Gates
l03 Cmos Gates
meta
l ndiff
poly pdiff
Physics
Application
Algorithm
Unit-Transaction Level (UTL) Model
Guarded Atomic Actions (Bluespec)
Register-Transfer Level (Verilog RTL)
Gates
Circuits Today’s
Lecture
Devices
Physics
One chip
Figures
Figuresare
arefrom
fromW.W.Maly,
Maly,Atlas
AtlasofofIC
ICTechnologies:
Technologies:AnAnIntroduction
IntroductiontotoVLSI
VLSIProcesses.
Processes.
(ignore dimensions in figures – they are quite out-of-date!)
(ignore dimensions in figures – they are quite out-of-date!)
Wet
etching
isotropic
Remove photoresist mask
Dry
etching
anisotropic
gate
inversion
Surface of wafer happens here
Source Eh Drain
diffusion diffusion
Ev
bulk
Reverse side of wafer
INVERSION:
A sufficiently strong vertical field CONDUCTION:
will attract enough electrons to the If a channel exists, a horizontal
surface to create a conducting n- field will cause a drift current
type channel between the source from the drain to the source.
and drain.
Metal 2
M1/M2 Via
Metal 1
Polysilicon
Diffusion
Width
rules
Spacing rules
3 3 2
1
1
3
diffusion (active)
2x2 3
poly
metal1
contact
F = (A+B).(C+D)
D
NFET connects
G G NFET only good
D and S when
at pulling down
S G=“high”=VDD
Ground = GND = 0V
Pullup network,
connects output to
VDD, contains only
PMOS
IN1
VOUT
IN2
INn
Pulldown network,
connects output to
GND,
contains only NMOS
For every set of input logic values, either pullup or pulldown network
makes connection to VDD or GND
• If both connected, power rails would be shorted together
• If neither connected, output would float (tristate logic)
A (A.B)
(A.B) B
B
B
A
(A+B) (A+B)
B
parallel
switches series
form OR A switches
form
(A.B) AND
B
B (A+B)
series
switches
A form parallel
AND switches
form OR
A
pullup p = (A+B).C
B
= (A+B)+C
(A+B).C = (A.B)+C
C
pulldown f = (A+B).C
Simple Equivalent RC G
Model of Transistor
CgateP CgateP
0⇒1
CgateN CgateN
Delay ~ RonN(CdrainN+CdrainP+CgateP+CgateN)
W
W/2
Diffusion
has high Use multiple contacts
resistance to diffusion to reduce
resistance
F = (A+B).(C+D).E.G+H.(J+K)
Cin
Logical Effort
Complexity of logic function (Invert, NAND, NOR, etc)
Define inverter has logical effort = 1
Depends only on topology not transistor sizing
Electrical Effort
Ratio of output capacitance to input capacitance Cout/Cin
Parasitic Delay
Intrinsic self-loading of gate
Independent of transistor sizes and output load
Relative
Transistor 2 2 4
Widths
2 4
2
1 1 1
2
Cin
CgateN
Cout