CENTURA INTEGRATED GATE STACK SYSTEM

Control. Down to the Last Atom.

Steve Ghanayem
Vice President and General Manager Silicon Systems Group

2011 Semicon West Briefing July 12, 2011

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Safe Harbor
These presentations contain forward-looking statements, including those regarding market outlooks; technology roadmaps; the proposed Varian merger; and Applieds market positions, products, growth opportunities, strategies and business outlooks. These statements are subject to known and unknown risks and uncertainties that could cause actual results to differ materially from those expressed or implied by such statements, including but not limited to: the level of demand for Applieds products, which is subject to many factors, such as uncertain global economic and industry conditions, demand for electronic products and semiconductors, government renewable energy policies and incentives, and customers new technology and capacity requirements; the satisfaction of conditions precedent to the proposed merger with Varian, including the ability to secure regulatory approvals in a timely manner or at all; Applieds ability to (i) develop, deliver and support a broad range of products and expand its markets, (ii) align its cost structure with business conditions, (iii) successfully execute its acquisition strategy and realize synergies, (iv) obtain and protect intellectual property rights, and (v) attract, motivate and retain key employees; and other risks described in Applieds SEC filings. All forward-looking statements are based on managements estimates, projections and assumptions as of July 12, 2011, and Applied undertakes no obligation to update any forward-looking statements.

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New Products Released at 2011 Semicon West

TRANSISTOR-ENABLING PRODUCTS

Reflexion GT for Tungsten Vantage Vulcan RTP Centura DPN HD Endura Versa XLR W PVD Endura HAR Cobalt PVD Centura Integrated Gate Stack
INTERCONNECT-ENABLING PR INTERCONNECT-ENABLING PRODUCTS T LING RODUCTS

Producer Black Diamond 3 Producer Nanocure 3

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The Transistor Is Undergoing a Revolution

90nm
Strained Silicon

65nm

45nm

32nm

22nm

High- Metal Gate

FinFET

Unrelenting innovation in materials and structure to continue scaling

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Engineering the High- Stack Layers

Highhh Interface Layer er

Source Drain

Si

2 nm

Atomic-scale engineering Material stability Interface layer precision

Source: Applied Materials Maydan Technology Center
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Increasing Complexity of Dielectric Gate Stack

TOTAL STACK STEPS Post-Nitridation Anneal

4X
NUMBER OF STEPS

Nitridation

HighDielectric Interface Layer

SiO2

10 Years Ago

Today

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Applied Leads in Gate Stack Production Experience

PREVIOUS PROCESS SEQUENCE

Applieds Market Position

#1

Post-Nitridation Anneal

#1

Nitridation

Centura DPN Gate Stack System

#1

Interface Layer Formation

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Applied Leads in the Gate Stack Market

GATE STACK SYSTEM SHIPMENTS

~$1B

cumulative revenue

'02

'03

'04

'05

'06

'07

'08

'09

'10

'11E

Fiscal Year
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Applied Leads in Gate Stack Production Experience

NEW PROCESS SEQUENCE Under Continuous Vacuum
Applieds Market Position

#1

Post-Nitridation Anneal

#1

Nitridation

new

Integrated ALD High-

Centura Integrated Gate Stack System

#1

Interface Layer Formation

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Interlayer Formation With Industry-Leading Thermal Oxidation

Critical surface preparation for ALD

Scales down to 3 for cutting-edge scaling

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SILICON SYSTEMS GROUP

Applied Materials Confidential

Atomic Layer Deposition Process

First precursor adsorbed as monolayer on surface Second precursor adsorbed as monolayer, reacts with first layer Reaction by-products purged and steps repeated to form each atomic layer

SILICON SYSTEMS GROUP

Applied Materials Confidential

Nitridation and Anneal Complete the Stack

Nitridation fixes the dose and stabilizes the film Anneal completes dielectric stack processing

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SILICON SYSTEMS GROUP

Applied Materials Confidential

Why Does Integration Under Vacuum Matter?

Because Interfaces Matter at 22nm

45nm
High-k h-k h-k Interface Layer er Si or SiGe r Ge

22nm
High-k gh Interface Layer e er
Si or SiGe SiG G Ge

Interface to Bulk Ratio

<15%

~50%

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Interfaces Matter Physically

Air Exposure Causes Interfacial Contamination

Non-Integrated Flow

Air Exposure

Highhh

Interface Layer e er
Si or SiGe SiG G Ge

Uncontrolled oxidation and contamination

Applieds Integrated Flow

No Air Exposure

High-k gh

Interface Layer er er
Si or SiGe SiG G Ge

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Interfaces Matter Even More Electrically

Yielding Chip Performance Benefits

Peak Mobility

5 to 10%
HIGHER PEAK MOBILITY

20 to 40%
TIGHTER THRESHOLD VOLTAGE DISTRIBUTION (1 )

Fully Integrated Gate Stack

Air Exposure After Interface Layer

Air Exposure After Interface Layer

Fully Integrated Gate Stack

Threshold Voltage

Half-of-a-Generation Performance Boost

For Lower Power Devices

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The Gate Stack System for Atomic-Scale Engineering

Centura platform is industrys benchmark for complex gate dielectrics Atomic-level control of interface layer, high- and nitridation Integrated system enables nearly perfect gate dielectrics

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