Professional Documents
Culture Documents
11 Chapter 06 Compression
11 Chapter 06 Compression
Test Compression
1
EE141 VLSI Test Principles and Architectures
2
EE141 VLSI Test Principles and Architectures
Test Compression
Introduction Test Stimulus Compression Test Response Compaction Industry Practices Concluding Remarks
3
EE141 VLSI Test Principles and Architectures
Introduction
Why do we need test compression?
Test data volume Test time Test pins
4
EE141 VLSI Test Principles and Architectures
6
EE141 VLSI Test Principles and Architectures
Decompressor
Compressed Stimulus
Core
Compacted Response
Compactor
Low-Cost ATE
7
EE141 VLSI Test Principles and Architectures
8
EE141 VLSI Test Principles and Architectures
9
EE141 VLSI Test Principles and Architectures
Code-based schemes
Dictionary code (fixed-to-fixed)
10
EE141 VLSI Test Principles and Architectures
Code-based schemes
Huffman code (fixed-to-variable)
11
EE141 VLSI Test Principles and Architectures
Code-based schemes
Huffman code (fixed-to-variable)
12
EE141 VLSI Test Principles and Architectures
Code-based schemes
Run-length code (variable-to-fixed)
13
EE141 VLSI Test Principles and Architectures
Code-based schemes
Golomb code (variable-to-variable)
14
EE141 VLSI Test Principles and Architectures
Code-based schemes
Golomb code (variable-to-variable)
15
EE141 VLSI Test Principles and Architectures
16
EE141 VLSI Test Principles and Architectures
Linear-decompression-based schemes
17
EE141 VLSI Test Principles and Architectures
Linear-decompression-based schemes
18
EE141 VLSI Test Principles and Architectures
Linear-decompression-based schemes
19
EE141 VLSI Test Principles and Architectures
Linear-decompression-based schemes
Combinational linear decompressors
XOR Network
XOR Network
MISR
20
EE141 VLSI Test Principles and Architectures
o1 o2
EE141 VLSI Test Principles and Architectures
o3
o4
o5
21
Linear-decompression-based schemes
Fixed-length sequential linear decompressors
22
EE141 VLSI Test Principles and Architectures
Linear-decompression-based schemes
Variable-length sequential linear decompressors
Can vary the number of free variables Better encoding efficiency More control logic and control information
23
EE141 VLSI Test Principles and Architectures
Linear-decompression-based schemes
Combined linear and nonlinear decompressors
Specified bits tend to be highly correlated Combine linear and nonlinear decompression together can achieve greater compression than either alone
24
EE141 VLSI Test Principles and Architectures
25
EE141 VLSI Test Principles and Architectures
Broadcast-scan-based schemes
Broadcast scan
26
EE141 VLSI Test Principles and Architectures
27
EE141 VLSI Test Principles and Architectures
28
EE141 VLSI Test Principles and Architectures
Broadcast-scan-based schemes
Illinois scan architecture
Broadcast-scan-based schemes
Reconfigurable broadcast scan
Reduce the number of channels that are required Static reconfiguration
The reconfiguration can only be done when a new pattern is to be applied
Dynamic reconfiguration
The configuration can be changed while scanning in a pattern
30
EE141 VLSI Test Principles and Architectures
Broadcast-scan-based schemes
First configuration is: 1->{2,3,6}, 2->{7}, 3->{5,8}, 4->{1,4} Other configuration is: 1->{1,6}, 2->{2,4}, 3->{3,5,7,8}
31
EE141 VLSI Test Principles and Architectures
Broadcast-scan-based schemes
Block diagram of MUX network
32
EE141 VLSI Test Principles and Architectures
Broadcast-scan-based schemes
Virtual scan
Pure MUX and XOR networks are allowed No need to solve linear equations Dynamic compaction can be effectively utilized during the ATPG process Very little or no fault coverage loss
33
EE141 VLSI Test Principles and Architectures
34
EE141 VLSI Test Principles and Architectures
35
EE141 VLSI Test Principles and Architectures
II CFI Linearity
III Nonlinearity
37
EE141 VLSI Test Principles and Architectures
Space compaction
Zero-aliasing linear compaction
38
EE141 VLSI Test Principles and Architectures
39
EE141 VLSI Test Principles and Architectures
Space compaction
X-compact
X-tolerant response compaction technique X-compact matrix Error masking
40
EE141 VLSI Test Principles and Architectures
Space compaction
X-compact
41
EE141 VLSI Test Principles and Architectures
Space compaction
X-compactor with 8 inputs and 5 outputs
42
EE141 VLSI Test Principles and Architectures
X-compact Matrix
SC1 SC2 SC3 SC4 S= SC5 SC6 SC7 SC8 O1 O2 O= O3 O4 O5
X S = O
43
Space compaction
X-blocking (or X-bounding)
Xs can be blocked before reaching the response compactor Can ensure that no Xs will be observed May result in fault coverage loss Add area overhead and may impact delay
44
EE141 VLSI Test Principles and Architectures
Space compaction
Illustration of the x-blocking scheme
45
EE141 VLSI Test Principles and Architectures
Space compaction
X-masking
Xs can be masked off right before the response compactor Mask data is required to indicate when the masking should take place Mask date can be compressed
Possible compression techniques are weighted pseudorandom LFSR reseeding or run-length encoding
46
EE141 VLSI Test Principles and Architectures
Space compaction
An example of X-masking circuit
47
EE141 VLSI Test Principles and Architectures
Space compaction
X-impact
Simply use ATPG to algorithmically handle the impact of residual xs on the space compactor Without adding any extra circuitry
48
EE141 VLSI Test Principles and Architectures
Space compaction
Handling of X-impact
49
EE141 VLSI Test Principles and Architectures
Space compaction
Handling of aliasing
50
EE141 VLSI Test Principles and Architectures
51
EE141 VLSI Test Principles and Architectures
52
EE141 VLSI Test Principles and Architectures
53
EE141 VLSI Test Principles and Architectures
Industry practices
OPMISR+ Embedded Deterministic Test Virtual Scan and UltraScan Adaptive Scan ETCompression
54
EE141 VLSI Test Principles and Architectures
Broadcast-scan-based schemes
Single step
SPMISR+, Cadence VirtualScan and UltraScan, SynTest DFT MAX, Synopsys
55
EE141 VLSI Test Principles and Architectures
Industry practices
OPMISR+
Cadence Roots in IBM s logic BIST and ATPG technology
56
EE141 VLSI Test Principles and Architectures
57
EE141 VLSI Test Principles and Architectures
Industry practices
Embedded Deterministic Test (TestKompress)
Mentor Graphics First commercially available on-chip test compression product
58
EE141 VLSI Test Principles and Architectures
59
EE141 VLSI Test Principles and Architectures
60
EE141 VLSI Test Principles and Architectures
61
EE141 VLSI Test Principles and Architectures
Industry practices
Virtual Scan and UltraScan
SynTest First commercial product based on the broadcast scan scheme using combinational logic for pattern decompression
62
EE141 VLSI Test Principles and Architectures
VirtualScan architecture
63
EE141 VLSI Test Principles and Architectures
UltraScan architecture
64
EE141 VLSI Test Principles and Architectures
Industry practices
Adaptive Scan
Synopsys Designed to be the next generation scan architecture
65
EE141 VLSI Test Principles and Architectures
66
EE141 VLSI Test Principles and Architectures
Industry practices
ETCompression
LogicVision Built upon embedded logic test (ELT) technology
67
EE141 VLSI Test Principles and Architectures
ETCompression architecture
68
EE141 VLSI Test Principles and Architectures
MISR: multiple-input signature register MUX: multiplexers PRPG: pseudo-random pattern generator TDDM: time-division demultiplexer TDM: time-division multiplexers XOR: exclusive-OR
69
EE141 VLSI Test Principles and Architectures
Concluding remarks
Test compression is
An effective method for reducing test data volume and test application time with relatively small cost An effective test structure for embedded hard cores Easy to implement and capable of producing high-quality tests Successfully as part of design flow