DESIGN OF ALU OF THE 8086 MICROPROCESSOR USING VHDL.

Project Synopsis
Submitted in Partial Fulfilment of the Requirements for the Degree of

BACHELOR OF TECHNOLOGY
in

ELECTRONICS & COMMUNICATION ENGINEERING (EC-1)

By

KUNDAN KUMAR (Roll no.-0800114038)

MD RIZWAN AHMAD (Roll no.-0800114048) DENIS KUMAR (Roll no.-0800114025) ADIL MASOOD(Roll no.-0800114007)

Under the guidance of

Ms Tarana Afrin Chandel

(ASST. PROFESSOR)

DEPT. OF ELECTRONICS & COMMUNICATION ENGINEERING

INTEGRAL UNIVERSITY
KURSI ROAD, LUCKNOW (U.P.)

TITLE-: DESIGN OF ALU OF 8086 MICROPROCESSOR USING VHDL. OBJECTIVE-: ALUs can be built in so many ways with wide specifications and since the objective of the class project is to learn the basic of VLSI design, the specifications of the ALU were relaxed. The main objective of the project is to have a working ALU that performs different arithmetic and logic functions for all possible combinations of the inputs. The speed of ALU was not an issue and we wanted it to run at low power.

INTRODUCTION
Digital design is an amazing and very broad field. The applications of digital design are present in our daily life, including Computers, calculators, video cameras etc. In fact, there will be always need for high speed and low power digital products which makes digital design a future growing business. ALU (Arithmetic logic unit) is a critical component of a microprocessor and is the core component of central processing unit. Furthermore, it is the heart of the instruction execution portion of every computer. ALUs comprise the combinational logic that implements logic operations, such as AND and OR, and arithmetic operations, such as ADD and SUBTRACT. This project includes the programming of an 16 bit ALU in VHDL language. VHDL basically is a hardware description language and used to make ASIC Ic and FPGA. In order to stimulate the program you will require two software that are Xilinx and Modelsim. ALU is basically a arithmetic and logic unit that does all logic and arithmetic operations inside the microprocessor.

PROPOSED WORK DESCRIPTION-: Arithmetic logic unit-:

In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. Research into ALUs remains an important part of computer science, falling under Arithmetic and logic structures in the ACM Computing Classification System.

1. 16 bit edge triggered register:(10%)

Registers are important modules in a synchronized circuit design. Write a 16 bit positive edge triggered register module. It has an a synchronized reset.

INPUT/ OUTPUT PIN DEFINATION-:

Property D CLK RESET Input Input Input Width(bits) 16 1 1 Active low synchronized reset Output 16-bit number Input 16-bit Number

Input

16

2.pipelined ALU design:(90%)

ALU(arithmetic logic unit) is the heart of a MIPS CPU. We will implement a basic ALU in this lab. The following picture is the block diagram of our 16-bit ALU:

IN/OUT PIN DEFINITION:

VHDL: The language

VHDL basically is a hardware description language and used to make ASIC Ic and FPGA. In order to stimulate the program you will require two software that are Xilinx and Modelsim. An entity declaration, or entity, combined with architecture or body constitutes a VHDL model. VHDL calls the entity-architecture pair a design entity. By describing alternative architectures for an entity, we can configure a VHDL model for a specific level of investigation. The entity contains the interface description common to the alternative architectures. It communicates with other entities and the environment through ports and generics. Generic information particularizes an entity by specifying environment constants such as register size or delay value.

Features of 8086 Microprocessor

1) 8086 has 16-bit ALU; this means 16-bit numbers are directly processed by 8086.

2) It has 16-bit data bus, so it can read data or write data to memory or I/O ports either 16 bits or 8 bits at a time. 3) It has 20 address lines, so it can address up to 220 i.e. 1048576 = 1Mbytes of memory (words i.e. 16 bit numbers are stored in consecutive memory locations). Due to the 1Mbytes memory size multiprogramming is made feasible as well as several multiprogramming features have been incorporated in 8086 design. 4) 8086 includes few features, which enhance multiprocessing capability (it can be used with math coprocessors like 8087, I/O processor 8089 etc. 5) Operates on +5v supply and single phase (single line) clock frequency.(Clock is generated by separate peripheral chip 8284). 6) 8086 comes with different versions. 8086 runs at 5 MHz, 8086-2 runs at 8 MHz, 8086-1 runs at 10 MHz. 7) It comes in 40-pin configuration with HMOS technology having around 20,000 transistors in its circuitry. 8) It has multiplexed address and data bus like 8085 due to which the pin count is reduced considerably.9) Higher Throughput (Speed)(This is achieved by a concept called pipelining).

Physical and electrical specifications:

Physical and electr ical specif icat ion : s

2.1. TECHNOLOGY: The design is to be implemented in a 0.25 m CMOS process with 5 metal layers You should use only 4 metal layers for the adder design. The SPICE technology is in the g25.mod file. 2.2. POWER SUPPLY: You are free to choose any supply voltage and logic swing up to 2.5 V. Make sure that you use the appropriate model when you perform any hand analysis. 2.3. PERFORMANCE METRIC: The propagation delay for static CMOS design is defined as the time interval between the 50% transition point of the inputs and the 50% point of the worst-case output signal. 2.4. AREA: The area is defined as the smallest rectangular box that can be drawn around the design. Since the ALU must interface with the cache, all of the row-matched inputs must be accessible from the left side of the design, in row-address order. In the first phase of the project, you should make area estimations based on the total transistor width and the wiring complexity. An expression for prediction of the area will be provided on the web page. 2.5. Each bit slice in the adder should accommodate 6 metal-5 busses and is 24 metal-1 tracks wide. Other circuits in the data path set this constraint. 2.5. NAMING CONVENTIONS: The input operands of the adder are named A<15:0> and B<15:0>. The output is SUM<16:0>, where SUM<16> is the carry out bit. 2.6. REGISTERS: The registers will be specified in the phase 4. 2.7. CLOCKS: The adder design is combinational, so there should be no global clock in project phases 1-3. If you choose to use dynamic logic, you are permitted a precharge/evaluate clock, but the result must become available after ONE evaluate phase (no pipelined logic). Remember that the load capacitance of the clock should be included in the energy analysis. 2.8. VOH, VOL, NOISE MARGINS: You are free to choose your logic swing. The noise margins should be at least 10% of the voltage swing. Test this by computing the VTC between one of the inputs and the output signals (with the other outputs set to the appropriate values) for a static design. For a dynamic circuit, apply an input signal with a 10% noise value added to the input and observe the outputs. 2.9. RISE AND FALL TIMES: All input signals have rise and fall times of 50 ps. The rise and fall times of the output signals (10% to 90%) should not exceed 200ps.

2.10. LOAD CAPACITANCE: Your adder is driving a 1.6mm long bus with 6 loads evenly distributed. Each capacitive load is equal to the adder input capacitance. Each wire in the bus is 4 wide with 4 spacing in M5. 2.11. INPUT CAPACITANCE: Each input of the adder should not load the previous stage with more than 50fF (less is OK).