UNIT 2 DATA TRANSFER TECHNIQUES:

Transmission Format y y Asynchronous synchronous

Modes of Data Transfer

y y

Parallel Serial

Device Controlled Operations

y y

Peripheral I/O Memory- mapped I/O

Conditions of Data Transfer

Microprocessor Controlled

Device Controlled

Unconditional

Polling

Interrupt

Handshake Signals

With HOLD Signal (Direct Memory Access)

FORMATS OF DATA TRANSFER: SYNCHRONOUS Synchronous means at same time ASYNCHRONOUS Asynchronous means at regular intervals

Transmitter & Receiver are synchronized Synchronized with different clock with same clock Used in high speed data transmission Used in low speed data transmission

Data transfer between microprocessor and peripheral is asynchronous

MODES OF DATA TRANSFER: y y Microprocessor sends or receives data either in parallel mode or serially. In the parallel mode the entire word(8 bits )is transferred one at a time.

y y y

In serial mode, the data are transferred one bit at a time. In microprocessor the entire 8 bits are transferred over the 8 data lines. in serial mode, microprocessor transfer the parallel data using parallel to serial converter and receives the data by converting the serial to parallel using serial to parallel converter.

Types of I/O: y y In peripheral I/O, a peripheral is identified with an 8 bit address. 8085 has 2 instructions IN and OUT- to implement data transfer between microprocessor and peripherals. In memory-mapped I/O, a peripheral is connected as if it was a memory location, and it is identified with16-bit address.

TYPES OF I/O: PERIPHERAL I/O Peripheral is identified by 8-bit address MEMORY-MAPPED I/O Identified by 16 bit address

IN & OUT Instructions implements The instructions are STA; LDA; MOV peripheral technique M,R; MOV R,M

CONDITIONS OF DATA TRANSFER: The process of data transfer between microprocessor and peripherals are controlled either by microprocessor or peripheral devices. MICROPROCESSOR CONTROLLED DATA TRANSFER: Unconditional Data Transfer: The microprocessor sends data assuming the peripheral is always available.eg. to display data. Polling (Status Check) The microprocessor is put in a loop to check whether data are available. for eg. to read the data from an input keyboard, the microprocessor can keep polling the port until a key is pressed. Data transfer with interrupt: Here, when the peripheral is ready it send a request signal as interrupt to the microprocessor. The microprocessor stops the execution of the program, accepts the data and then returns to the program.

Data Transfer using Handshake Signals: Here, the microprocessor and the peripheral exchanges the handshake signals prior to the actual data transfer to check the ready condition. PERIPHERAL CONTROLLED DATA TRANSFER: When the peripheral is faster than the microprocessor , the peripheral request for the control of system buses using HOLD. In turn, microprocessor sends an acknowledgement signal HLDA and releases its address bus, data bus and data are transferred at high speed without the help of microprocessor. 8085 INTERRUPTS: Interrupts: Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device The process is asynchronous.

Types of interrupts: Interrupts can be classified into two types: Maskable Interrupts (Can be delayed or Rejected) RST Interrupts, INTR Non-Maskable Interrupts (Cannot be delayed or Rejected) TRAP Interrupts can also be classified into: Vectored (the address of the service routine is known to microprocessor) RST5.5, RST6.5, RST7.5, TRAP Non-vectored (the address of the service routine needs to be supplied externally by the device) INTR Interrupts can also be classified into: Hardware interrupts: TRAP, RST7.5, RST 6.5, RST5.5,INTR Software interrupts: RST 0 , RST 1 ,RST 2 ,RST 3 ,RST 4, RST 5 ,RST 6 ,RST 7

Interrupt Process: 1. The interrupt process should be enabled using the EI instruction by enabling the interrupt enable flip-flop. the instruction DI disables or resets the flip flop. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If INTR is high, microprocessor completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted 4. INTA allows the I/O device to send a RST instruction through external hardware to data bus. 5. When microprocessor receives RST instruction, saves the memory location of the next instruction on the stack and the program is transferred to call location (ISR Call) specified by the RST instruction 6. Microprocessor Performs the ISR. 7. ISR must include the EI instruction to enable the further interrupt within the program. 8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.