Rambus'S Opp. To Manufacturers' Mot. For Summary Judgment of Invalidity (MSJ No. 1) C 05-00334 RMW C 05-02298 RMW C 06-00244 RMW

Case 5:05-cv-00334-RMW Document 2536 Filed 11/14/2008 Page 1 of 19
1 Gregory P. Stone (SBN 078329) Rollin A. Ransom (SBN 196126)

Andrea Weiss Jeffries (SBN 183408) SIDLEY AUSTIN LLP
2 Fred A. Rowley, Jr. (SBN 192298) 555 West Fifth Street, Suite 4000
MUNGER, TOLLES & OLSON LLP Los Angeles, CA 90013-1010
3 355 South Grand Avenue, 35th Floor Telephone: (213) 896-6000
Los Angeles, CA 90071-1560 Facsimile: (213) 896-6600
4 Telephone: (213) 683-9100 Email: rransom@sidley.com
Facsimile: (213) 687-3702
5 Email: gregory.stone@mto.com Pierre J. Hubert (Pro Hac Vice)
Email: andrea.jeffries@mto.com Craig N. Tolliver (Pro Hac Vice)
6 Email: fred.rowley@mto.com McKOOL SMITH PC
300 West 6th Street, Suite 1700
7 Peter A. Detre (SBN 182619) Austin, TX 78701
Rosemarie T. Ring (SBN 220769) Telephone: (512) 692-8700
8 Jennifer L. Polse (SBN 219202) Facsimile: (512) 692-8744
MUNGER, TOLLES & OLSON LLP Email: phubert@mckoolsmith.com
9 560 Mission Street, 27th Floor Email: ctolliver@mckoolsmith.com
San Francisco, CA 94105
10 Telephone: (415) 512-4000
Facsimile: (415) 512-4077
11 Email: peter.detre@mto.com
Email: rose.ring@mto.com
12 Email: jen.polse@mto.com
13 Attorneys for RAMBUS INC.
14 UNITED STATES DISTRICT COURT
15 NORTHERN DISTRICT OF CALIFORNIA, SAN JOSE DIVISION
16
RAMBUS INC., CASE NO. C 05-00334 RMW
17
Plaintiff, RAMBUS INC.’S OPPOSITION TO
18 MANUFACTURERS’ MOTION FOR
v. SUMMARY JUDGMENT OF INVALIDITY
19 UNDER 35 U.S.C. § 102 OF CLAIM 16 OF
HYNIX SEMICONDUCTOR INC., et al., U.S. PATENT NO. 6,266,285; CLAIMS 27
20 AND 43 OF U.S. PATENT NO. 6,314,051;
Defendants. CLAIM 28 OF U.S. PATENT NO. 6,426,916;
21 AND CLAIM 16 OF U.S. PATENT NO.
6,452,863 (MSJ NO. 1)
22
Date: December 11, 2008
23 Time: 2:00 p.m.
Ctrm: 6 (Hon. Ronald M. Whyte)
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RAMBUS’S OPP. TO MANUFACTURERS’ MOT. FOR
SUMMARY JUDGMENT OF INVALIDITY (MSJ NO. 1)
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2 RAMBUS INC., CASE NO. C 05-02298 RMW

Plaintiff,
3
v.
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SAMSUNG ELECTRONICS CO., LTD.,
5
et al.,
6 Defendants.
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CASE NO. C 06-00244 RMW
8 RAMBUS INC.,
9 Plaintiff,
10 v.
11 MICRON TECHNOLOGY INC., et al,
12 Defendants.
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SUMMARY JUDGMENT OF INVALIDITY (MSJ NO. 1)
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1 TABLE OF CONTENTS
2 Page
3 I. INTRODUCTION .............................................................................................................. 1
II. ARGUMENT ...................................................................................................................... 1
4
A. The Manufacturers Must Prove Anticipation by Clear and Convincing
5 Evidence.................................................................................................................. 1
B. Bennett Does Not Disclose Placing Its Interface on a Memory Device ................. 2
6
C. Bennett Does Not Disclose Programmable Read/Write Delay............................... 5
7 D. Bennett Does Not Disclose Variable Block Size .................................................... 8
8 E. Bennett Does Not Disclose a Set Register Request .............................................. 10
F. Bennett Does Not Anticipate the Claims at Issue ................................................. 10
9
1. Bennett Does Not Anticipate Claim 16 of the ’285 Patent ....................... 11
10 2. Bennett Does Not Anticipate Claim 27 of the ’051 Patent ....................... 12
11 3. Bennett Does Not Anticipate Claim 43 of the ’051 Patent ....................... 12
12
13 III. CONCLUSION ................................................................................................................. 15
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1 TABLE OF AUTHORITIES
2 Page
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FEDERAL CASES
4
Electro Med. Sys., S.A. v. Cooper Life Sci., Inc.,
5 34 F.3d 1048 (Fed. Cir. 1994)................................................................................................... 2
Net MoneyIN, Inc. v. Verisign, Inc.,
6 ---F.3d---, 2008 WL 4614511 (Fed. Cir. Oct. 20, 2008)........................................................... 2
7 Schumer v. Lab. Computer Sys., Inc.,
308 F.3d 1304 (Fed. Cir. 2002)............................................................................................. 1, 2
8 Scripps Clinic & Research Found. v. Genentech Inc.,
927 F.2d 1565 (Fed. Cir. 1991)................................................................................................. 2
9
10 STATUTES AND RULES

11 35 U.S.C. § 102 ............................................................................................................................... 2
12 35 U.S.C. § 282 ............................................................................................................................... 1
Fed. R. Civ. P. 56(c)........................................................................................................................ 2
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1 I. INTRODUCTION
2 The Manufacturers move for summary judgment of anticipation of five Rambus
3 patent claims, generally directed to the programmable read and write latency and variable block
4 size features, based on U.S. Patent No. 4,734,909 (“Bennett”).1 Bennett is, however, not directed
5 to a synchronous memory device as claimed by Rambus’s patents. Bennett discloses what it
6 refers to as a “Versatile Bus” and an interface for components to connect to that bus, but
7 numerous references in Bennett make clear that Bennett does not contemplate placing the
8 interface on memory chips. Rather, Bennett contemplates using memory cards containing
9 multiple memory chips together with a separate bus interface chip. Such a combination of
10 memory chips with a bus interface chip is not a “memory device” within the meaning of
11 Rambus’s claims.
12 Further, while the Bennett interface does contain a configuration register, that
13 register contains no values corresponding to read latency, write latency, or block size. The
14 Manufacturers do not argue otherwise, but assert that other parameters in the configuration
15 register indirectly determine the parameters of interest. For example, the Manufacturers argue
16 that whether certain signals are multiplexed on the same lines or not, a parameter that is
17 programmed in the configuration register, also determines the read and write latency. But there is
18 no such disclosure in Bennett and there is no direct correlation between multiplexing and latency.
19 Especially in light of the heavy burden the Manufacturers bear in seeking to invalidate Rambus’s
20 patents on summary judgment, the Court should deny their motion.
21 II. ARGUMENT
22 A. The Manufacturers Must Prove Anticipation by Clear and Convincing
Evidence.
23
United States patents are presumed valid. 35 U.S.C. § 282. Accordingly,
24
“[e]vidence of invalidity must be clear as well as convincing.” Schumer v. Lab. Computer Sys.,
25
26 1
Rambus has moved to strike the Manufacturers’ motion as plainly improper under the Court’s
27 schedule which required motions for summary judgment dependent on claim construction issues
to be brought over a year ago. Nevertheless, Rambus is compelled to respond on the merits
28 because the hearing on Rambus’s motion will not take place until after this opposition is due.
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1 Inc., 308 F.3d 1304, 1315 (Fed. Cir. 2002) (reversing district court’s grant of summary judgment
2 of invalidity).
3 Anticipation under 35 U.S.C. § 102 is a question of fact. Scripps Clinic &
4 Research Found. v. Genentech Inc., 927 F.2d 1565, 1576 (Fed. Cir. 1991). Anticipation requires
5 that each and every element of the claimed invention be disclosed in a single prior art reference,
6 arranged or combined in the same way as recited in the claim, either expressly or inherently. Net
7 MoneyIN, Inc. v. Verisign, Inc., ---F.3d---, 2008 WL 4614511, at *8 (Fed. Cir. Oct. 20, 2008). A
8 limitation is present in a prior art reference inherently only if a person of ordinary skill in the art
9 would recognize that the limitation, although not expressed, is necessarily present. See Electro
10 Med. Sys., S.A. v. Cooper Life Sci., Inc., 34 F.3d 1048, 1052 (Fed. Cir. 1994) (“[T]he mere fact
11 that a certain thing may result from a given set of circumstances is insufficient to prove
12 anticipation . . . . [The challenger] was required to prove that [the limitation] is necessarily
13 present.”) (emphasis in original) (internal citations omitted).
14 A party is entitled to summary judgment only when there are no genuine disputes
15 as to material facts concerning an issue. Fed. R. Civ. P. 56(c). On a motion for summary
16 judgment, all reasonable inferences must be drawn in favor of the non-movant. Accordingly,
17 “[t]he burden of proving invalidity on summary judgment is high.” Schumer, 308 F.3d at 1316;
18 see also Scripps Clinic, 927 F.2d at 1578 (reversing district court’s grant of summary judgment of
19 anticipation and noting that “[t]rial by document is an inadequate substitute for trial with
20 witnesses, who are subject to examination and cross-examination in the presence of the decision-
21 maker”).
22 B. Bennett Does Not Disclose Placing Its Interface on a Memory Device.
23 Contrary to the Manufacturers’ argument, Bennett does not disclose putting its
24 interface on a memory chip. The Manufacturers rely on references to “memory” and separate
25 statements that certain system components “may” be implemented as VLSIC devices. See Col.
26 35:67-68.2 A person of skill in the art, however, would understand that Bennett did not intend for
27
2
28 Citations to columns and lines are all to Bennett.
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1 the memory devices used with its invention to be implemented as VLSIC devices. See Murphy
2 Declaration, Ex. A (Supplemental Expert Report of Robert J. Murphy Regarding Validity)
3 (hereinafter “Supp. Murphy Report”), ¶¶ 3-9.
4 Indeed, the Manufacturers concede that certain references to memory in Bennett,
5 despite no express statement to that effect, would necessarily be understood as referring to large
6 memory cards containing many memory chips. According to the Manufacturers, “Bennett
7 explains that multiple memory chips may be used together as a ‘Large Memory.’” Mot. at 183
8 (citing Bennett Fig. 34; Col. 94:24-36). The cited portions of Bennett do not state in so many
9 words that a “large memory” contains multiple memory chips, but the Manufacturers are correct
10 that a person of skill in the art would understand the term in that way. Indeed, Bennett notes that
11 a large memory may contain “up to 232 addresses of 32 bit words,” i.e. 128 Gigabits of memory.
12 Col. 95:58-59; Supp. Murphy Report, ¶ 4. The largest memory chips of the time, however,
13 contained 64 Kilobits of memory and it would take over two million of such chips to total the 128
14 Gigabits of memory contemplated by Bennett. Murphy Report, ¶ 4. No person of skill in the art
15 would have attempted to implement this amount of memory as a VLSIC device; to the contrary, it
16 would have taken thousands of large memory cards and would have filled a medium-sized room.
17 Id. The parties thus agree that the general references in Bennett to the possibility of
18 implementing certain components as VLSIC components do not apply to all of the system
19 components discussed in Bennett and, in particular, do not apply to what Bennett refers to as a
20 “large memory.” Rather, such a large memory would consist of multiple cards, each containing
21 thousands of memory chips, and additional interface chips implementing the invention described
22 in the Bennett patent.
23 A person of skill in the art would also understand that the other memories referred
24 to in Bennett likewise consist of memory cards with multiple memory chips and separate
25 interface logic chips. For example, Bennett notes that “[a]n efficient interconnect system cannot
26 saddle simple interconnects with the coordination overhead required for the complex ones.” Col.
27 3
The Manufacturer’s motion is not paginated. This brief cites to the page numbers in the Court’s
28 filing stamp at the top of the motion’s pages.
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1 8:10-12. Connecting memory to a controller is a prime example of what Bennett refers to as a

2 “simple” interconnect, and it is clear that Bennett does not intend to “saddle” that simple
3 interconnect with the complex interface described. See Supp. Murphy Report, ¶ 5. The complex
4 Bennett interface might be considered for chips that use a large number of pins, such as
5 microprocessors – as Bennett notes “a VLSIC chip has on the order of 100 pins.” Col. 66:65-66.
6 But, as a person of skill in the art would recognize, it would be absurd to put such a complex
7 interface on memory chips which, at that time, had only 16 pins total. Supp. Murphy Report, ¶ 6.
8 Pins are a “precious resource” (Col. 7:25-26), and adding the interface would multiply the
9 number of pins many times over at great expense without any corresponding benefit. Indeed,
10 simply to connect to Bennett’s “maintenance processor” – a device responsible for initialization
11 tasks, such as loading the configuration register in the devices with the Bennett interface –
12 requires 24 pins in addition to the pins required to connect to the Versatile Bus itself. Col. 117:64
13 – 118:13; Supp. Murphy Report, ¶ 7. Add to this what Bennett describes as the “modest thirty-
14 seven pin requirement” of the interface to the Versatile Bus (Col. 36:62-63), and it would become
15 clear to any person of skill in the art that Bennett is not proposing an interface to be incorporated
16 on a memory chip. Supp. Murphy Report, ¶ 8.
17 A person of skill in the art would understand that Bennett contemplates using
18 existing memory technology – multiple asynchronous DRAMs on memory cards – with separate
19 interface chips to connect to the Versatile Bus. Indeed, Bennett essentially says as much, stating
20 that “[m]emories and memory subsystems must be selected to provide the operations needed in a
21 specific design.” Col. 91:2-4 (emphasis added). Bennett does not contemplate designing new
22 memory technology, but simply selecting from the options already available. Supp. Murphy
23 Report, ¶ 9.
24 Memory cards containing large numbers of existing asynchronous DRAMs
25 combined with separate interface chips do not constitute “memory devices” within the meaning of
26 Rambus’s patent claims. The Court has not yet ruled on Rambus’s motion for reconsideration of
27 claim construction, seeking a ruling that a “memory device” as used in those claims refers to a
28 single chip. Even if the Court were to deny Rambus’s motion, however, while the Court
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1 previously held that a memory device need not be a single chip, nothing in the Court’s claim
2 construction suggests that any collection of chips could be a memory device so long as some of
3 those chips were memory chips.4 In fact, Rambus made clear during the prosecution of its patents
4 that conventional asynchronous DRAMs, combined with a separate bus interface chip as in
5 Bennett, did not constitute a “memory device.” Supp. Murphy Report, Ex. 1, at 10-11.
6 Moreover, a person of skill in the art would not consider such a collection of chips to be a single
7 memory device. Id. ¶ 11.
8 Bennett’s failure to disclose a memory device containing the Bennett interface,
9 dooms the Manufacturers anticipation arguments because those arguments hinge on the interface
10 being part of the memory device of the claims. Even if the Manufacturers were correct that
11 various elements of Rambus’s claims are disclosed by Bennett (and, as discussed below, they are
12 not), they do not dispute that the features of Bennett that they identify with most of these
13 elements – such as the receipt of an external clock, block size information, and operation codes –
14 are part of the Bennett interface. Because that interface is not part of the memory device, Bennett
15 cannot anticipate Rambus’s patent claims.
16 C. Bennett Does Not Disclose Programmable Read/Write Delay.
17 The Manufacturers argue that Bennett discloses programming values into a
18 “configuration register” that determine read and write delays. However, while Bennett does
19 disclose a configuration register, it is clear from the specification that the values in the register –
20 none of which are for programming a read or write delay – cannot determine the timing of
21 responses to transaction requests. Supp. Murphy Report, ¶ 12.
22 As an initial matter, even if the configuration of a device determined the timing of
23 4
Moreover, the Court suggested that if the term “memory device” were further qualified as a
24 “synchronous dynamic random access memory device” or a “synchronous memory device,” it
would refer to a single chip. Claim Construction Order, July 10, 2008, at 35. Of the claims at
25 this issue in this motion, only claim 16 of the ’285 patent and claim 27 of the ’051 patent includes
a “memory device” without further qualification. Claim 43 of the ’051 patent claims a
26 “synchronous dynamic random access memory” device, claim 28 of the ’916 patent claims a
“synchronous semiconductor memory device,” and claim 16 of the ’863 patent claims a method
27 of operation of a “synchronous memory device.” Thus, all but claim 16 of the ’285 patent and
claim 27 of the ’051 patent require a single-chip memory device even under the Court’s original
28 claim construction.
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1 a response to a transaction request – and, as discussed below, it does not – the values in the
2 configuration register do not determine the actual configuration of the device. Rather, the values
3 in the configuration register provide a ceiling on the number of lines and other parameters that the
4 part can support; the part must also support all values under that ceiling and the actual
5 configuration will depend not only on the ceiling but also on the capabilities of other components
6 in the system. Supp. Murphy Report, ¶ 13; Col. 37:66-38:3 (“The design rule for Versatile Bus
7 interface logics is that any value may be chosen for each primitive [i.e. parameter in the
8 configuration register], but then all smaller values for that primitive must also be supported. With
9 this rule, it is always possible to find a value for each primitive that is supported by all the chips
10 that are to be used together . . . .”); Col. 78:51-55 (“[T]o assure that any chip can be connected to
11 any other chip using a Versatile Bus configuration, the chip design must support any
12 configuration whose configuration digits are all equal to or less than the corresponding chosen
13 configuration digits . . . . ”). Thus, the values in the configuration register do not determine the
14 actual configuration of the device.
15 The Manufacturers point to two sets of figures in Bennett that they assert disclose
16 programmable read and write delay: figures 25a and 25b, and figures 32 and 33. Mot. at 10-11.
17 Neither set of figures support the Manufacturers’ argument.
18 Figures 25a and 25b do not disclose programmable read or write delays. In the
19 configuration shown in figure 25a, as the Manufacturers note, the DATA signals and the WAIT
20 signal are multiplexed on the same lines and, hence, cannot be sent simultaneously. Mot. at 10.
21 In the configuration shown in figure 25b, the DATA signals and the WAIT signal are sent on
22 separate lines and, therefore, can be sent simultaneously. As the figures indicate, having separate
23 lines for the signals to be sent simultaneously allows the transaction at issue to be completed
24 more quickly than if the lines are multiplexed.
25 The purpose of these different configurations is to permit trade-offs of the
26 competing interests of speed versus reducing the number of pins, and not to adjust read or write
27 delays. See Col. 12:62-64 (discussing “trade off [of] pins for communication bandwidth”). Not
28 surprisingly then, there is no particular set time between a read or write command and the
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1 corresponding data when the data lines are multiplexed with the wait lines, or when these lines
2 are independent. Supp. Murphy Report, ¶ 14. While figure 25a shows a data signal one clock
3 cycle before figure 26a, as Bennett makes clear this is just an example: “In order to simplify
4 presentation of timing concepts all Arbitration, Slave Identification/Function, and Data activities
5 are assumed to be but one cycle.” Col. 85:17-19 (referring to figures 25a through 25h). Thus,
6 while one cycle is used as an example, there is no value stored in the configuration register of
7 Bennett, or anywhere else, that mandates a one cycle difference between the two configurations.
8 Moreover, the WAIT signal itself, if asserted, injects further indeterminacy into the transaction.
9 As Bennett notes, the WAIT signal is the way that slave devices (like memories) “inform a
10 requesting bus-owning master device of their individual or collective incapacity to immediately
11 receive data within the instant communication transaction . . . . In other words, in a simplistic
12 sense wait means ‘abort’ or ‘try again after a time.’” Col. 16:53-58. Thus, assertion of the WAIT
13 signal causes additional unknown, and unprogrammed, delay in the timing of a transaction. Supp.
14 Murphy Report, ¶ 17. Bennett does not disclose any method for determining the time between
15 read or write commands and the corresponding data, and, so does not disclose programmable read
16 or write delay. Id. ¶ 16.
17 Moreover, even if the choice of whether to multiplex the data and wait lines did
18 determine the read or write delay (which it does not), for the reasons discussed above, the values
19 in the configuration register do not determine whether those lines are multiplexed. Rather, they
20 determine only whether those lines could be multiplexed. For example, in the example given in
21 Col. 79:4-10, the eight bits of the configuration register are set to the preferred embodiment of
22 55255355. Referring to Figure 3 of Bennett, we see that the digit “3” in the sixth configuration
23 bit corresponds to one WAIT line. But, as Bennett makes clear, the device must support all
24 possible configurations with smaller values of the configuration digits. For example, despite the
25 values in the configuration register, the actual configuration of the device may be 42252255 –
26 with a “2” in the sixth configuration bit corresponding to zero wait lines according to Figure 3. In
27 other words, even though the value in the register is a “3” for the preferred embodiment
28 configuration, it may be connected to a device with a “2” such that no wait lines are present and
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1 the device with a “3” would multiplex WAIT and data and have the corresponding timing for data
2 output that is the same as the device with a “2” in its register. Supp. Murphy Report, ¶ 15.
3 Likewise, Bennett’s figures 32 and 33 fail to disclose programmable read or write
4 delay. As an initial matter, contrary to the Manufacturers’ argument, these figures do not show
5 data being transmitted at different times following a read or write command. In figure 32, the
6 “operation” is transmitted on the second clock cycle, and data is transmitted on the third clock
7 cycle – one clock cycle later. In figure 33, the “operation” is transmitted on the third clock cycle,
8 and data is transmitted on the fourth clock cycle – again one clock cycle later. The reason that
9 data is transmitted on the third clock cycle in figure 32 and the fourth clock cycle in figure 33 is
10 because figure 33 allows two cycles for arbitration prior to the operation being transmitted,
11 instead of just one cycle – but this is irrelevant to the read and write delays at issue in Rambus’s
12 patent claims which are measured from the relevant read or write request. Moreover, nowhere
13 does Bennett suggest that the one clock cycle delay shown in both figures 32 and 33 is anything
14 other than an example, or that it corresponds to some programmed value. Supp. Murphy Report,
15 ¶ 18. Certainly, no such value is programmed in the Bennett configuration register.
16 D. Bennett Does Not Disclose Variable Block Size.
17 The Manufacturers argue that Bennett discloses variable block size in two different
18 ways. Neither can withstand scrutiny.
19 First, the Manufacturers point to a “BUSY” signal in Bennett that is active during
20 a Block Read or Block Write operation. Mot. at 11-12. “Dropping the BUSY line to inactive
21 terminates the transaction.” Col. 91:59-61. The Court has construed “block size information” as
22 “information that specifies the total amount of data that is to be transferred on the bus in response
23 to a transaction request.” Claim Construction Order at 88, July 10, 2008 (emphasis added); see
24 also ’916 patent, claim 26 (“the block size information is representative of an amount of data to
25 be output by the memory device in response to a first operation code”) (emphasis added); ’863
26 patent, claim 14 (“the first block size information represents a first amount of data to be input by
27 the memory device in response to an operation code”) (emphasis added). Thus, as the Court’s
28 claim construction, and the express claim language, recognizes, the block size information must
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1 specify an amount of data that is to be transferred in the future. Changing the state of the BUSY
2 signal in Bennett cuts off the stream of data and puts an end to the Block Read or Block Write
3 operation, but in no way specifies the amount of data to be transferred, as Bennett acknowledges.
4 See Col. 61:54-58 (“[B]lock data transfer transpires under the same BEGIN and BUSY control
5 signals as the transmission of a single word – no special information transmission (such as block
6 length) or control protocol is ever involved.”) (emphasis added); see also Supp. Murphy Report, ¶
7 20.
8 In fact, the Manufacturers have acknowledged that a signal, like the BUSY signal
9 in Bennett, is not “block size information” within the meaning of Rambus’s patents. In the
10 “conduct” phase of this litigation, the Manufacturers argued that viable alternatives existed to
11 Rambus’s inventions, including variable block size. In particular, they argued that one such
12 alternative would be a “burst terminate” signal, described as “a dedicated signal input to indicate
13 or command at will the termination of an otherwise fixed-length burst in progress, thereby
14 achieving variable-length bursts on-the-fly without requiring the programmable feature.” Supp.
15 Murphy Report, Ex. 2 (McAlexander Conduct Report at 29). This is precisely a description of
16 Bennett’s BUSY signal and a concession that it an alternative to variable block size as described
17 in Rambus’s patents. Id. ¶ 21.
18 Second, the Manufacturers argue that a “form of block transfer is set by bits 18-23
19 stored in the configuration register, which together define (a) the number of bits per data word
20 and (b) the number of data cycles used to transfer each data word.” Mot. at 12. The fallacy in the
21 Manufacturers’ argument is that the bits they point to do not specify the number of data words to
22 be transferred. Of course, in order to specify the total amount of data to be transferred, as
23 required for block size information within the meaning of Rambus’s patent claims, the number of
24 data words, in addition to the number of bits per data word, must be provided and Bennett does
25 not do so. Supp. Murphy Report, ¶ 22. Indeed, Bennett itself makes this clear: “The seventh
26 configuration dimension [namely, bits 18-23 in the configuration register] is the format – the
27 partionment in pins times cycles as equals bits – of data words and is not the amount thereof.”
28 Col. 17:29-31 (emphasis added).
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1 E. Bennett Does Not Disclose a Set Register Request

2 The Court has construed a “set register request” as “one or more bits to specify
3 that a value be stored in a programmable register.” The Manufacturers assert that Bennett
4 discloses this feature because it states that “the configuration register may be set before the device
5 is even soldered into a machine system, or it may be set and reset through an optional device
6 management interface.” Mot. at 17 (quoting Col. 35:48-51). Of course, this quote from the
7 patent says nothing about how the configuration register is set and whether it is accomplished
8 through a “set register request” as that term has been construed by the Court.
9 The Manufacturers also cite to column 125 of Bennett, but here Bennett makes
10 clear that setting the configuration register does not involve a set register request. Rather, Bennett
11 explains that, in order to set the configuration register, the SCAN/SET ENABLE signal must be
12 held low, the SCAN/SET SELECT signal must be held low, and the SEL LOOP D signal must be
13 held high, while the SET DATA signal successively takes on the values to be set in the
14 configuration register. Col. 125:46-56; Supp. Murphy Report, ¶ 23. Since the three signal lines
15 (SCAN/SET ENABLE, SCAN/SET SELECT, and SEL LOOP D) must be held at the required
16 values during the entire process of setting the configuration register – that is, while all 28 bits are
17 shifted into the register (Col. 125:33-46) – those values cannot be considered to be “bits” as
18 required for a set register request. Supp. Murphy Report, ¶ 23. This is easily seen because, if
19 those values are transmitted to the device and sampled by the device so that the device receives
20 the “bits” in question, but the values are not held on the signal lines, the configuration register
21 will not be set. Id.
22 F. Bennett Does Not Anticipate the Claims at Issue

23 For at least the reasons set forth above, Bennett does not disclose numerous claim
24 elements in each of the claims that are the subject of the Manufacturers’ motion. It follows that
25 Bennett cannot anticipate any of those claims. At a minimum, and especially in light of the high
26 burden that the Manufacturers must meet, there can be no doubt that there remains a genuine
27 dispute of material fact as to anticipation of each of claims at issue. A number of limitations of
28 each of those claims that are not disclosed by Bennett are set forth below.
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1 1. Bennett Does Not Anticipate Claim 16 of the ’285 Patent

2 Claim 16 of the ’285 patent depends on claims 13 and 15 as follows:
3 13. A method of operation in a memory device having a section of

memory which includes a plurality of memory cells, the method
4 comprising:
5 receiving an external clock signal;
6 receiving a request for a write operation synchronously with respect
to the external clock signal; and
7
sampling data, in response to the request for a write operation, after
8 a programmable number of clock cycles of the external clock signal
transpire.
9
15. The method of claim 13 further including storing a value which
10 is representative of the programmable number of clock cycles of the
external clock in a programmable register on the memory device.
11
16. The method of claim 15 further including receiving a set
12 register request, wherein in response to the set register request, the
memory device stores the value in the register.
13
For the reasons set forth above, numerous elements of claim 16 are not disclosed
14
in Bennett. First, the Manufacturers’ arguments are based on the bus interface disclosed in
15
Bennett, but, as discussed in section II.B above, Bennett does not disclose putting its interface on
16
a memory device. It follows that Bennett does not disclose a memory device that performs any of
17
the claimed steps. For example, Bennett does not disclose a memory device that receives an
18
external clock signal, that receives a request for a write operation synchronously with respect to
19
the external clock signal, etc.
20
Second, even if Bennett had disclosed putting its interface on a memory device, as
21
discussed in section II.C above, it still would not disclose programmable write delay. It follows
22
that Bennett does not disclose sampling data, in response to the request for a write operation, after
23
a programmable number of clock cycles of the external clock signal transpire, or storing a value
24
which is representative of the programmable number of clock cycles of the external clock in a
25
programmable register on the memory device.
26
Third, even if Bennett had disclosed putting its interface on a memory device, as
27
set forth in section II.E above, it still would not disclose receiving a set register request.
28
C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW

2 Claim 27 of the ’051 patent claims:
3 27. A memory device having a plurality of memory arrays, wherein

each memory array includes a plurality of memory cells, the
4 memory device comprising:
5 clock receiver circuitry to receive an external clock signal;
6 a programmable register to store a value which is representative of
a number of clock cycles of the external clock signal to transpire
7 before sampling a first portion of data, wherein the first portion of
data is sampled in response to an operation code; and
8
data input receiver circuitry to sample the first portion of data
9 synchronously with respect to the external clock signal.
10 For the reasons set forth above, numerous elements of claim 27 are not disclosed
11 in Bennett. First, the Manufacturers’ arguments are based on the bus interface disclosed in
12 Bennett, but, as discussed in section II.B above, Bennett does not disclose putting its interface on
13 a memory device. It follows that Bennett does not disclose a memory device that contains many
14 of the claim limitations. For example, Bennett does not disclose a memory device containing
15 clock receiver circuitry to receive an external clock signal, containing a programmable register,
16 etc.
17 Second, even if Bennett had disclosed putting its interface on a memory device, as
18 discussed in section II.C above, it still would not disclose programmable write delay. It follows
19 that Bennett does not disclose a programmable register to store a value which is representative of
20 a number of clock cycles of the external clock signal to transpire before sampling a first portion
21 of data.

23 Claim 43 of the ’051 patent depends on claims 34 as follows:
24 34. A memory device having a plurality of memory arrays, the

memory device comprising:
25
first input receiver circuitry to receive an operation code
26 synchronously with respect to an external clock; and
27 second input receiver circuitry to sample data, in response to the
operation code, after a predetermined number of clock cycles of the
28 external clock.
C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
1
43. The memory device of claim 34 wherein the memory device is a
2 synchronous dynamic random access memory.
8 input receiver circuitry to receive an external clock signal, containing a programmable register,
9 etc.
11 discussed in section II.C above, it still would not disclose programmable write delay. It follows
12 that Bennett does not disclose a programmable register to store a value which is representative of
13 a number of clock cycles of the external clock signal to transpire before sampling a first portion
14 of data.

16 Claim 28 of the ’916 patent depends on claim 26 as follows:
17
26. A synchronous semiconductor memory device having at
18 least one memory section including a plurality of memory cells, the
memory device comprising:
19
clock receiver circuitry to receive an external clock signal;
20
first input receiver circuitry to sample block size information
21 synchronously with respect to the external clock signal, wherein the
block size information is representative of an amount of data to be
22 output by the memory device in response to a first operation code;
23 a register which stores a value that is representative of an amount of
time to transpire after which the memory device outputs the first
24 amount of data; and
25 a plurality of output drivers to output the amount of data in
response to the first operation code and after the amount of time
26 transpires.
27 28. The memory device of claim 26 wherein in response to a
second operation code, the value is stored in the register.
28
C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
6 clock receiver circuitry to receive an external clock signal, containing first input receiver circuitry
7 to sample block size information synchronously with respect to the external clock signal, etc.
9 discussed in section II.C above, it still would not disclose programmable read delay. It follows
10 that Bennett does not disclose a register which stores a value that is representative of an amount
11 of time to transpire after which the memory device outputs the first amount of data.
12 Third, even if Bennett had disclosed putting its interface on a memory device, as
13 set forth in section II.D above, it still would not disclose variable block size. It follows that
14 Bennett does not disclose first input receiver circuitry to sample block size information
15 synchronously with respect to the external clock signal.
16 Fourth, even if Bennett had disclosed putting its interface on a memory device, as
17 set forth in section II.E above, it still would not disclose a set register request. It follows that
18 Bennett does not disclose an operation code that directs the memory device to store a value in a
19 register.
21 Claim 16 of the ’863 patent depends on claims 14 and 15 as follows:
22 14. A method of operation in a synchronous memory device,
wherein the memory device includes a plurality of memory cells,
23 the method of operation of the memory device comprises:
24 receiving first block size information from a memory controller,
wherein the memory device is capable of processing the first block
25 size information, wherein the first block size information represents
a first amount of data to be input by the memory device in response
26 to an operation code;
27 receiving the operation code, from the memory controller,
synchronously with respect to an external clock signal; and
28
C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW
1 inputting the first amount of data in response to the operation code.

2 15. The method of claim 14 wherein inputting the first amount
of data includes receiving the first amount of data synchronously
3 with respect to the external clock signal.
4 16. The method of claim 15 wherein the first amount of data is
sampled over a plurality of clock cycles of the external clock signal.
5
For the reasons set forth above, numerous elements of claim 16 are not disclosed
6
in Bennett. First, the Manufacturers’ arguments are based on the bus interface disclosed in
7
Bennett, but, as discussed in section II.B above, Bennett does not disclose putting its interface on
8
a memory device. It follows that Bennett does not disclose a memory device that performs any of
9
the claimed steps. For example, Bennett does not disclose a memory device receiving what the
10
Manufacturers identify with first block size information, receiving an operation code, etc.
11
Second, even if Bennett had disclosed putting its interface on a memory device, as
12
set forth in section II.D above, it still would not disclose variable block size. It follows that
13
Bennett does not disclose receiving first block size information, inputting the first amount of data
14
(which is represented by the block size information) synchronously with respect to the external
15
clock signal, or sampling the first amount of data over a plurality of clock cycles of the external
16
clock signal.
17
III. CONCLUSION
18
For the reasons set forth above, the Court should deny the Manufacturers’ motion for
19
summary judgment of invalidity of the claims at issue based on Bennett.
20
21 DATED: November 14, 2008 MUNGER, TOLLES & OLSON LLP

SIDLEY AUSTIN LLP
22 McKOOL SMITH PC
23
24
By: /s/ Peter A. Detre
25 PETER A. DETRE
26 Attorneys for RAMBUS INC.
27
28
C 05-00334 RMW; C 05-02298 RMW; C 06-00244 RMW

Rambus'S Opp. To Manufacturers' Mot. For Summary Judgment of Invalidity (MSJ No. 1) C 05-00334 RMW C 05-02298 RMW C 06-00244 RMW

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Rambus'S Opp. To Manufacturers' Mot. For Summary Judgment of Invalidity (MSJ No. 1) C 05-00334 RMW C 05-02298 RMW C 06-00244 RMW

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Case 5:05-cv-00334-RMW Document 2536 Filed 11/14/2008 Page 1 of 19

1 Gregory P. Stone (SBN 078329) Rollin A. Ransom (SBN 196126)

15 NORTHERN DISTRICT OF CALIFORNIA, SAN JOSE DIVISION

2 RAMBUS INC., CASE NO. C 05-02298 RMW

11 MICRON TECHNOLOGY INC., et al,

10 STATUTES AND RULES

5 to a synchronous memory device as claimed by Rambus’s patents. Bennett discloses what it

20 patents on summary judgment, the Court should deny their motion.

1 8:10-12. Connecting memory to a controller is a prime example of what Bennett refers to as a

1 E. Bennett Does Not Disclose a Set Register Request

21 will not be set. Id.

22 F. Bennett Does Not Anticipate the Claims at Issue

27 dispute of material fact as to anticipation of each of claims at issue. A number of limitations of

1 1. Bennett Does Not Anticipate Claim 16 of the ’285 Patent

3 13. A method of operation in a memory device having a section of

1 2. Bennett Does Not Anticipate Claim 27 of the ’051 Patent

3 27. A memory device having a plurality of memory arrays, wherein

22 3. Bennett Does Not Anticipate Claim 43 of the ’051 Patent

24 34. A memory device having a plurality of memory arrays, the

15 4. Bennett Does Not Anticipate Claim 28 of the ’916 Patent

1 inputting the first amount of data in response to the operation code.

21 DATED: November 14, 2008 MUNGER, TOLLES & OLSON LLP

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