Education Services Quick Reference Introduction to Verilog

From the Xilinx Education Services Introduction to Verilog course. For more information on Xilinx courses, please visit www.xilinx.com/education.

Module with Procedural Block

`timescale 1 ns / 100 ps `define D_WIDTH 8 module MY_CNTR # ( parameter Q_WIDTH = 8 ) ( input CLK, LOAD, CE, RST, UPDN, input [ `D_WIDTH -1 : 0 ] D, output reg [ Q_WIDTH -1 : 0] Q ) ; // `timescale declaration; specifies time units within module // `define; could be used for global constant // module declaration and label; V 01 parameter declaration // V 01 ANSI-C style port declaration, comma separated ports // port declaration with user-specified `define // port declaration with user-specified parameter, variable data type

always @ ( posedge CLK, negedge RST ) begin if ( RST == 1b0 ) Q <= 0 ; else if ( CE == 1'b1) if ( LOAD ) Q <= D ; else if ( UPDN == 1'b1 ) Q <= Q + 1; else Q <= Q - 1; end endmodule

// procedural block declaration with sensitivity list in parentheses // begin procedural block; required if more than one statement enclosed // asynchronous reset; must be tested within block and part of sensitivity // use non-blocking assignment for sequential logic // else if; treated as alternative to if // simplified text; this test, and others, could be written as if ( LOAD) // use non-blocking assignment for sequential logic

// close procedural block; FYI: begin/end not required in this example // close module declaration

Building Hierarchy and Internal Wire Declaration

`timescale 1 ns / 100 ps module AND_OR ( input [3:0] INP, output Y ) ; wire SIG1, SIG2 ; MY_AND2 U0 ( .A(INP[0]), .B(INP[1]), .C(SIG1)) ; MY_AND2 U1 ( .A(INP[2]), .B(INP[3]), .C(SIG2)) ; MY_OR2 U2 ( .A(SIG1), .B(SIG2), .C(Y)) ; endmodule // `timescale declaration, specifies time units within module // V 01 ANSI-C-style port declaration, comma separated ports list // declare 1-bit signals, local to this module // lower-level component declaration and instantiation // using named association, explicit port/signal mapping // each instance must be uniquely labeled // close module declaration

2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

LANG12000-10-QR (v1.0) January 15, 2009 Quick Reference Card Page 1 of 6

www.xilinx.com 1-800-255-7778

Education Services Quick Reference Introduction to Verilog

From the Xilinx Education Services Introduction to Verilog course. For more information on Xilinx courses, please visit www.xilinx.com/education.

wire(s), reg(s), Header Files, and `include

wire A, B, C ; wire [7:0] DATA_BUS ; reg [7:0] Q ; reg [7:0] Q = 8b0000_0000 ; // local signal declaration, within module, scalar (1-bit wide) // local signal declaration, within module, vector (n-bit wide) // local variable declaration, within module or subprogram, vector (n-bit wide) // local variable declaration, initialized, affects simulation only

`define DEPTH 512 `define WIDTH 8 `define ADDR 9

// example of global declarations typical to a header file // example of global declarations typical to a header file // this file saved as MY_HEADER.h (use .h for Xilinx XST)

`include MY_HEADER.h module RAM512 ( . . .

// make contents of header file visible in module; state path if necessary

case and if/else

always @ ( SEL, A,B,C, D ) case ( SEL ) 2b00: Y = A ; 2b01: Y = B ; 2b10: Y = C ; 2b11: Y = D; default: Y = 1bx ; endcase // V 01, combinatorial logic can be modeled using always @ * // selector expression must be in parentheses // each possible value constitutes new branch for case statement // each branch can contain one or more statements based on that condition // each condition should be mutually exclusive // should cover every possible value for selector expression // default is used for conditions not explicitly covered; aids simulation // close case expression, required

always @ ( SEL, A,B,C, D ) if ( SEL == 2b00 ) Z = A ; else if ( SEL == 2b01 ) Z = B ; else if ( SEL == 2b10 ) Z = C ; else if ( SEL == 2b11 ) Z = D ; else Z = 1bx ;

// V 01, combinatorial logic can be modeled using always @ * // Boolean expression must be in parentheses // each possible value constitutes new branch for if/else statement // each branch can contain one or more statements based on that condition // each condition should be mutually exclusive to avoid priority-encoded logic // default is used for conditions not explicitly covered; aids simulation

2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

LANG12000-10-QR (v1.0) January 15, 2009 Quick Reference Card Page 2 of 6

www.xilinx.com 1-800-255-7778

Education Services Quick Reference Introduction to Verilog

From the Xilinx Education Services Introduction to Verilog course. For more information on Xilinx courses, please visit www.xilinx.com/education.

FSM and Local Parameters

module STAT_MACH ( input A, B, CLK, RST, output reg [6:0] OUT1 ) ;

localparam [2:0] INIT = 3b001, LOAD = 3b010, JUMP = 3b100 ; reg [2:0] CURR_STATE, NEXT_STATE ;

// local parameter declaration; cannot be changed from elsewhere // each local parameter declared to be 3-bits wide, comma separated // close declaration with semicolon; will be used to model FSM states // local signal declaration; will be used to store state values

always @ ( posedge CLK, negedge RST ) begin : SYNC if ( !RST ) CURR_STATE <= INIT; else CURR_STATE <= NEXT_STATE ; end always @ ( A, B, CURR_STATE) begin : COMB case ( CURR_STATE ) INIT: begin OUT1= 7d47; NEXT_STATE = LOAD; end LOAD: begin OUT1 = 7d11; if ( A == 1b1 && B == 1b1 ) NEXT_STATE =JUMP; else if ( A == 1b1 && B == 1b0 ) NEXT_STATE = INIT; else NEXT_STATE = LOAD; end JUMP: begin NEXT_STATE = INIT; OUT1 = 7d68; end default: begin NEXT_STATE = INIT; OUT1 = 7d47; end endcase end endmodule

// clocked procedural block for current_state --registered output(s) // example of block label // test for RST assertion, could be written as if ( !RST) or ( RST == 1b0) // using non-blocking for sequential assignment // default assignment each clock edge // end procedural block // combinatorial process for next-state and combinatorial output(s) // optional block label // use case statement to model individual FSM states // begin/end required because more than one assignment per branch // assign to output, specifying decimal to enhance readability // assign to NEXT_STATE, using blocking assignment (combinatorial)

// combinatorial; updates on same clock edge as CURR_STATE // use if/else within branch of case to model input conditions

// explicit else should be used to maintain state // end this branch of case

2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

LANG12000-10-QR (v1.0) January 15, 2009 Quick Reference Card Page 3 of 6

www.xilinx.com 1-800-255-7778

Education Services Quick Reference Introduction to Verilog

From the Xilinx Education Services Introduction to Verilog course. For more information on Xilinx courses, please visit www.xilinx.com/education.

Testbench and Basic Input Stimulus

`timescale 1 ns / 100 ps module STAT_MACH_TB ( ) ; // general recommendation; label testbench same as Unit Under Test (UUT) // testbench module declared without ports; standalone top-level unit reg A_SIG = 1b0 ; reg B_SIG = 1b0 ; reg CLK_SIG = 1b0 ; reg RST_SIG ; wire [6:0] OUT1_SIG ; STAT_MACH UUT ( .A(A_SIG), .B(B_SIG), .CLK(CLK_SIG), .RST( RST_SIG), .OUT1(OUT1_SIG )); always #10 CLK_SIG = ~ CLK_SIG ; initial begin RST_SIG = 1b1 ; #25 RST_SIG = 1b0 ; #15 RST_SIG = 1b1 ; end always begin #200 A_SIG = 1b1 ; B_SIG = 1b0 ; # 200 A_SIG = 1b1 ; B_SIG = 1b1 ; # 200 A_SIG = 1b0 ; B_SIG = 1b1 ; end endmodule // declare local signals that connect to component; drive UUT stimulus // A_SIG and B_SIG need separate declarations due to initialization // declare local signals that connect to component; initialize value // declare local signals that connect to component; monitor UUT outputs // instantiate component to be tested; recommended label instance as UUT // port map, map lower-level ports to upper-level signals

// simple clock model with fixed period; requires that signal first be initialized // initial block used to create input stimulus for RST signal // sequential stimulus; all times relative within the procedural block // RST set to value of logic 1 at sim time 0 // RST set to value of logic 0 (assertion level) at sim time 25 // RST set to value of logic 1 (de-assertion ) at sim time 40

// sequential stimulus; all times relative within the procedural block // procedural block suspends for 200 ns

// procedural block suspends for 200 ns

// procedural block suspends for 200 ns

// procedural repeats, starting at top // close module declaration

2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

LANG12000-10-QR (v1.0) January 15, 2009 Quick Reference Card Page 4 of 6

www.xilinx.com 1-800-255-7778

Education Services Quick Reference Introduction to Verilog

From the Xilinx Education Services Introduction to Verilog course. For more information on Xilinx courses, please visit www.xilinx.com/education.

Subprograms: function and task

module PAR_GEN_FUNC ( input [7:0] D_WORD, output [8:0] DATA_FRAME ) ; function PAR_GEN ( input [7:0] BV ) ; reg PAR ; integer i ; begin PAR = 1b0 ; for ( i = 0; i < 8; i = i + 1 ) PAR = PAR ^ BV [i] ; PAR_GEN = PAR ; end endfunction // function declaration, using V 01 ANSI-C-style for arguments // local variable declaration; visible only within function // local integer declaration; used within loop construct // start of function body // initialize PAR // for loop construct, with bounds set to 8 // each loop iteration, xor PAR with corresponding element from bus // return specification; required in this example // close function declaration

assign DATA_FRAME = { D_WORD PAR_GEN ( D_WORD )} ; // call function; pass in argument (D_WORD) returns PAR // D_WORD concatenated w/PAR, assigned to signal DATA_FRAME endmodule module PAR_GEN_TASK ( input [7:0] D_WORD, output [8:0] DATA_FRAME ) ; reg PAR_SIG ; task PAR_GEN ( input [7:0] BV, output PAR_OUT ) ; reg PAR ; integer i ; begin PAR = 1b0 ; for ( i = 0; i < 8; i = i + 1 ) PAR = PAR ^ BV [i] ; PAR_OUT = PAR ; end endtask always @ ( D_WORD ) PAR_GEN ( D_WORD, PAR_SIG ) ; assign DATA_FRAME = { D_WORD, PAR_SIG } ; endmodule // declare variable, passed in as actual argument // task declaration, using V 01 ANSI-C-style for arguments // local variable declaration, visible only within task // local integer declaration, used within loop construct // start of task body // initialize PAR // for loop construct, with bounds set to 8 // each loop iteration, xor PAR with corresponding element from bus // assign to output signal // close task body // close task declaration // trigger based on any change to input bus // call task, pass in arguments (D_WORD, PAR_SIG) // returns updated PAR_SIG; used in expression; D_WORD is // concatenated with PAR_SIG, assigned to signal DATA_FRAME

2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

LANG12000-10-QR (v1.0) January 15, 2009 Quick Reference Card Page 5 of 6

www.xilinx.com 1-800-255-7778

Education Services Quick Reference Introduction to Verilog

From the Xilinx Education Services Introduction to Verilog course. For more information on Xilinx courses, please visit www.xilinx.com/education.

Using $readmemb
`timescale 1ns / 1ps module SIMPLE_CALC_FILEIO_TB_v; reg CLK_TB = 1'b0; reg RESET_TB = 1'b0; wire RESULT_TB; // declare 1-D array, 17 bits wide, 8 words deep here, label as INPUT_ARRAY reg [`WIDTH-1:0] INPUT_ARRAY [0:2**`ADDR] ; // end of declaration ///////////////////// // solution at bottom of file //////////// reg [`WIDTH-1:0] DATA_FRAME = 0; // declare $readmemb statement here, load data from MY_INUT.txt to INPUT_ARRAY initial $readmemb ( "MY_INPUT.txt", INPUT_ARRAY ); // end of declaration ///////////////////// // solution at bottom of file ////////////

initial begin #80 DATA_FRAME = INPUT_ARRAY[0]; #80 DATA_FRAME = INPUT_ARRAY[1]; #80 DATA_FRAME = INPUT_ARRAY[2]; #80 DATA_FRAME = INPUT_ARRAY[3]; #80 DATA_FRAME = INPUT_ARRAY[4]; #80 DATA_FRAME = INPUT_ARRAY[5]; #80 DATA_FRAME = INPUT_ARRAY[6]; #80 DATA_FRAME = INPUT_ARRAY[7]; end

2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

LANG12000-10-QR (v1.0) January 15, 2009 Quick Reference Card Page 6 of 6

www.xilinx.com 1-800-255-7778