IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO.

1, JANUARY 2002

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A Wideband CMOS SigmaDelta Modulator With Incremental Data Weighted Averaging

Tai-Haur Kuo, Member, IEEE, Kuan-Dar Chen, and Horng-Ru Yeng
AbstractA low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigmadelta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25- m CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dispissation is less than 105 mW and the active area is 2.6 mm2 . Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance. Index TermsAnalog-to-digital converters, CMOS analog integrated circuits, deltasigma modulators, dynamic element matching, mixed analogdigital integrated circuits, switched capacitor circuits.

I. INTRODUCTION OMMUNICATION applications drive the development of high-resolution (1214 bit) sigmadelta analog-to-digital converters (ADCs) with a signal bandwidth greater than 1 MHz. Combining sigmadelta modulators (SDMs) with multibit quantization is an effective means to achieve a high dynamic range and a wide bandwidth. The major obstacle in designing multibit SDMs is that very good component matching is required for internal digital-to-analog converter (DAC) linearity. Good attenuation of DAC noise due to component mismatches can be provided by the data weighted averaging (DWA) algorithm, which ideally can achieve a first-order DAC noise shaping. However, the DWA can cause significant baseband tones, resulting in reduction of SDM performance [1]. Although the tone problem can be circumvented by rotated
Manuscript received June 4, 2001; revised September 24, 2001. This work was supported by the Taiwan Semiconductor Manufacturing Company (TSMC). T.-H. Kuo is with the Department of Electrical Engineering, National Cheng Kung University, Tainan City 70101, Taiwan, R.O.C. (e-mail: thkuo@msic.ee.ncku.edu.tw). K.-D. Chen was with the Department of Electrical Engineering, National Cheng Kung University, Tainan City 70101, Taiwan. He is now with VIA Technologies, Taipei, Taiwan, R.O.C. H.-R. Yeng is with the Design Service Division, Taiwan Semiconductor Manufacturing Company (TSMC), Hsin-Chu, Taiwan. He is now with Innochip Technology, Inc., Hsin-Chu, Taiwan, R.O.C. Publisher Item Identifier S 0018-9200(02)00135-X.

DWA [2] and bi-directional DWA [3], which were proposed and implemented in these years, these techniques contribute additional noise to the baseband and result in the degradation of first-order DAC noise shaping. To increase DAC noise shaping ability, several second-order mismatch-shaping techniques [4] have been proposed, but very complex implementation is needed and circuit speed is limited. Hence, for cost and power considerations, first-order shaping is preferred. In [5], coauthors Chen and Kuo proposed a very efficient technique, referred to as incremental data weighted averaging (IDWA) algorithm, for moving DAC tones away from the baseband without increasing baseband noise. Hence, IDWA can achieve ideal first-order mismatch shaping. In this paper, a low-complexity high-speed circuit is proposed for the implementation of the IDWA. Previously, most published wideband sigmadelta modulators used cascaded structures. In this paper, a single-stage feedforward (FF) SDM is implemented for wideband applications. In addition, the effects of circuit nonidealities on the FF SDM are evaluated by using behavioral simulations. Such analysis helps generate critical circuit specifications and avoid circuit over-design in area and power. Incorporating the IDWA technique, a fourth-order FF SDM with an oversampling ratio (OSR) of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25- m CMOS process. This paper is organized as follows. In Section II, structure and coefficients of a wideband multibit FF SDM are designed. The performance of the SDM using IDWA is analyzed. In Section III, the circuit implementation of the IDWA is proposed. In Section IV, the detailed analog circuit implementation of the SDM using IDWA is presented. In Section V, measurement results of the implemented SDM are presented. Finally, conclusions are presented in Section VI. II. IDWA FOR WIDEBAND SDMs A. SDM Structure and Coefficients For most wideband applications, the ADC resolution required is up to 14 bits. In this paper, the target is to design a 14-bit wideband SDM employing IDWA for the reduction of the mismatch noise in the baseband. The single-stage FF structure is adopted and its structural coefficients are synthesized by an in-house tool, the high-order sigmadelta modulator synthesis tool (HOST) [6]. In HOST, high-pass inverse-Chebyshev functions are used to design SDM noise transfer functions (NTFs). Design concerns including stability, 1% SDM coefficient tolerances for circuit component mismatch, reduction of in-band tones, design tradeoffs among in-band quantization noise suppression, OSR, modulator order, and quantizer resolution are

00189200/02$17.00 2002 IEEE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002

Fig. 1.

Structure and coefficients of a fourth-order FF SDM where H (z ) = z

=(1 0 z

).

taken into consideration for SDM coefficient synthesis. In order to achieve a wide signal bandwidth, the OSR must be as low as possible, because the higher sampling frequency imposes increasing demands on circuit speed and power consumption. A synthesized fourth-order FF SDM with a 4-bit quantizer resolution and an OSR of 12 can achieve a maximum stable input of 5 dB, a peak signal-to-noise ratio (PSNR) of 90 dB, and a dynamic range of 88 dB, if circuit nonidealities and noise coupling are not considered. The FF SDM with its structural coefficients is shown in Fig. 1. The maximum and minimum output voltages and , respecof the internal DAC are is the common-mode voltage. tively, where B. IDWA Technique To illustrate the principle of IDWA, a simple example is given. For a 4-bit DAC, one IDWA example is shown in Fig. 2 where 16 unit elements are used, instead of 15 for a conventional DAC. Fig. 2 shows that IDWA operates like a conventional DWA, in which DAC elements are selected in a circular way. Moreover, in IDWA, one extra element is added to shift the notable tones away from the baseband. As described in [5], SDM baseband tones are closely correlated to the number elements used of unit elements used in the DAC. For is the original DAC element number in the IDWA, where is the number of added extra element(s), the tones are and shifted to if is odd (1) where is the greatest common divisor (gcd) value of the and the number of . Because tones can number of be moved to out-of-band, total in-band DAC noise power due to element mismatches can be lowered. Therefore, a careful and can result in a DAC noise floor lower choice of

Fig. 2. Element selection algorithm of IDWA.

than the first-order shaping curve, , in the baseband. or fixed due to the reuse of Under two cases, large choices may not shift all the existing circuitry, some tones to the out-of-band and the first tone may be located in the baseband. Based on numerous simulations, the total inband mismatch noise power is still lower than that calculated from the first-order shaping curve because the noise power amount moved from the baseband to the frequencies as in (1) is usually larger than that of the first tone. For the 4-bit FF SDM synthesized above, its is 15. In the following simulations, 3- of 0.45% statistical component mismatch is used. This mismatch value is for 0.2-pF unit capacitors used for DAC implementation in this paper. For DWA with 15 elements and IDWA with elements, IDWA with elements, their DAC mismatch noise spectra generated in the FF SDM with a 33 dB input are shown in Fig. 3(a)(c), respectively, where ideal first-order noise shaping curves are also added for performance comparison. As shown in Fig. 3, DWA has large inband tones. No obvious baseband tones are observed elements, and the out-of-band tones are for IDWA with in accordance with (1). approximately located at elements is still The inband noise power of IDWA with 7 dB lower than that calculated from the ideal first-order shaping , although the first-tone according to (1) is locurve, . In Fig. 3(b) and (c), some tones predicted by (1) cated at

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KUO et al.: A WIDEBAND CMOS SIGMADELTA MODULATOR WITH INCREMENTAL DATA WEIGHTED AVERAGING

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Fig. 3. Mismatch noise spectra of (a) DWA with 15 elements, (b) IDWA with elements, and (c) IDWA with in Fig. 1, f is the sampling frequency, and BW is signal bandwidth. The input frequency is f /512.

15 + 1

15 + 3 elements, where the SDM is shown

cannot obviously be observed when the 32 768 points FFT is used. When larger component mismatches are used, more pronounced tones can be observed at the frequencies predicted by (1). elements is used for DAC In this paper, IDWA with implementation, which is already good enough for the FF SDM synthesized above, and can reuse our previously designed modulo-15 circuit cells. The two lower curves of Fig. 4 show elements. the dynamic range plot of the FF SDM with The SNDR performance of the FF SDM with IDWA is almost the same as that of the FF SDM without capacitor mismatch. To demonstrate the capabilities of IDWA for a higher OSR, the two upper curves of Fig. 4 show that another fourth-order 4-bit FF SDM with IDWA and an OSR of 24, which is also synthesized using HOST, can achieve very high SNDR, compared with the same SDM using DWA. Hence, IDWA has very good performance for both high OSRs and low OSRs. With a lower OSR, SDMs can achieve a wider bandwidth and require lower circuit speed and lower power. III. CIRCUIT IMPLEMENTATION OF IDWA A. IDWA Control Circuit In this paper, a low-complexity high-speed circuit for the implementation of the IDWA technique is proposed, as shown in Fig. 5. The IDWA circuit converts the 4-bit SDM quantizer

Fig. 4. Dynamic range plots of two fourth-order 4-bit FF SDMs with elements, where 3- of 0.45% statistical component mismatch is used. The modulator structure and coefficients for the two lower curves are in Fig. 1. The modulator structure for the two upper curves is the same as that in Fig. 1 and its coefficients are g : ,g : ,g : ,g : ,a : , a : ,a : ,a : ,b : ,b : ,b : , and b : , respectively. The input frequency is f = .

15 +

= 4 90 = 0 73 = 0 53 = 0 25 = 0 17 = 0 60 = 0 004 = 0 06

= 0 04 = 0 02 512

= 0 29 = 0 11

output to the control signals, , , for the element selection of a 4-bit DAC. The conversion has to be completed within half a sampling period. A 4-bit adder and a 4-bit

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002

TABLE I SUMMARY OF CIRCUIT SPECIFICATIONS OF THE FF MODULATOR

Fig. 5. Proposed circuit diagram for the IDWA realization.

DAC. Therefore, seven unit capacitors are connected to and nine unit capacitors are connected to , which results in an offset voltage. In order to cancel the offset voltage, the extra in Fig. 6 is added and is always connected to unit capacitor when is high. The area occupied by these two extra SC units is negligible compared with that of the whole SDM. IV. SDM CIRCUIT IMPLEMENTATION DETAIL A. Circuit Nonidealities Evaluation Time-domain behavioral simulations are necessary for quick performance evaluation of SDMs with circuit nonidealities. Such analysis provides detailed insight that helps minimize nonidealities which ultimately limit performance. Moreover, such analysis helps avoid circuit over-design in area and power. The impact of major circuit nonidealities, including operational amplifier (opamp) frequency response, opamp nonlinearity, capacitor mismatch, switch resistance, clock jitter, and noise budget, is evaluated and then the required circuit specifications are obtained, as in Table I. The following SDM circuits are designed with a reference to the required specifications. B. Switched-Capacitor Integrator SDM performance is generally limited by the SC integrator circuits. For the fully differential SC integrator with dual-reference voltages, where the maximum stable input magnitude and V is (about 5 dB) half of the full scale of the DAC output voltage, the sampling pF is taken for capacitance of the first integrator dB. This still leaves a margin for the noise PSNR contributed by other nonidealities. The sampling capacitance of the second to fourth integrators are 1.5, 1, and 1 pF, respectively. The latter stages have smaller sampling capacitances due to their allowance of a higher level of circuit noise. The minimum capacitance for each integrator stage is the capacitor used to implement the NTF zero. These small capacitances are limited by matching considerations in the process. For the MOS switches, the reduced supply voltage from 5 V/3.3 V to 2.5 V increases the switch turn-on resistance and degrades the SC integrator settling performance. This issue is solved by using large enough switch sizes. The effective settling period is 8 ns for a half period of the 48-MHz clock rate with nonoverlapped duration. For the designed SDM with an input

register generate two indexes and . Two binary-tothermometer decoders convert the two indexes to two 16-bit and , respectively, outputs, and are always low. When the carry output of where , the output control the adder is low indicating are the mutual exclusive-OR of and . On the signals contrary, when the carry output of the adder is high indicating , the output control signals are the mutual exclusive-NOR of and . The delay time from the input to the output of the IDWA circuit is around 4 ns for the 0.25- m CMOS technology used in this paper. The total gate count of the IDWA circuit is 295. Aggressive full custom design of the IDWA circuit could further reduce its gate count. Therefore, the proposed IDWA implementation can not only operate at high speed but also have low circuit complexity and small area. B. Implementation of a Multibit DAC With IDWA A simplified schematic of the first integrator stage is shown in Fig. 6. This fully differential stage incorporates a 4-bit feedback DAC at the input sampling network. The DAC is implemented by switched-capacitor (SC) circuits, where the unit caand are pacitance is 0.2 pF and the reference voltages and are nonoverlap1.925 and 0.575 V, respectively. is high, analog input signal is samping clocks. When is high, the pled in the unit capacitors of the DAC. When connections of the unit capacitors are controlled by the IDWA , as shown in Fig. 5. When is output signals, 1 (or 0), the corresponding unit capacitor will be connected (or ). The normal capacitor array would contain to 15 units. Here, however, there are 17; one of the extra units is for the IDWA technique, and the other is for voltage level shifting. The reason why level shift is needed is explained as could be follows. If the DAC input code is 7, the 000 000 011 111 1100, where there are seven ones and nine zeroes instead of seven ones and eight zeroes in a conventional

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KUO et al.: A WIDEBAND CMOS SIGMADELTA MODULATOR WITH INCREMENTAL DATA WEIGHTED AVERAGING

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Fig. 6.

First integrator stage where only the noninverting portion is shown, although it is a fully differential type.

Fig. 7. Gain-boosted folded-cascode amplifier.

magnitude of , the nMOS and pMOS switch sizes ) used for input sampling networks are 3 m/0.24 m ( and 12 m/0.24 m, respectively. The size of nMOS switches is 10 m/0.24 m. The sizes of nMOS and connected to pMOS switches in the feedback path are 1 m/0.24 m and 4.3 m/0.24 m, respectively. The second to fourth integrator stages all use the same opamp, as in Fig. 7. C. Gain-Boosted Folded-Cascode Amplifier A folded-cascode amplifier is adopted to implement SC integrators for high-speed considerations. In order to achieve the minimum required gain, an amplifier gain of the order of and the use of gain-boosted circuits for the folded-cascode amplifier are needed, in particular for transistors with short channel lengths. Fig. 8 shows the simulated open-loop gain of the gain-boosted amplifier. The gain presents a maximum value in the center of the scale and decreases as the output voltage approaches the end

of the saturation region. The open-loop gain is curve fitted by using a second-order polynomial equation to model gain nonlinearity where its maximum gain is 7700, first-order nonlinearity is 0.01, and second-order nonlinearity is 0.5, respectively. The maximum achievable signal-to-distortion ratio (SDR) of the SC integrator is 94 dB, considering only amplifier gain nonlinearity, which leaves a large margin for process variation. The simulated amplifier performance is shown in Fig. 7. The amplifier also contributes thermal noise to SC integrators. The calculated input referred thermal noise for the gain-boosted folded-cascode amplifier is 90 dB below the maximum signal power. D. Other Circuitry The SDM summing stage is implemented with SC circuits. The 4-bit quantizer is implemented with a flash ADC architecture where a unit resistance of 640 is used for the reference ladder, the fully differential SC comparator is adopted, and its comparator core includes a pre-amplifier stage and a latch stage.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002

Fig. 8.

Simulated opamp gain nonlinearity. Fig. 10. FFT plot of the measured modulator output for 30-MHz sampling frequency.

Fig. 9.

Microphotograph of the SDM chip.

All the timing phases are generated by a nonoverlapped clock generator circuit. V. EXPERIMENTAL RESULTS The SDM was fabricated with a 2.5-V 0.25- m 1P5M CMOS mixed-mode process where the typical nMOS and pMOS threshold voltages are 0.55 and 0.55 V, respectively. Linear capacitors were implemented using metalinsulatormetal (MIM) capacitors, which have capacitance values of approximately 1 fF/ m . The first-order and second-order capacitor voltage coefficients are about 50 ppm and 15 ppm, respectively, for a 0.5-pF capacitor. The chip layout and floorplan of the SDM are shown in Fig. 9. The active circuitry occupies an area of 2.6 mm . In the following measurements, 400-kHz sinusoidal inputs are used and the modulator operates from a 2.5-V supply voltage. At a sampling frequency of 30 MHz, the output power spectrum density of the SDM with a 8-dB input is shown in Fig. 10, where a 16 384-point FFT is taken. The flat baseband

Fig. 11. Plots of the measured SNDR for 30- and 48-MHz sampling frequencies.

noise floor reveals that with the IDWA technique, no significant baseband tones are observed in the SDM output. At sampling frequencies of 30/48 MHz, the modulator with signal bandwidths of 1.25/2 MHz achieves respective dynamic ranges of 84/80 dB, peak signal-to-(noise distortion) ratios (PSNDRs) of 80/74 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB. The SNDR plots are shown in Fig. 11. The power consumption measured with 48-MHz sampling frequency is 85 mW for the analog portion and 20 mW for the digital portion. When the SDM operates up to 60 MHz, higher than 80-dB SFDR is measured in a 2.5-MHz bandwidth. The measured performance of the SDM is summarized in Table II. For comparison purposes, two recently published 3.3-V/3-V CMOS wideband SC SDMs with comparable SNDR performance [7], [8] are also given in the table. The implemented 2.5-V FF SDM achieves less power, lower supply voltage, lower OSR, and wider bandwidth.

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TABLE II PERFORMANCE SUMMARY OF THE IMPLEMENTED FF SDM AND TWO RECENTLY PUBLISHED 3.3-V/3-V CMOS WIDEBAND SDMS

[7] Y. Geerts, A. M. Marques, M. S. J. Steyaert, and W. Sansen, A 3.3-V, 15-bit deltasigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications, IEEE J. Solid-State Circuits, vol. 34, pp. 927936, July 1999. [8] J. C. Morizio, M. Hoke, T. Kocak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, M. H. Hood, G. Lynch, H. Kondoh, T. Kumamot, T. Okuda, H. Noda, M. Ishiwaki, T. Miki, and M. Nakaya, 14-b 2.2-MS/s sigmadelta ADC, IEEE J. Solid-State Circuits, vol. 35, pp. 968976, July 2000.

VI. CONCLUSION The low-complexity high-speed implementation of the IDWA technique for the reduction of baseband tones of the multibit SDM is proposed. A 2.5-V wideband FF SDM with the IDWA technique has been successfully implemented in a 0.25- m CMOS technology and has achieved very good performance, especially in power consumption, area, and bandwidth, due to the use of IDWA and a lower OSR. More aggressive scaling of the power dissipation in the opamps used for the latter stages could further lower modulator power dissipation. REFERENCES

Tai-Haur Kuo (S87M88) was born in Tainan, Taiwan, R.O.C., in 1960. He received the B.S. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1982 and the M.S. and Ph.D. degrees in electrical engineering from the University of Maryland, College Park, MD, in 1988 and 1990, respectively. From 1984 to 1986, he was with Industrial Technology and Research Institute, Hsin-Chu, Taiwan, working as an Analog IC Designer, where he received an Annual Personal Special Contribution Award in 1986. During the summer of 1989, he was with the Aerospace Space Technology Center of Allied-Signal, Columbia, MD, performing research work on the design and simulation of monolithic ultrahigh-speed RTD-HEMT ICs. From 1990 to 1992, he was initially a Design Engineer with Integrated Device Technology in Santa Clara, CA, and then a Project Manager with Industrial Technology and Research Institute. Since 1992, he has been with the Department of Electrical Engineering, National Cheng Kung University, where he is currently a Professor. His current research interests include data converters and filters. He holds seven U.S. patents.

[1] R. T. Baird and T. S. Fiez, Linearity enhancement of multibit A/D and D/A converters using data weighted averaging, IEEE Trans. Circuits Syst. II, vol. 42, pp. 753762, Dec. 1995. [2] R. E. Radke, A. Eshraghi, and T. S. Fiez, A 14-bit current-mode DAC based upon rotated data weighted averaging, IEEE J. Solid-State Circuits, vol. 35, pp. 10741084, Aug. 2000. [3] I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S. Chan, A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit deltasigma modulation at 8 oversampling ratio, IEEE J. Solid-State Circuits, vol. 35, pp. 18201828, Dec. 2000. [4] I. Galton, Spectral shaping of circuit errors in digital-to-analog converters, IEEE Trans. Circuits Syst. II, vol. 44, pp. 808817, Oct. 1997. [5] K.-D. Chen and T.-H. Kuo, An improved technique for reducing baseband tones in sigmadelta modulators employing data weighted averaging algorithm without adding dither, IEEE Trans. Circuits Syst. II, vol. 46, pp. 6368, Jan. 1999. [6] T.-H. Kuo, K.-D. Chen, and J.-R. Chen, Automatic coefficients design for high-order sigmadelta modulators, IEEE Trans. Circuits Syst. II, vol. 46, pp. 615, Jan. 1999.

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Kuan-Dar Chen was born in Tainan, Taiwan, R.O.C., in 1970. He received the B.S. and Ph.D. degrees in electrical engineering from the National Cheng Kung University, Tainan, in 1994 and 2000, respectively. In 2000, he joined the Mixed Signal Department of VIA Technologies, Inc., Taiwan, where he is a Member of Technical Staff. His main research interests are in the design of analog and mixed-signal integrated circuits, including high-resolution and high-speed sigmadelta converters, high-speed data converters, and continuous-time filters. Dr. Chen received the NSC Creativity Awards in 1995 and 1996, respectively. He received the Golden Prize of the Acer Thesis Award in 2000.

Horng-Ru Yeng received the M.S. degree in computer engineering from Syracuse University, Syracuse, NY, in 1989. He was with Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, as a Manager working on mixed-signal library development. Currently, he is in charge of Innochip Technology Inc., an ASIC and design service company with TSMC foundry.

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