Model Question Paper Computer System Architecture (BC141)

Section A
Answer any two of the four questions given below: 1. a. b. c. 2. a. b. What is the importance of cache memory? Discuss different types of cache memory. Registers are storage units that hold data values, programming instructions and memory addresses. Explain the functionality of various types of registers. Explain the functionality of master-slave J-K flip-flop with a block diagram. Construct a full-subtractor with two half-subtractors and an OR gate. Explain the following addressing modes: i. ii. c. 3. a. b. Indirect addressing mode. Register addressing mode. ( 6 marks) ( 8 marks) ( 6 marks) (2 20 = 40 marks) ( 8 marks)

( 6 marks) ( 6 marks) ( 6 marks)

Construct AND, OR, NOT gates using NAND and NOR gates. Write short notes on impact and non-impact printers. Perform the M-N operation for the following M and N numbers using 1s complement and 2s complement: i. ii. M=1010100 N=1000100 M=1000100 N=1010100.

( 8 marks) ( 6 marks) ( 8 marks) ( 6 marks)

c. 4. a. b. c.

Discuss the characteristics of Reduced Instruction Set Computer (RISC) architecture. Explain on what criteria the performance of the disk is measured. Discuss the characteristics of different types of Read Only Memory (ROMs). Explain the function of 4-bit bidirectional shift register with parallel load using a block diagram.

( 6 marks)

Section B
Answer any two of the three questions given below: 5. a. b. 6. a. Draw the characteristic tables for D flip-flop and T flip-flop. Draw the block diagram of 4-bit adder-subtractor and explain its functionality. Convert the 16-bit binary number 1101100101100110 into Octal and Hexa-decimal number systems. Prove (A' B + B' A)' = A 'B' + AB. What are the different types of sequential circuits? Explain. Construct 8-to-1 multiplexer using four 2-to-1 multiplexers. (2 10 = 20 marks) ( 5 marks) ( 5 marks)

( 5 marks) ( 5 marks) ( 5 marks) ( 5 marks)

b. 7. a. b.

Page 1 of 18

Section C
Answer any two of the four questions given below: 8. (2 20 = 40 marks) Design a two bit binary counter. This is a sequential circuit with two flip flops (JK flip flop) and one input x. When x=0, the state of the flip flops does not change and when x=1, the circuit goes through a sequence of repeated binary states 00,01,10,11, and so on. ( 20 marks) i. ii. Express the Boolean function F = A + B'C in a sum of minterms. The function F has three variables A, B, C. Express the Boolean function three variables x, y, z.

9.

F = xy + x'z in a product of maxterms. The function F has

( 20 marks)

10.

Write three address, two address and one address instructions to compute the given Y value: Y= (A-B)/(C+D E) ( 20 marks)

11.

What is Redundant Array of Independent Disks (RAID)? Explain in detail the characteristics of different RAID levels. ( 20 marks) END OF QUESTION PAPER

Page 2 of 18

Suggested Answers Computer System Architecture (BC141)

Section A
1. a. Importance of cache memory The registers built into the CPU are accessible within one cycle of the CPU clock. But the access to main memory may take many CPU cycles. This is because the main memory is accessed via a transaction on the memory bus. So, the CPU has to stall if it does not have the required data to complete the instruction in execution. This may result in frequent memory accesses and this situation is not satisfactory. To solve this problem a fast memory called cache memory between the CPU and the memory is added. It acts as a buffer to reduce the time of the memory access. When the data present in main memory is used, it is copied onto the cache on temporary basis with the assumption that it may be required again. So when a particular data is needed, it is first checked in cache. If it is present in cache the data is used directly from cache and if it is not present then it is retrieved from main memory again putting a copy in cache. It holds the currently active segments of a program and their data. Main memory can be viewed as a fast cache for secondary storage, because data should be moved from secondary storage to the main memory before it is used by the CPU and data should be present in the main memory before it is moved to the secondary storage. The movement of information between different levels of storage hierarchy may be either explicit or 'implicit, depending on the hardware design and the controlling operating system software. For example, the data transfer between cache and CPU and registers is usually a hardware function, with no operating-system intervention. Also the transfer of data between disk and main memory is usually controlled by the operating system. Types of Cache Memory There are two types of cache memory. One is the primary cache which is included in the microprocessor chip and the other is the secondary cache or level 2 (L2) cache which is included on a separate printed circuit board. To improve the secondary cache performance, microprocessors are provided in plastic modules that contain a special type of secondary cache, called backside cache. Performance can be improved by keeping the secondary cache as close as possible. b. S. No. 1. 2. 3. 4. 5. 6. c. Name of Register Memory Address Registers (MAR) Memory Buffer Register (MBR) Program Control Register (PER) Accumulated Register (AR) Instruction Register (IR) Input/Output Register (I/OR) Function Holds the address of the active memory location. Holds information on its way to and from memory. Holds the address of the next instruction to be executed. Holds accumulated results and data to be accumulated. Holds an instruction while it is being executed. Communicates with I/O devices.

A master/slave flip-flop actually contains two flip-flops - a master and a slave. One circuit serves as a master and the other as a slave. The master flip-flop is enabled on the positive edge of the clock pulse and the slave flip-flop is disabled by the inverter. The result is that the output changes during the l-to-0 transition of the clock signal. When the clock is high, the master is active. The output of the master is set or reset according to the state of the input. As the slave is inactive during this period, its output remains in the previous state. When the clock becomes low, the output of the slave flip-flop changes because it becomes active during low clock period. The final output of the master-slave flip-flop is the output of the slave flip-flop. So, the output of the master-slave flip-flop is available at the end of a clock pulse. The circuit diagram of a Master-Slave J-K flip-flop is shown in following figure.

Page 3 of 18

Figure: Master- Slave J-K flip flop 2. a.

x y z Borrow Difference H.S H.S

The Boolean expression for Difference (D) , Borrow (B) with x, y and z as inputs as follows: D = x ' y' z + x ' y z ' + x y' z' + xyz B = x ' y + x ' z + yz. b. i. INDIRECT ADDRESSING The limited address range problem of the direct addressing is solved by indirect addressing. In case of indirect addressing, the address field in the instruction refers to the address in memory, which in turn contains the address of the operand. The advantage of this technique is that for a word length of N, an address space of 2 is available. The disadvantage is that instruction execution requires two memory references to fetch the operand. Indirect addressing
N

Page 4 of 18

ii.

REGISTER ADDRESSING Like direct addressing, the address field refers to a register in the case of register addressing. The address field used to refer registers has 3 or 4 bits and this allows 8 or 16 general purpose registers to be referenced. The main advantages of register addressing are:

Only a small address field is needed in the instruction. No memory reference is required.

The main disadvantage of register addressing is that the address space is very limited. Since there are only limited numbers of registers in the CPU, when register addressing is used heavily, it is required to use the registers and the addressing technique efficiently. For example, the heavy usage of register addressing is justified only if the operand is brought into register for multiple operations. And if every operand is brought into a register from main memory for each operation, then a wasteful intermediate step is added. Register addressing

Page 5 of 18

c.

AND

3.

a.

IMPACT PRINTERS : These printers can produce a page, a line or a character at a time. Large computers use line printers that can generate hard copies at a rate of 3000 lines per minute. These printers are generally used for printing backup copies of large amounts of stored data. However, their print quality is poor. Dot-matrix printers fall in this category. The cheapest dot matrix printers use a matrix of pins and produce poor quality printouts. There are some dot-matrix printers, which use a 24-pin print-head and can produce near letterquality print-outs, which are almost as good as non-impact prints. Maintenance costs are generally low for these printers. NON-IMPACT PRINTERS These are the most widely used printers for personal computers. They can produce both text and graphics with good print quality. The most popular non-impact printers are laser printers and inkjet printers. Inkjet printers: They are also called bubble jet printers. They are the least expensive and most popular non-impact printers. Inkjet printers, like the dot-matrix printers, work by forming an image that is composed of tiny dots, but the dots are much smaller. It is difficult to distinguish these printouts from those of laser printers, which have fully formed characters. They also print in color, which makes them a popular choice for home users. Though inkjet printers are inexpensive and produce excellent output, they are slow. Laser printers: These work like photocopy machines. A laser beam generates electrical charges on a rotating print drum. These charges attract tones that are fused on to the surface of a paper by means of heating process. They are faster than inkjet printers. Although the initial cost is high, they cost less in the long-run because of lower operational costs.

b.

Subtraction using 2s complements The direct method of subtraction uses the barrow concept. In this method, we barrow a 1 from a higher Page 6 of 18

significant position when the minuend digit is smaller than the corresponding subtrahend digit. But when subtraction is implemented by means of digital components, we have a method that uses complements and addition. The subtraction of two positive numbers (M - N), both of base r, may be done as follows: Add the minuend M to the rs complement of the subtrahend N. Inspect the result obtained in step 1 for an end carry: a. b. (i) If an end carry occurs, discard it. If an end carry does not occur, take the rs complement of the number obtained in step 1, and place a negative sign in front. M = 1010100 N = 1000100 Performing M N: M= 1010100 + 2s complement of N = End carry Answer: 0010000 (ii) M = 1000100 N = 1010100 Performing M N: M = 1000100 + 2s complement of No carry N = 0101100 -------------------1110000 -------------------Answer: -0010000 = - (2s complement of 1110000) Subtraction with 1s complement The subtraction of M N, both positive numbers in base r, may be calculated as follows: 1. 2. Add the minuend M to the (r-1)s complement of the subtrahend N. Inspect the result obtained in step 1for an end carry. a. b. (i) If an end carry occurs, add 1 to the least significant digit (end -around carry.) If an end carry does not occur, take the (r-1)s complement of the number obtained in step 1 and place a negative sign in front. 0111100 -------------------1 | 0010000 --------------------

M = 1010100 N = 1000100

Page 7 of 18

Performing of M N: M = 1010100 + 1s complement of N = 0111011 -------------------End around carry 1 | 0001111 +1 -------------------0010000 -------------------Answer: 0010000 (ii) M = 1000100 N = 1010100 Performing M N: M = 1000100 + 1s complement of N = 0101011 -------------------No carry 1101111 -------------------Answer: -0010000 = - (1s complement of 1101111) c. Characteristics of RISC Architecture: i. Relatively few instructions

ii.

Mostly register-to-register operations.

Relatively few addressing modes (because of i).

iii. Memory access limited to load and store instructions. iv. All operations done within the registers of the CPU. v. Fixed-length, easily decoded instruction format, Aligned to word boundaries. Simplifies control logic. Fetch, decode, and execute phases for two to three instructions overlap: pipelining. Memory references may take more clock cycles.

vi. Single-cycle instruction execution,

vii. Hardwired rather than micro programmed control (which is faster). Other RISC Characteristics i. A large number of registers, a. b. ii. Useful for storing intermediate results and for optimizing operand references: much faster than memory references. Most frequent accessed operands are kept in registers.

Use of overlapped register windows to speed-up procedure call and return. Page 8 of 18

iii. iv. 4. a.

Efficient instruction pipeline. Compiler support for efficient translation of high-level language programs into machine language programs.

The performance of the disks is measured based on the following criteria:

Seek time is the time to reposition the head and it increases with the distance that the head must move. Seek times can range from 2 to 30 milliseconds. Average seek time is the average of all seek times and is normally one-third of the worst-case seek time. Rotational latency time is the time from when the head is over the correct track until the data rotates around and is under the head and can be read. When the rotation is 120 rotations per second, the rotation time is 8.35 milliseconds. Normally, the average rotational latency time is one-half of the rotation time. Access time is the time from when a read or write request is issued to when the data transfer begins. It is the sum of the seek time and latency time. Data-transfer rate is the rate at which data can be retrieved from the disk and sent to the controller. This will be measured as megabytes per second. Mean time to failure is the number of hours (on average) until a disk fails. Write Volatility Mechanism Electrically . Volatile Masks

b.

Characteristics of Different Types of ROMs Memory Type Random Access Memory (RAM) Read Only Memory (ROM) Programmable ROM (PROM) Erasable PROM (EPROM) Flash Memory Electrically Erasable PROM (EEPROM) Category Read-Write Memory. Read-Only Memory Erasing Data Electrically, byte-level Not possible

Read-Mostly Memory

UV light, chiplevel Electrically, block-level Electrically Electrically, byte-level

Non-volatile

Page 9 of 18

c.

4-bit bidirectional shift register with parallel load

A4

A3

A2

A1

Clear

CP

A register that can shift in both directions is called by directional shift register. The register which has both shift and parallel load capabilities is called a shift register with parallel load. It consists of four D flip-flops. The four multiplexers (MUX) are part of the register and are drawn here in block diagram form. The four multiplexers have two common selection variables, s1 and s0. Input 0 in each MUX is selected when s1 s0 = 00, input 1 is selected when s1 s0 = 01, and similarly for the other two inputs to the multiplexers. The s1 and s0 inputs control the mode of operation of the register as specified in the function table. Mode control S1 0 0 1 1 S0 0 1 0 1 Register operation No change Shift right Shift left Parallel load

When s1 s0 = 00, the present value of the register is applied to the D inputs of the flip-flops. This condition forms a path from the output of each flip-flop into the input of the same flip-flop. The next clock pulse transfers into each flip-flop the binary value it held previously, and no change of state occurs. When s1 s0 = 01, terminals 1 of the multiplexer inputs have a path to the D inputs of the flip-flops. This causes a shift-right operation, with the serial input transferred into flip-flop A4. When s1 s0 = 10, a shift-left operation results, with the other serial input going into flip-flop Al. Finally, when s1 s0 = 11, the binary information on the parallel input lines is transferred into the register simultaneously during the next clock pulse.

Section B
5. a. Characteristic Table for D Flip-Flop Input (Dn) 0 1 X Clock Input 1 1 0 Output (Qn+1) 0 1 Qn

Page 10 of 18

Characteristic Table for T Flip-Flop Input (Tn) 0 1 b. Clock Input 1 0 Output (Qn+1)

Qn
Qn

The subtraction of binary numbers can be done most conveniently by means of complements. The subtraction A-B can be done by taking the 2's complement of B and adding it to A. The 2's complement can be obtained by taking 1's complement and adding one to the least significant pair of bits. The one's complement can be implemented with inverters and a one can be added to the sum through the input carry. The addition and subtraction operations can be combined into one common circuit by including an exclusive-OR gate with each full-adder. For example, consider a 4-bit adder-subtractor circuit. B3 A3 B2 A2 B1 A1 B0 A0

C3

The mode input M controls the operation. When M = 0 the circuit is an adder and when M = 1 the circuit becomes a subtractor. Each exclusive-OR gate receives input from M and other inputs of B (B0, B1, B2, B3) When M = 0, we have B XOR 0 = B. The full-adders receive the value of B, the input carry is 0, and the circuit performs A plus B. When M = 1, we have B XOR 1 = B' and C0 = 1. The B inputs are all complemented and a 1 is added through the input carry. The circuit performs the operation A plus the 2's complement of B. 6. a. Each Octal digit corresponds to three binary digits and each Hexadecimal digit corresponds to four binary digits. The conversion from binary to octal is easily accomplished by partitioning the binary number into groups of three bits each starting from the low-order bit. The corresponding octal digit is then assigned to each group of bits and the string of digits so obtained gives the octal equivalent of the binary number. For example, the 16-bit binary number 1101100101100110 is converted to octal as follows; 1 | 101 | 100 | 101 | 100 | 110 1 5 4 5 4 6 (1101100101100110)2 = (154546)8 The conversion from binary to hexadecimal is achieved in the same way except that the bits are divided into groups of four starting from the low-order bit. The corresponding hexadecimal digit for each group of four bits is written. For example, the same 16-bit binary number 1101100101100110 is converted to hexadecimal as follows: 1101 | 1001 | 0110| 0110 D 9 6 6 Page 11 of 18 (1101100101100110)2 = (D966)16.

b.

According Demorgans law

(A'B+ B'A)' = (A + B' ) (B + A' ) = AB+ AA' + BB' + A'B' = AB+ 0 + 0 + A'B' = A'B' + AB.
7. a. There are two main types of sequential circuits. The classification depends on the timings of their signals. A synchronous sequential circuit is a system whose behavior can be known from the knowledge of its signals at discrete instants of time. The behavior of an asynchronous sequential circuit depends upon the order in which the input signals change and can be affected at any instant of time. The memory elements commonly used in asynchronous sequential circuits are time-delay devices. The memory capability of a time-delay device is due to the fact that it takes a finite time for the signal to propagate through the device. In gate-type asynchronous systems, the memory elements consist of logic gates whose propagation delays constitute the required memory. Thus, an asynchronous sequential circuit may be regarded as a combinational circuit with feedback. Because of the feedback among logic gates, an asynchronous sequential circuit may, at times, become unstable. The instability problem imposes many difficulties on the designer. Hence, they are not as commonly used as synchronous systems. A synchronous sequential logic system, by definition, must employ signals that affect the memory elements only at discrete instants of time. One way of archiving this goal is to use pulses of limited duration throughout the system so that one pulse amplitude represents logic-1 and pulse amplitude (or the absence of a pulse) represents logic-0. The difficulty with a system of pulses is that any two pulses arriving from separate independent sources to the inputs of the same gate will exhibit unpredictable delays, will separate the pulse slightly, and will result in unreliable operation. Practical synchronous sequential logic systems use fixed amplitudes such as voltage levels for the binary signals. Synchronization is achieved by a timing device called a master clock generator which generates a periodic train of clock pulses. The clock- pulses are distributed throughout the system in such a way that memory elements are affected only with the arrival of the synchronization pulse. In practice, the clock pulses are applied into AND gates together with the signals that specify the required change in memory elements. The AND gate outputs can transmit signals only at instants which coincide with the arrival of clock pulses. Synchronous sequential circuits that use clock pulses in the inputs of memory elements are called clocked sequential circuits. Clocked sequential circuits are the type encountered most frequently. They do not manifest instability problems and their timing is easily broken down into independent discrete steps, each of which is considered separately.

Page 12 of 18

b.

Logic diagram of 8-to-1 line multiplexer using four 2-to-1 multiplexers

The function table of the above 8-to-1 multiplexer is as follows: Enable E 1 0 0 Select S X 0 1 Output Y All 0s Select A Select B

Section C
8. If we want wish to design a clocked sequential circuit that goes through a sequence of repeated binary states 00, 01, 10, and 11 when an external input x is equal to 1. The state of the circuit remains unchanged when x = 0. This type of circuit is called a two-bit binary counter because the state sequence is identical to the count sequence of two binary digits. Input x is the control variable that specifies when the count should proceed. The binary counter needs two flip-flops because two bits are specified for each state. The state diagram for the circuit is shown below. The diagram is drawn

State diagram for binary counter. to show that the states of the circuit follow the binary count as long as x = 1. The state following 11 is 00 which causes the count to be repeated. If x = 0, the state of the circuit remains unchanged. This sequential circuit has no external outputs and therefore, only the input value is labeled in the diagram. The state of the flip-flops may be Page 13 of 18

considered as the outputs of the circuit. Assign the symbols A and B to the two flip-flops. The next state of A and B as a function of their present state and input x can be transferred from the state diagram into a state table. The first five columns of Table constitute the state table. The entries for this table are obtained directly from the state diagram. The excitation table of a sequential circuit is an extension of the state table. This extension consists of a list of flip-flop input excitations that will cause the required. State table

Present State A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1

Input x 0 1 0 1 0 1 0 1 A 0 0 0 1 1 1 1 0

Next State B 0 1 1 0 0 1 1 0 Flip-Flop Input Conditions JA 0 0 0 1 X X X X KA X X X X 0 0 0 1 JB 0 1 X X 0 1 X X KB X X 0 1 X X 0 1

Inputs of combinational circuit

Outputs of combinational circuit

state transitions. The flip-flop input conditions are a function of the type of flip-flop used. If I employ JK flipflops I need columns for the J and K inputs of each flip-flop. I denote the inputs of flip-flop A by JA and KA, and those of flip-flop B by JB and KB. The inputs are the variables A, B, and x, the outputs are the variables JA, KA, JB, and KB. The information from the excitation table is transferred into the maps, where the four simplified flip-flop input functions are derived: JA = Bx KA = Bx JB = x KB = x
B 1 A x x x x A x x x 1
x KA= Bx

B x

x JA = Bx

B 1 A 1
x JB= x

B x x A x x x x 1 1

x x

x KB= x

The logic diagram is drawn consists of two flip-flops and an AND gate. Note that inputs J and K determine the transition that will occur when a dock pulse (CP) arrives. If both J and K are equal to 0, a clock pulse will have no effect, that is, the state of the flip-flops will not change. Thus, when x = 0, the state of the flip-flops remains Page 14 of 18

unchanged even though clock pulses are continuously applied. The behavior of the circuit is first formulated in a state diagram. The number of flip-flops needed for the circuit is determined from the number of bits listed within the circles of the state diagram.
A B

J CP

Logic diagram of binary counter 9. i. The function has three variables A, B and C. In the first term A, two variables B and C are missing; therefore. A = A(B + B) = AB + AB ( B + B = 1) This is still missing one variable C A = AB (C + C) + AB (C + C) = ABC + ABC + ABC + ABC The second term BC is missing one variable: BC = BC (A + A) = ABC + ABC Combining all terms, we have: F = A + BC = ABC + ABC + ABC + ABC + ABC + ABC But ABC appears twice and according to Boolean law (x + x = x), it is possible to remove one of them. Rearranging the minterms in ascending order, we finally obtain: F = ABC + ABC + ABC + ABC + ABC = m1 + m4 + m5 + m6 + m7 It is sometimes convenient to express the Boolean function, when it is in sum of minterms, in the following short notation: F (A, B, C) = (1, 4, 5, 6, 7) The summation symbol stands for the ORing of terms; the numbers following it are the minterms of the function. The letters in parentheses following F form a list of the variables in the order taken when the minterm is converted to an AND term. ii. First convert the function into OR terms using the distributive law: F = xy + xz = (xy + x) (xy + z) F = (x + x)(y + x)(x + z)(y + z) F = (x + y)(x + z)(y + z) The function has three variables: x, y and z. Each OR term is missing one variable; therefore: x + y = x + y + zz = (x + y + z)(x + y + z) x + z = x + z + yy = (x + y + z)(x + y + z) y + z = y + z + xx = (x + y + z)(x + y + z) Page 15 of 18

Combining all the terms and removing those that appear more than once, we finally obtain: F = (x + y + z)(x + y + z)(x + y + z)(x + y + z) = M0M2M4M5 A convenient way to express this function is as follows: F (x, y, z) = (0, 2, 4, 5) The product symbol, , denotes the ANDing of maxterms; the numbers are the maxterms of the function. 10. Y = (A B) / (C + D X E). Instruction SUB Y,A,B MPY T,D,E ADD T,T,C DIV Y,Y,T Instruction MOVE Y,A SUB Y,B MOVE T,D MPY T,E ADD T,C DIV Y,T Instruction LOAD D MPY E ADD C STOR Y LOAD A SUB B DIV Y STOR Y 11. Comment YAB TDxE TT+C YY/T Comment YA YYB TD TTxE TT+C YY/T Comment AC D AC AC x E AC AC + C Y AC AC A AC AC B AC AC / Y Y AC

(a) Three-address instructions

(b) Two-address instructions

(c) One-address instructions Due to improvements in technology, small disks are produced in large numbers and it has become economically feasible to attach a large number of disks to a computer system, store large amount of information and improve the process of reading and writing data by the parallel operation of disks. To take advantage of this situation, different techniques, collectively called RAID (Redundant Array of Independent Disks) have been proposed to take into account the issue of performance and reliability. There is an agreement in the industry on a standardized scheme for multiple-disk database design, known as RAID. RAIDs are used for their improvement in reliability and data transfer rate. Since RAIDs involve multiple disks, it is possible to store extra information which is normally redundant. This redundant information can be used in the event of failure of one of the disks. With RAIDs it is possible to access all the data from multiple disks at one time. The transfer rate of data from multiple files can be improved by stripping data across multiple disks in which bits of a single byte are spilt across multiple disks. The concepts of RAID have been extended to other storage devices like arrays of tapes and to transfer data over wireless systems. The advantage here is that data is split over a number of tapes such that it is possible to reconstruct data which is lost due to failure of a single tape at a time. The RAID scheme consists of seven levels ranging from zero through six. Though these levels do not imply a hierarchical relationship, they designate different design architectures that share three common characteristics: i. ii. RAID is a set of physical disk drives viewed by the operating system as a single logical drive. Data are distributed across the physical drives of an array. Page 16 of 18

iii.

Redundant disk capacity is used to store parity information, which guarantees data recoverability in case of a disk failure.

The important contribution of the RAID proposal is to address effectively the need for redundancy. Although allowing multiple heads and actuators to operate simultaneously achieves higher I/O and transfer rates, the use of multiple devices increases the probability of failure. To compensate for this decreased reliability, RAID makes use of stored parity information that enables the recovery of data lost due to a disk failure. Diagrammatic representation of RAID scheme is shown in the figure. Seven levels of RAID scheme

Different RAID Levels RAID level 0 refers to disk arrays with striping at the level of blocks, but without any redundancy. RAID level 1 refers to disk mirroring with block striping. RAID level 2 known as memory-style Error-Correcting-Code (ECC) organization, employs parity bits. Each byte in a memory system may have a parity bit associated with it that records whether the numbers of bits in the byte that are set to 1 is even (parity = 0) or odd (parity = 1). If one of the bits in the byte gets damaged, the parity of the byte changes and thus will not match the stored parity. Similarly, if the stored parity bit gets damaged, it will not match the computed parity. Thus, all 1-bit errors will be detected by the memory system. RAID level 3, bit interleaved parity organization, improves on level 2 by exploiting the fact that disk controllers, unlike memory systems can detect whether a sector has been read correctly, so a single parity bit can be used for error correction as well as for detection. If one of the sectors gets damaged, the system knows exactly which sector it is and for each bit in the sector, the system can figure out whether it is a I or a Page 17 of 18

0 by computing the parity of the corresponding bits from sectors in the other disks. If the parity of the remaining bits is equal to the stored parity, the missing bit is 0 otherwise it is 1. RAID level 3 is as good as level 2, but is less expensive in the number of extra disks. RAID level 3 has two benefits over level 1. It needs only one parity disk for several regular disks, whereas level 1 needs one mirror disk for every disk and thus reduces the storage overhead. Since reads and writes of a byte are spread out over multiple disks, with N-way striping of data, the transfer rate for reading or writing a single block is N times faster than RAID level 1 organization using N-way striping. On the other hand, RAID level 3 supports a lower number of I/O operations per second, since every disk has to participate in every I/O request. RAID level 4, block-interleaved parity organization, uses block level striping like RAID 0 and in addition keeps a parity block on a separate disk for corresponding blocks from N other disks. A block read accesses only one disk, allowing other requests to be processed by the other disks. Thus, the data-transfer rate for each access is slower, but multiple read accesses can proceed in parallel, leading to a higher overall I/O rate. The transfer rates for large reads is high, since all the disks can be read in parallel; large writes also have high transfer rates, since the data and parity can be written in parallel. Small independent writes, on the other hand cannot be performed in parallel. A write of a block has to access the disk on which the block is stored as well as the parity disk, since the parity block has to be updated. And both the old value of the parity block and the old value of the block being written have to be read for the new parity to be computed. Thus, a single write requires four disk accesses: two to read the two old blocks and two to write the two blocks. RAID level 5, block-interleaved distributed parity, improves on level 4 by partitioning data and parity among all N+l disks, instead of storing data in N disks and parity on one disk. In level 5, all disks can participate in satisfying read requests, unlike RAID level 4, where the parity disk cannot participate, so level 5 increases the total number of requests that can be met in a given amount of time. For each set of N logical blocks, one of the disks stores the parity and the other N disks store the blocks. RAID level 6, the P + Q redundancy scheme, is much like RAID level 5 but stores extra redundant information to guard against multiple disk failures. Instead of using parity, level 6 uses error-correcting codes such as the Reed-Solomon codes. 2 bits of redundant data are stored for every 4 bits of data unlike 1 parity bit in level 5 and the system can tolerate two disk failures. Characteristics of different RAID Levels Raid Level 0 Description a. b. c. it does not include redundancy. The data is stripped across the available disks. A set of consecutive strips that maps exactly one strip to each disk in the array is called Stripe. a. The data is duplicated. b. Every disk has a mirror disk. c. Read request is serviced by either of the two disks while a write request must be done on both disks but can be done in parallel. Parallel array of disks with error detection. All disks participate in every I/O request; It has bit interleaved parity. Block interleaved parity: It uses large strips with a parity strip. The parity strips are distributed across all disks. Block interleaved dual distributed parity.

2 3 4 5 6

Page 18 of 18