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E3

Nguyen-viet Tuan

Nguyen-viet Tuan

Slide 1

E2 Framing
The E2 frame is created by bit multiplexing four E1 bit streams. Of course, its a bit more complex than that because framing must be added along with a technique for adapting to varying clocks. The E2 rate is 8.448 Mbps with a tolerance of +/- 30 ppm. The basic E2 frame is 848 bits, with a 10-bit frame alignment signal of {1, 1, 1, 1, 0, 1, 0, 0, 0, 0} at the beginning. The 848-bit frame is broken into four 212 bit sub frames.

Nguyen-viet Tuan

Slide 2

E3 Framing / Deframing according ITU-T G.703 / G.751

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Slide 3

General

Standard : ITU-T G.703 and G.751 Data rate : 34 368 Kbps Tolerance : +/- 20 ppm The E3 transmission scheme according G.751 consists of frames with a length of 1536 bits. A frame consists of four sets, which are 384 bits long. 22375 frames are transmitted per second.

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Slide 4

E3 Framing 4 sets

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Slide 5

E3 Framing OAM Signals

Frame synchronization is achieved, if three consecutive correct frame alignment signals are detected. Frame synchronization is lost (LOF), if four consecutive defective frame alignment signals are detected. The Frame Alignment Signal (FAS) is located in the first set of a frame. The Remote Alarm Indication (RAI) Bit and the National (NA) Bit are following the FAS. The remainder of the first set is filled with the four E2 data streams. These data streams are mapped in a bit interleaved manner, starting with the first E2 data stream. There is no frame alignment between the multiplex formats E3 and E2.

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Slide 6

E3 Framing OAM Signals (2)

Only positive justification is used. The first four bits in the sets numbered #2 to #4 are the justification control bits (CJN). The justification payload or stuffing bits (JJ) are located in the forth set in the bits numbered #5 to #8. The justification control bits specifies if the corresponding justification payload bits are carrying valid data bits or not.

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Slide 7

E3 ITU-T G.832

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Slide 8

General

Supports both PLCP and direct cell mapping. Direct Mapping: The E3 frame structure when direct mapping is employed. The 531 octet payload consists of 59 columns and 9 rows. The 53 byte ATM cell wraps around the 59 bytes of the E3 frame. There is no relationship between the start of a direct mapping frame and the start of the ATM cell.

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Slide 9

G.832 E3 Framing
59 columns
FA1 EM TR MA <---------------------------------------------------------------------------------> 530 Payload bytes 48 bytes of Payload FA2

9 rows

NR GC

The 53 byte ATM cell is represented as follows: Header <--------------------------------------------------------------------------------------------> 53 bytes E3 Frame Structure Direct Mapping

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Slide 10

G.832 E3 Framing (2)

FA1 FA2 EM TR

Frame Alignment 1. Frame Alignment 2. Error Monitor, BIP-8. Trail Trace.

MA Maintenance and Adaptation. NR Network Operator. GC General Purpose Communications Channel.

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Slide 11

PLCP Cell Mapping

The E3 PLCP frame provides the transmission of 9 ATM cells every 125 msec. The net transmission rate is thus 3.456 Mbytes/sec. The PLCP frame is octet aligned to the 16 overhead (OH) bits in the ITU-T G.751 E1 frame. There is no relationship between the start of the PLCP frame and the start of the E3 frame. A trailer is inserted at the end of each PLCP frame.

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Slide 12

PLCP Cell Mapping (2)

A1 A1 A1 A1 A1 A1 A1 A1 A1 1

A2 A2 A2 A2 A2 A2 A2 A2 A2 1

P8 P7 P6 P5 P4 P3 P2 P1 P0 1

Z3 Z2 Z1 F1 B1 G1 M1 M2 C1 1

ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell ATM Cell 53 bytes

Trailer 17-21 bytes

<---> <---> <---> <---> <--------------------------> <------------------------> E3 Frame Structure PLCP Cell Mapping

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Slide 13

PLCP Cell Mapping (3)


A-bits Framing pattern octet (byte). P-bits Path overhead (POH) identifier. C1 Pad bit counter. M-bits SIP layer 1 management information. G1 PLCP path status. B1 Bit-interleaved parity 8 (BIP-8). F1 PLCP path user channel. Z-bits For future use.
Nguyen-viet Tuan Slide 14

Thank You !

Nguyen-viet Tuan

Slide 15

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