EE5518 VLSI Digital Circuit Design

(Part I CMOS Inverter)

XU Yong Ping
Dept of Electrical and Computer Engineering
Email: elexuyp@nus.edu.sg

EE5518 VLSI Digital Circuit Design - XU YP

Lecture schedule (Part I)

Week WK1 (12 Aug) WK2 (19 Aug) WK3 (26 Aug) WK4 (2 Sept) WK5 (9 Sept) WK6 (16 Sept) Lectures Introduction CMOS inverter Wire and parasitics Pass transistor logic Combinational logic circuits Sequential logic circuits Assignment-3 out (Due 30 Sept) Assignment-1 out (Due 2 Sept) Project out (Due on 7 Oct, Week 8) Assignment-2 out (Due 16 Sept) Assignment & Project

*Time: 6 9pm, Thursday, Venue: E1-06-05 * Solutions will be released after the corresponding due date of the assignments * Any assignment submitted after the solution is released will not be graded.

EE5518 VLSI Digital Circuit Design - XU YP

CMOS inverters
1. MOS transistor characteristics
IV I-V characteristics Body effect Short channel effect Sub-threshold slope Static and dynamic analysis

2. CMOS inverter 3. Power consumption

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1. MOS transistor characteristics

MOS transistor
Polysilicon Gate Gate oxide Drain n+
L

Source n+ p substrate Bulk (Body)

Field-Oxide (SiO2) p+ stopper

EE5518 VLSI Digital Circuit Design - XU YP

Transistor in Linear Region

For long-channel devices (L > 0.25 micron) When VDS VGS VT
I D = kn W L
2 VDS (VGS VT )VDS 2

where kn = nCox is the process transconductance parameter (n is the carrier mobility (m2/Vsec))

kn = kn

W is the gain factor of the device L

For small VDS, omitting the quadratic term of VDS,

RDS =
EE5518 VLSI Digital Circuit Design - XU YP

VDS W = [k n (VGS VT )]1 ID L

Transistor in Saturation Region

For long channel devices When VDS > VGS VT

k W ID = n (VGS VT ) 2 2 L

since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at VGS VT However, the effective length of the conductive channel is modulated by the applied VDS, so ID = ID (1 + VDS) where is the channel-length modulation factor (varies with the inverse of the channel length)
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Current-Voltage Plot
6 x 10
-4

nMOS transistor
VGS= 2.5 V

Linear
4

Saturation
VGS= 2.0 V

ID (A)

VDS = VGS - VT
VGS= 1.5 VGS 1 5 V

Quadratic Relationship

VGS= 1.0 V
0 0.5 1 VDS (V) 1.5 2 2.5

EE5518 VLSI Digital Circuit Design - XU YP

Threshold Voltage and Back-Gate

VT = VT 0 + ( 2 F + VSB 2 F )
where VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. VSB is the source-bulk voltage F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal ( / p q
voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon)

= (2qsiNA)/Cox is the body-effect coefficient (impact of changes in VSB)

(si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate oxide capacitance with ox=3.5x10-11F/m)
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The Body Effect

nMOS transistor
0.9 0.85 0.8 0.75 0.7

V (V)

0.65 0.6 0.55 0.5 0.45 0.4 -2.5

-2

-1.5

-1

-0.5

BS

(V)

EE5518 VLSI Digital Circuit Design - XU YP

Short Channel Effects

10 5

Velocity saturation the velocity of the carriers y saturates due to scattering (collisions suffered by the carriers)
Electron velocity:

n =
0 0

n 1 + c

( c )

c 1.5 (V/m)

n = sat =

n c
2

( = c )
( >> c )
10

sat = n c

EE5518 VLSI Digital Circuit Design - XU YP

Short Channel Effects (cont)

ID
VGS = VDD

Long-channel d i L h l device

VDSAT < VGS VT so the device enters saturation before VDS reaches VGS VT and operates more often in saturation

IDSAT

Short-channel

VDSAT = L c =
VDSAT VGS-VT

L sat

VDS

or sat = n

VDSAT L
11

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Drain current
Drain current in linear region:

ID =

1+

1 W nCox VDS L L

V2 (VGS VT )VDS DS 2

W = (VDS ) nCox L

V2 (VGS VT )VDS DS 2

1 long channel 1 (VDS ) = = 1 / 2 VDS L = c ( short channel ) V L 1 + DS << 1 VDS L > c ( short channel ) c
Measured the degree of velocity saturation
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IDSAT
Drain current at VDS = VDSAT :

I DSAT

V2 W nCox (VGS VT )VDSAT DSAT long channel L 2 W V = (VDSAT ) n Cox VGS VT DSAT short channel L 2 V sat CoxW VGS VT DSAT short channel 2
where sat V = n DSAT L approximation for c

Under velocity saturation

VDSAT = C L
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ID-VGS Plot
Fixed VDS is set to ensure the transistor in saturation
6 5 4
I D (A)

x 10

-4

x 10 2.5

-4

quadratic

linear
1.5
ID (A)

3 2 1 0 0

0.5

0.5

1
VGS(V)

1.5

2.5

0 0

quadratic
0.5 1
VGS(V)

1.5

2.5

Long Channel

Short Channel

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ID-VDS Plot
Due to velocity saturation
6 5 4 ID (A) 3 2 1 0 0 x 10
-4

VGS= 2.5 V Saturation Linear VGS= 2.0 V

x 10 2.5

-4

VGS= 2.5 V
2

VGS= 2.0 V
ID (A) 1.5

VDS = VGS - VT
VGS= 1.5 V

VGS= 1.5 V VGS= 1.0 V

0.5

VGS= 1.0 V
0.5 1 VDS(V) 1.5 2 2.5 0 0 0.5 1 VDS(V) 1.5

2.5

Long Channel

Short Channel

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Sub-Threshold Conductance
10-2

Linear region

Quadratic region

Subthreshold exponential region

10-12

Transistor is not completely off when VGS < VT Transition from ON to OFF is gradual (decays exponentially) This causes leakage current in digital circuits and hence the static power consumption In sub-threshold region,
V qVGS DS I D = I S e nkT 1 e kT q (1 VDS )

VT
0 0.5 1 1.5 2 2.5

( n > 1)

n is typically 1.5
16

EE5518 VLSI Digital Circuit Design - XU YP

VGS (V)

Sub-threshold slope
The sub-threshold slope,
10-2

I D I S e nkT S=

qVGS

VGS ln I D

Linear region Li i Quadratic region

kT = n ln(10) q 60 mV decade 90 mV decade

( n = 1) ( n = 1.5)
10-12

Subthreshold exponential region g VT

0 0.5 1 1.5 2 2.5

What does this imply in the digital IC design?

VGS (V)
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2. CMOS Inverter
N Well

VDD
PMOS

VDD 2

PMOS In Out
In

Contacts

Out Metal 1

NMOS

Polysilicon

NMOS GND

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Inverter Chain
Share power and ground

Abut cells

VDD
Connect in Metal

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Inverter Static Analysis

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20

10

Inverter switching model

| VGS |

Gate Drain (of carriers)

Source (of carriers)

Open (off) (Gate = 0)

Closed (on) (Gate = 1)

Ron

| VGS | < | VT |

| VGS | > | VT |

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First-order DC Analysis
VDD VDD VOL = 0 VOH = VDD VM = f(Rn, Rp) (VM Switching threshold) Vout = 0 Rn

Rp Vout = 1

Vin = 0
EE5518 VLSI Digital Circuit Design - XU YP

Vin = V DD
22

11

CMOS Properties
Full rail-to-rail swing high noise margins
Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless

Always a path to Vdd or GND in steady state low output impedance (output resistance in k range) large fan-out Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay is a function of load capacitance and resistance of transistors

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NMOS I-V Plot

2.5 2 1.5 1 0.5 0 0 0.5 1
X 10-4

VGS = 2.5V VGS = 2.0V VGS = 1.5V VGS = 1.0V

VDS (V)

1.5

2.5

NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

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12

PMOS I-V Plot

VDS (V)
-2 -1 0 0

VGS = -1.0V VGS = -1.5V VGS = -2.0V

-0.2 -0 2 -0.4 -0.6 -0.8

VGS = -2.5V

-1 X 10-4

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V

All polarities of all voltages and currents are reversed

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Transforming PMOS I-V Lines

Make a common coordinate set, IDn vs. Vout with Vin as a parameter
IDn

IDSp = -IDSn VGSn = Vin; VGSp = Vin - VDD VDSn = Vout; VDSp = Vout - VDD

Vout
Vin = 0 Vin = 1.5 Vin = 0 Vin = 1.5

VGSp = -1 VGSp = -2.5

Mirror around x-axis Vin = VDD + VGSp IDn = -IDp

Horiz. shift over VDD Vout = VDD + VDSp

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CMOS Inverter Load Lines

2.5
Vin = 0V
X 10-4

PMOS

NMOS Vin = 2.5V

2
Vin = 0.5V 1.5 Vin = 1.0V 1 Vin = 2.0V

Vin = 1.5V

Vin = 1.5V Vin = 2.0V

Vin = 2V 0.5

Vin = 1.5V

Vin = 1V

Vin = 0.5V
Vin = 1 0V 1.0V Vin = 0.5V

0 0 0.5 1 1.5 Vout (V) 2 2.5

Vin = 2.5V

Vin = 0V

EE5518 VLSI Digital Circuit Design - XU YP

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

27

CMOS Inverter Voltage Transfer Characteristic

Vout (V) VDD
2.5 2 1.5 1 0.5 05 0 0 0.5 1 1.5 2 2.5
NMOS res PMOS sat NMOS res PMOS off NMOS off PMOS res NMOS sat PMOS res

VTC
NMOS sat PMOS sat

Vout Vin CL

Vin (V)
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14

Transistor Sizing
When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to
maximize the noise margins and obtain symmetrical characteristics

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Switch Threshold
VM where Vin = Vout (both PMOS and NMOS always in saturation since VDS = VGS > VGS VT) Equating the drain current,

k nVDSATn (VM VTn VDSATn 2) = k pVDSATp (VM + VDD + VTp + VDSATp 2)

Switching threshold:

VM =

(VTn + VDSATn 2) + r (VDD + VTp + VDSATp 2 1+ r k pVDSATp k nVDSATn

where r =

- Switching threshold is set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors
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15

Switch Threshold (contd)

Choice of PMOS and NMOS transistor size for VM,
' (W L ) k nVDSATn (VM VTn VDSATn 2) (W L ) = k ' V p DSATp (VDD VM + VTp + VDSATp 2)
p n

For VDD >> VT+VDSAT/2,

VM =

r VDD 1+ r

For VM = VDD/2 (to have comparable high and low noise margins), r1

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Simulated Inverter Threshold

1.5 1.4 1.3 13 1.2 1.1 1 0.9 0.8 0.1
~3.4

(W/L)p/(W/L)n

10

Note: x-axis is logarithm scale. VDD=2.5V

EE5518 VLSI Digital Circuit Design - XU YP

VM is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives VMs of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves VM towards VDD Increasing the width of the NMOS moves VM toward GND
32

16

VIH and VIL (Piece-wise VTC)

A piece-wise linear approximation of VTC
3
VOH = VDD

VIH and VIL are the input voltages where voltage gain is -1 Noise margins,

dVout = 1 dVin
VM

N MH = VDD VIH N ML = VIL 0

Linear approximation of the gain in transition region,
g= VDD V VIH VIL = DD VIH VIL g VDD g

VOL = GND 0

N MH + N ML = VDD (VIH VIL ) = VDD

VIL

Vin VIH

High g is desirable for maximum noise margin

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Gain of the Inverter

Vin
0 0 2 -2 -4 -6 -8 -10 -12 -14 14 -16 -18 0.5 1 1.5 2

g= =

dVout dVin V

in =VM

knVDSATn + k pVDSATp 1 I D (VM ) n p 1+ r (VM VTn VDSATn )(n p ) 2

The gain is mostly determined by the channel length modulation

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17

CMOS Inverter VTC from Simulation

2.5 2

0.25um, (W/L)p/(W/L)n = 3.4 (W/L)n = 1.5 (min size) VDD = 2 5V 2.5V Calculated: VM 1.25V, g = -27.5 VIL = 1.2V, VIH = 1.3V NML = NMH = 1.2 Simulated: VIL = 1.03V, VIH = 1.45V NML = 1.03V, NMH = 1.05V)

Vout (V)

1.5 1

0.5 0 0 0.5 1 1.5 2 2.5

Vin (V)
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Impact of the Process Variations

2.5 2
Fast PMOS Slow NMOS

Vout (V)

1.5 1 0.5 0 0 0.5 1 1.5 Vin (V)

Slow PMOS Fast NMOS

Nominal

r=

k pVDSATp k nVDSATn

2.5

The shift in the switching threshold is mostly caused by process variation

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18

Example 2.1
Design an inverter with switching threshold at 1.5V. 0.25um, (W/L)n = 1.5 (min size), VDD = 2.5V Determine (W/L)p
' k nVDSATn (VM VTn VDSATn 2) W W = ' L p L n k pVDSATp (VDD VM + VTp + VDSATp 2)

= 1.5 27

115 10 6 0.63 (1.5 0.43 0.315) (30 10 6 ) (1) (2.5 1.5 0.4 0.5)

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Inverter Dynamic Analysis

EE5518 VLSI Digital Circuit Design - XU YP

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19

Propagation delay
Propagation delay caused by charge and discharge of load capacitance VDD V
DD

Rp Vout CL Rn Vout CL

Vin = 0
EE5518 VLSI Digital Circuit Design - XU YP

Vin = V DD
39

Inverter Propagation Delay - Approach 1

Vin VOH

VOL Vout VOH V50%

t
tPHL tPLH

t pHL = t pLH =

C L VHL C L (VOH V50% ) C L (VDD VDD 2) = I av , HL I av , HL I av , HL C L VLH C LV50% VOL C L (VDD 2 0 ) = I av , LH I av , LH I av , LH

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20

Propagation delay
I av , HL = VOH 2 VDD 1 V50%
VDD 2 V50%

VOH

(Vout )dv

VDD

(VDS )dv

1 V [ I D (VDD ) + I D ( DD )] 2 2
Use the appropriate ID expression that is corresponding to the correct operation region
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Inverter Propagation Delay - Approach 2

Based on the switching model and consider the transistor (on) as a resistive path. VDD Vout = VDD -> VDD/2 CL

Vin = V DD Rn

t pHL = (ln 2) ReqnC L 0.69 ReqnC L t pLH = (l 2) Reqp C L 0.69 Reqp C L (ln tp = 1 (t pHL + t pLH ) = 0.69(Reqn + Reqp )CL 2

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21

Equivalent ON resistance
ID R(VDD/2) ( ) VGS=VDD R(VDD) VDD/2 VDD VDS

Req =

2 VDD

VDD 2

VDD

v 3V 7 dv DD (1 VDD ) I Dsat (1 + v ) 4 I Dsat 9

Or using the two endpoints:

3VDD 1 VDD VDD 2 5 Req = (1 VDD ) I (1 + V ) + I (1 + V 2) 4 I 2 Dsat 6 DD Dsat DD Dsat

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Example 2.2
Process: 0.25m, VDD=2.5V, W/Ln = 1.5, W/Lp = 4.5 CL=6fF, Unified device U ifi d d i model ( d l (see appendix) di ) Calculate the propagation delay. Vout (V)
3 2.5 2 1.5 1 0.5 0

Vin
tpHL
39.9ps 31.7ps

tpLH

I DSATn = k '

W (VGS VT )VDSAT V L 2 1.91 104 A

2 DSAT

-0.5 0 0.5 1 1.5 2

t (sec)

2.5

Reqn

3VDD 7 (1 VDD ) 8.67k 4 I Dsat 9

t pHL = 0.69 ReqnCL = 35.9 ps t pLH = 0.69 ReqpCL = 28.9 ps t p = 0.69(Reqn + Reqp )CL = 32.4 ps
44

Similarly,

I DSATp = 2.16 104 A, Reqp 6.99k

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Design for Speed

Reduce CL
internal diffusion capacitance of the gate itself
keep the drain diffusion as small as p p possible

interconnect capacitance fanout

Increase W/L ratio of the transistor

the most powerful and effective performance optimization tool in the hands of the designer watch out for self-loading! when the intrinsic capacitance dominates the extrinsic load

Increase VDD

can trade-off energy for performance increasing VDD above a certain level yields only very minimal improvements reliability concerns enforce a firm upper bound on VDD
45

EE5518 VLSI Digital Circuit Design - XU YP

NMOS/PMOS Ratio
For equal tpHL and tpLH, Reqn = Reqp
r=
=

Is tp also minimized?

Rp Rn

Resistance ration of identical sized PMOS and NMOS transistors

ration of the sizes of PMOS and NMOS transistors
C L ,n = C R CL, p = C
(Ignoring the wire parasitic capacitance)

(W L )p (W L )n
Reqp =

Reqn = R r

CL = (1 + )C

0.69 0.69 RC r r [ RC (1 + ) + RC (1 + )] = (1 + + + r ) tp = 2 2 t p r = 0 opt = r Reqp = Reqn = r Reqn Smaller PMOS is required for optimum delay, but at the expense of symmetry delays (tpHL and tpHL)
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23

Example 2.3
For the given devices in 0.25m CMOS process, find the values that give (1) equal tpHL and tpLH, and (2) minimum propagation delay. VDD is 2.5V.
For equal tpHL and tpLH,

Reqp = Reqn

=1

= r = 31 13 2.38
For minimum tp,

= r = 31 13 1.54
From simulation, symmetrical response occurs at = 2.4, while optimal delay performance is at =1.9
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Delay vs. VDD

Channel length modulation is ignored

5.5 5 4.5 4

t (n normalized)

3.5 3 2.5 2 1.5 1 0.8

Large over drive: VDD >> Vtn + VDASTn/2

1.2

1.4

1.6

1.8

2.2

2.4

V
EE5518 VLSI Digital Circuit Design - XU YP

DD

(V)
48

24

Delay vs. Device Scaling

Before scaling,

t p = 0.69 Req (Cint + Cext ) = 0.69 ReqCint (1 + Cext Cint )

After transistor size is scaled by S (S>1), Req = Rref S , Cint = SCiref

t p = 0.69

Rref

C ( SCiref )1 + ext SC S iref

t p0

C = 0.69( Rref Ciref )1 + ext = t p 0 (1 + Cext Cint ) SC iref = 0.69( Rreff Cireff ) Intrinsic (no external loading) delay

Intrinsic delay is independent of scaling and purely determined by technology; If S is infinite or S>>Cext/Ciref, the effect of extrinsic load on the delay is eliminated and the delay is reduced to the intrinsic one, but at the expense of silicon area
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Example 2.4
Process: 0.25m, VDD=2.5V, W/Ln = 1.5, W/Lp = 4.5, Cext=3.15fF, Cint=3fF, What is the percentage delay reduction when S=5, 10 and infinite?
-11

Calculation:

3.8 3.6 3.4 3.2 t (sec) 3 2.8 2.6 2.4 2.2 2

x 10

t p ,s

(1 + Cext SCiref ) ( 100) = 1 100 (1 + Cext Ciref ) tp 41% ( S = 5) 46% ( S = 100 51% ( S = )

From simulation under a fixed fan-out

t p 0 ( S = ) = 19.3 ps 49%
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8 S

10

12

14

50

25

Inverter Chain
In Out CL

If CL is given: - How many stages are needed to minimize the delay? - How to size the inverters?

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Inverter with Load

CP = 2Cunit 2W W
Delay

Cint

CL
Load

CN = Cunit

C t p = 0.69 Req (Cint + Cext ) = 0.69 ReqCint + 0.69 ReqC L = 0.69 ReqCint 1 + ext C int
Internal delay
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Due to external load

26

Inverter delay with the load

f = CL Effective fanout C gin Cint Self loading factor C gin

Cgin

Cint

CL

==

is independent of gate size and only a function of technology

t p = 0 . 69 RC int (1 + C L /C int ) = 0 . 69 C L C gin = 0 . 69 R unit C unit 1 + C int C gin

R unit C unit W (1 + C L /C int ) W

= t p0 1 + f
t p0 = 0 . 69 R unit C unit

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Delay of Inverter Chain

In 1 2 N Out CL

tp = tp1 + tp2 + + tpN

C t pjj ~ RunitCunit 1 + gin , j +1 , i i C gin , j

C gin , j +1 , t p = t p , j = t p 0 1 + C j =1 i =1 gin , j
N N
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f =

C gin , j +1 Cgin , j
C gin , N +1 = C L
54

27

Optimal Sizing for Given N

Delay equation has N - 1 unknowns, Cgin,2 Cgin,N Minimize the delay, find N - 1 partial derivatives and let them y, p equal to zero Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 Size of each stage is the geometric mean of two neighbors
C gin , j = C gin , j 1C gin , j +1

- each stage has the same effective fan-out (f = Cgin,j+1/Cgin,j) - each stage has the same delay

t p = Nt p 0 (1 + f / )

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Optimum Delay and Number of Stages

Since each inverter has the same effective fan-out f, for N stage:

= =

C g , 2 C g ,3 C g , N 1 C L ..... C g ,1 C g , 2 C g , N 2 C g , N CL =F C g ,1
Overall effective fan-out

Effective fan-out of each stage: Minimum path delay:

f =NF

56

NF t p = Nt p 0 1 +
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Example 2.5
A 3-stage inverter chain needs to drive a CL of 8 times of its input gate capacitance, C1 what is the required fan-out for minimum delay?

In C1

Out CL= 8 C1

f =N F =3

8C1 =2 C1

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Optimum Number of Stages

For a given load, CL and input capacitance Cin, find optimal sizing f

f ln F f + 1 t p = Nt p 0 + 1 = t p 0 ln f

t p f

= 0 ln f = 1 + f f = e1+
N= ln F ln F = ln f 1 + f
N = ln F

For = 0 (ignore internal delay),

f = e,
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Numerical solution with non-zero

5 4.5 4 3.5 3 2.5 0 0.5 1 1.5 2 2.5 3

7 6 5 4 3 2 1 0 1 1.5 2 2.5 3 3.5 4 4.5 5

f Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). Common practice to use f = 4 Too many stages has a substantial negative impact on delay
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Buffer Design Example

N
1 6 64

f 64 8

tp 65 18

1 2

64

16

64

15

2.8

22.6

64

2.8

15.3

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30

Impact of Buffer Staging for Large CL

topt/tpo versus CL
F ( = 1) 10 100 1,000 10,000 Unbuffered 11 101 1001 10,001 Two Stage Chain 8.3 22 65 202 Opt. Inverter Chain 8.3 16.5 24.8 33.1

Impressive speed up for large CL!

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3. Power Consumption
Power consumption is a major design specification of digital IC Low power consumption will save battery, long operation time for portable systems reduce the heat dissipation of the system reduce operation cost simplify the cooling system design

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Power Consumption Trend

100000 10000 Power (Watts) 1000 100 10 18KW 5KW 1.5KW 500W Pentium proc

286 486 8086 386 8085 8080 8008 1 4004

0.1 1971 1974 1978 1985 1992 Year 2000 2004 2008

Power delivery and dissipation will be prohibitive

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Power density of the Processors

10000 Power Density (W/ /cm2) 1000

Rocket Nozzle Nuclear Reactor

8086 Hot 4004 8008 8085 386 286 8080 1980

100

10

Plate
486 1990 Year

P6 Pentium proc

1970

2000

2010

Power density too high to keep junctions at low temp

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CMOS Inverter Power Dissipation

Dynamic power consumption
Charging and discharging the capacitances

Short circuit currents

Short circuit path between power supply rails during switching

Leakage
Leaking diodes and transistors

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Dynamic Power Dissipation

Vdd

Vin CL
2 Energy / transition = CLVDD

Vout

( = Q VDD )

2 Pdyn = Energy / transition f = CLVDD f 01

Not a direct function of transistor sizes! Need to reduce CL, VDD and frequency to reduce the dynamic power consumption Data or activity dependent - a function of switching activity
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Example 2.6
Consider a 0.25 m chip with 2 million gates, an average load cap of 15fF/gate (fan-out of 4), 2.5V supply and 500MHz clock. Compute the dynamic Power consumption per gate, as well as for the whole chip (assuming each transitions per clock cycle) cycle).
Single gate:
2 P = VDD CL f

= ( 2.5)2 15 1015 500 106 46.8W

The whole chip:
2 Ptotal = VDD CL f

= ( 2.5) 2 15 1015 500 106 2 106 93.6W

What about: - Pentium 4: ~42million transistors! 1.5GHz; - 8-core processor: ~2.3billion transistors! 2.66GHz
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Lower the Dynamic Power

Capacitance (CL):
- Function of fan-out - wire length - transistor sizes

Supply Voltage (VDD):

- Decreased with process p generations

2 2 Pdyn = CLVDD f 01 = CLVDD Psw f clk

Activity factor (Psw):

- How often, on average, the gates switch?

Clock frequency (f ):
- Is increasing

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Short Circuit Power Consumption

VDD
Input slope
VDD

ts

Vin

Isc

Vout CL
tsc

Esc = VDD I sc (t )dt , Psc = VDD f I sc (t )dt

0 0

tsc

t sc

I t 2 Esc = 2VDD peak sc = VDD I peak tsc , Psc = VDD I peak tsc f = CscVDD f 2 VDD 2VT VDD V 2VT V 2VT tr ( f ) Input slope ts DD = tsc = DD tsc ts VDD VDD 0.8
PSC is reduced when VDD is lowered. At VDD < 2VT, PSC is completely eliminated.
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Impact of CL on Psc
- VDSp is ~ zero and PMOS is OFF most of the time - VDSp is ~ VDD PMOS is ON most of the time

Isc 0 Vin Vout CL Vin

Isc Imax Vout CL

Large capacitive load: - Output fall time significantly larger than input rise time.

Small capacitive load: - Output fall time substantially smaller than the input rise time.

Can the PSC be minimized by making output tr/f > input tr/f?
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Isc as a Function of CL
- Th short circuit current, Isc i The h t i it t is large for small load capacitance - Practical rule: - Short circuit power dissipation can be minimized by matching the rise/fall times of the input and output signals (slope engineering). Input slope = 500ps
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Psc as a Function of Rise/Fall Times

Normalized with refer to zero input rise-time dissipation
8
W/Lp = 1.125 m/0.25 m 7 W/Ln = 0.375 m/0.25 m CL = 30 fF 6

5 4 3 2 1 0 0

VDD= 3.3 V

VDD = 2.5 V VDD = 1 5V 1.5V

2 4

Short circuit current is reduced when VDD is lowered; For VDD<2VT, PSC is completely eliminated as both PMOS and NMOS will not be turned on simultaneously; For large CL, dynamic power dissipation dominates; For small CL, short circuit power dissipation dominates.

Large CL

Small CL

tsin/tsout
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Static (leakage) Power Consumption

VDD VDD

Vout = VDD Drain junction (PN) leakage Sub-threshold current

Leakage in CMOS includes drain/source to substrate/well junction leakage current and subthreshold current; The Pstat is Pstatic = I statVDD = ( I junc + I sub )VDD
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Sub-threshold Leakage Current

~104 times

Sub-threshold leakage becomes large for low VT as the subthreshold slope is fixed ~104 times increase in leakage current when VT changes from 0.4 to 0.1V (sub-threshold slope: ~75mV/decade)
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TSMC Processes Leakage and VT

CL018 G Vdd Tox (effective) Lgate IDSat (n/p) (A/m) Ioff (leakage) (pA/m) VTn FET Perf. (GHz) 1.8 18V 42 0.16 m 600/260 20 0.42 0 42 V 30 CL018 LP 1.8 18V 42 0.16 m 500/180 1.60 0.63 0 63 V 22 CL018 ULP 1.8 18V 42 0.18 m 320/130 0.15 0.73 0 73 V 14 CL018 HS 2V 42 0.13 m 780/360 300 0.40 0 40 V 43 CL015 HS 1.5 15V 29 0.11 m 860/370 1,800 0.29 0 29 V 52 CL013 HS 1.2 12V 24 0.08 m 920/400 13,000 0.25 0 25 V 80

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Power dissipation - Summary

Ptotal = Pdyn + Psc + Pstat
2 = C LVDD f 01 + I peakVDD t s f 01 + I leakVDD

Power reduction:
VDD Pdyn Psc Pstat CL f0-1 Dev size

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Power/Energy delay product

Power delay product:

Average energy consumed per switch event (i.e., 0 to 1 or 1 to 0)

2 PDP = Pav t p = CLVDD f max t p = 2 CLVDD , 2

( f max =

1 ) 2t p

Energy delay product:

EDP = PDP t p =

2 C LVDD tp 2

- Both PDP and EDP strongly depend VDD - Reducing VDD is an effective way to reduce the PDP/EDP - However, the performance will be degraded
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Appendix: Models for MOSFET (for examples)

Unified device models in 0.25m CMOS : VTO (V) NMOS PMOS 0.43 0 43 -0.4

(V1/2)
0.4 04 -0.4

VDSAT(V) 0.63 0 63 -1

K(A/V2) 115x10 6 115 10-6 -30x10-6

(V-1)
0.06 0 06 -0.1

Req (for WL=1) of NMOS and PMOS in 0.25m CMOS: VDD (V) NMOS(k) PMOS(k) 1 35 115 1.5 19 55 2 15 38 2.5 13 31

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