Important questions on OP-AMP and Digital Electronics 1.

(a) Draw the schematic diagram of an ideal inverting OP-AMP with voltage shunt feedback (b) Define CMRR and Slew rate (c) Draw the schematic diagram of practical Integrator (d) What is value of feed factor for a phase shift oscillator? (e) In a regulated power supply the regulation factor (Sv) =0.03 and output resistance (Ro) =0.5. Compute the change in output voltage (Vo) due to input voltage changes of 5 V and load current (IL) variation from 5A to 6A (f) Define a multiplexer and draw the logic block diagram of a 4 to 1 line multiplexer (g) What is 1 bit memory? Draw its logic diagram. (h) Why is the data bus bidirectional? (i) List the four operations commonly performed by the MPU (P). (j) Name two general purpose devices that may be interfaced with the MPU. 2. (a) An amplifier without feedback has the midband voltage gain AVo = 1000. If the reverse transmission factor () = 0.1 and Vs=0.1V, then for the feedback amplifier, compute the voltage gain (AVof ), the difference signal (Vi) and the output voltage (Vo). At some higher frequency the gain of the amplifier (without feedback) has fallen to half of its previous value, so that AV = 500. Then, if Vs remains at 0.1V, calculate the new values of the voltage gain (AVf ), Vi and Vo, and explain the self-regulatory action of the feedback amplifier. (b) Draw the circuit diagram of a dual input emitter coupled differential amplifier (DIFF AMP) and explain why the CMRR for a symmetrical circuit with
resistors Z and Zf

Re .

3. (a) Show that the expression for the closed-loop gain of a practical inverting OP-AMP is given by

AVf = Y/{Y'(1/AV)(Y'+Y+Yi)}
where Ys are admittance corresponding to the Zs (for example Y'=1/Z') and where the voltage gain AV Vo/Vi, taking the loading of Z' into account, is given by

AV= (Av+RoY')/(1+ RoY') Also show that |Av| , leads to |AV| and AVf (Z'/Z)
(b) Why is Re in an emitter coupled DIFF AMP replaced by a constant current source?

4. (a) Sketch the topology for a generalized resonant circuit oscillator, using impedances Z1, Z2, Z3. (b) At what frequency will the circuit oscillate? (c) Under what conditions does the configuration reduce to Colpitts oscillator? A Hartley oscillator? (d) State the frequency -stability criterion for a sinusoidal oscillator. 5. (a) With the help of suitable circuit diagram explain how the following differential equation can be solved using OP-AMP and other essential circuit elements:

(b) Draw the circuit of an OP-AMP differentiator and explain its operation with the help of suitable waveform charts. (c) Explain why the differentiating OP-AMP circuit is not commonly used as compared to their integrating counterpart. 6. (a) List three reasons why an unregulated supply is not good enough for some applications. (a) Consider two 4-bit numbers A and B with B > A. Verify that to subtract A from B it is only required to add B, A, and 1. Sketch the block diagram of a 4-bit subtractor obtained from a full adder and explain its operation. (c) Reduce the following logic expression using K-map technique and realize using logic gates. F(w,x,y,z) =( 0,1,2,4,5,6,8,9,12,13,14) 7. (a) Show that a 4-bit parallel binary adder can be constructed from cascaded full adders. Draw the truth table for a three-input adder and write the Boolean expressions for the Sum and Carry. (b) Define a decoder. How to decode the 4-bit code 1010 (LSB)

d2v/dt2 + K1dv/dt + K2v v1 =0

8. (a) Explain the race-around condition in connection with the J-K FLIP-FLOP and Also describe two methods to overcome this problem. (b) Draw the block-diagram of a four-stage ripple counter. Sketch the waveform at the input and at the output of each FLIP-FLOP for the counter. Explain how this waveform chart is obtained. 9. Draw the labeled functional block diagram of 8085 microprocessor and describe its primary features. 10. (a) Give the list of Instruction set of 8085- addressing modes.

(b) What do you mean by looping, counting and indexing 11. (a) Write an assembly language program to find the largest data byte among a graph of 16 data bytes. (b) Write a program segment to generate a delay of 100ms. Assume the system clock frequency to be 2 MHz.