Features

Compatible with the ARM7 Family of Processors Can Directly Connect to the Atmel Implementation of the AMBA Peripheral Bus (APB) Controls Power Consumption Elements
Main Oscillator Two Phase Locked Loops (PLLs) PLL Dividers Clock Prescalers ARM Core Clock Peripheral Clocks Drives Up to 30 Peripherals Two Oscillators Main Oscillator 32.768 Hz Clock Supports Three Operating Modes Normal Mode Idle Mode Slow Clock Mode Selection of Four Different Clocks to Drive Peripherals Up to Eight Clocks Can be Driven on Pads Fully Scan Testable (up to 90% Fault Coverage)

32-bit Embedded ASIC Core Peripheral Advanced Power Management Controller for ARM7 (APMC_ARM7)

Description
The Advanced Power Management Controller for ARM7 (APMC_ARM7) optimizes power consumption by controlling all clocking elements such as the oscillators, PLLs and system and user peripheral clocks. The APMC_ARM7 enables/disables the clock inputs to many of the peripherals and the ARM7 Core. Moreover, the APMC_ARM7 features two oscillators and supports three operating modes, which further assists in the optimization of power consumption. Furthermore, the APMC_ARM7 block gives the user the ability to control the driving of up to eight clock signals on pads.

Rev. 2636A-CASIC02/02

Figure 1. APMC_ARM7 Symbol

clk32768_clktree slclk_eq_sysclk a_reqarbiter nasb_clock_e_r hard_arm_clock syn_arm_clock syn_arm_clock_n permanent_clock permanent_clock_n sys_clock sys_clock_n asb_clock asb_clock_n additional_clocks pio_clocks[pio_number-1:0] usart_clocks[usart_number-1:0] digital_clocks[digital_number-1:0] spi_clocks[spi_number-1:0] ssc_clocks[ssc_number-1:0] timer_clocks[timer_number-1:0] div2_clock div8_clock div32_clock div128_clock div1024_clock div4096_clock p_d_out[31:0] Reset Controller Interrupt Controller ASB ARM Debug ARM Test sys_clock_e nint b_wait dbgrqi test_hard_arm test_sys_clock_n pck[7:0] apmc_int pllb_enable plla_enable pllb_div plla_div clock_for_pll_b clock_for_pll_a out_current_plla[3:0] clk_range_out_plla[1:0] clk_range_in_plla[1:0] bias_plla[3:0] out_current_pllb[3:0] clk_range_out_pllb[1:0] clk_range_in_pllb[1:0] bias_pllb[3:0] dataload_plla dataload_pllb main_osc_enable clk_cpu_usb usb_pad_onn clk48_usb test_so[1:0]

On-chip 32K Clocktree Slow Mode Arbiter ASB

Reset

nreset_r nreset_f clk32768 clk_main clkpll_a clkpll_b p_sel_apmc p_write p_stb p_stb_rising p_a[13:0] p_d_in[31:0]

System Clocks

Gated Clocks

User Interface

Arbiter USB

a_reqmaster a_gntpdc a_gntarm a_reqpdc power_down

APMC_ARM7

On-chip System Clock Divided

User Interface Pads Interrupt Controller

PLLs

Test Scan

scan_test_mode test_se test_si[1:0]

Main Oscillator USB

Test Scan

APMC_ARM7
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APMC_ARM7
Pin Description
Table 1. APMC_ARM7 Pin Description
Name Definition Reset nreset_f Reset System Input Low Resets all the counters and signals on falling edge of system_clock Resets all the counters and signals on rising edge of system_clock Type Active Level Comments

nreset_r

Reset System

Input

Low

System Clocks clk32768 clk_main clkpll_a clkpll_b Clock from 32K Oscillator Clock from Main Oscillator Clock from PLL A Clock from PLL B User Interface p_sel_apmc p_write p_stb p_stb_rising Block Selection Write Enable Peripheral Strobe User Interface Clock Signal Input Input Input Input High High High From host (bridge) From host (bridge) From host (bridge) From host (bridge), clock for some DFFs controlling configuration registers The address takes into account the 2 LSBs, but the macrocell does not take these bits into account From host (bridge) To host (bridge) Input Input Input Input Permanently turned on

p_a[13:0]

Address Bus

Input

p_d_in[31:0] p_d_out[31:0]

Input Data Bus Output Data Bus ASB

Input Output

b_wait nasb_clock_e_r

Wait Signal Reserved Arbiter

Input Output

High

From ASB Left unconnected

a_gntarm a_reqpdc a_gntpdc a_reqmaster a_reqarbiter

ARM Granted Signal PDC Request Signal PDC Granted Signal Master Request Signal ARM Request Signal Interrupt Controller

Input Input Input Input Output

High High High High High

From ASB From ASB From ASB From ASB To Arbiter

nint apmc_int

Global (IRQ+FIQ) Line APMC Interrupt

Input Output

High High

From Interrupt Controller To Interrupt Controller

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Table 1. APMC_ARM7 Pin Description (Continued)

Name Definition ARM Debug dbgrqi Debug Interrupt ARM Test test_hard_arm test_sys_clock_n Test Selection Test Selection Slow Mode slclk_eq_sysclk Slow Mode Output On-chip 32K Clocktree clk32768_clktree Clock 32768 Hz Reset Controller sys_clock_e System Clock Enable USB power_down usb_pad_onn clk48_usb clk_cpu_usb USB Power Down USB Pad Enable 48 MHz Clock for USB CPU Clock for USB Gated Clocks hard_arm_clock syn_arm_clock syn_arm_clock_n permanent_clock permanent_clock_n sys_clock sys_clock_n asb_clock asb_clock_n usart_clocks[usart_number-1:0] ssc_clocks[ssc_number-1:0] spi_clocks[spi_number-1:0] timer_clocks[timer_number-1:0] pio_clocks[pio_number-1:0] digital_clocks[digital_number-1:0] additional_clocks Clock for ARM Core Clock for ARM Core Clock for ARM Core Inverted Clock Never Stopped Clock Never Stopped Inverted System Clock System Clock Inverted Reserved Reserved USART Clocks SSC Clocks SPI Clocks Timers PIO Clocks Digital Clocks Additional Clocks Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Only for a hard core Only for a synthesizable core Only for a synthesizable core Even during reset Even during reset Stopped during reset Stopped during reset Left unconnected Left unconnected Clocks for peripherals Clocks for peripherals Clocks for peripherals Clocks for peripherals Clocks for peripherals Clocks for peripherals Clocks for peripherals Input Output Output Output High High Input High System Clock enable from Reset Controller Output For RTC High Periph clocks = 32768 Hz Input Input High Test for ARM Core Test for blocks clocked on sys_clock_n Input High From ARM Type Active Level Comments

APMC_ARM7
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APMC_ARM7
Table 1. APMC_ARM7 Pin Description (Continued)
Name Definition Type Active Level Comments

On-chip System Clock Divided div2_clock div8_clock div32_clock div128_clock div1024_clock div4096_clock System Clock Divided System Clock Divided System Clock Divided System Clock Divided System Clock Divided System Clock Divided PLLs plla_enable pllb_enable plla_div pllb_div dataload_plla dataload_pllb clock_for_pll_a clock_for_pll_b out_current_plla[3:0] clk_range_out_plla[1:0] clk_range_in_plla[1:0] bias_plla[3:0] out_current_pllb[3:0] clk_range_out_pllb[1:0] clk_range_in_pllb[1:0] bias_pllb[3:0] PLL A Enable PLL B Enable PLL A Divided Clock PLL B Divided Clock Sampling Clock for PLL A Sampling Clock for PLL B PLL A Clock PLL B Clock Charge Pump Current for PLL A Output Range for PLL A Input Range for PLL A PLL A Bias Charge Pump Current for PLL B Output Range for PLL B Input Range for PLL B PLL B Bias Main Oscillator main_osc_enable Main Oscillator Enable Pads pck[7:0] Pad Clocks Test Scan scan_test_mode test_se test_si[1:0] test_so[1:0] Clock Selection for Test Purposes Scan Test Enable Scan Test Input Scan Test Output Input Input Input Output High High/Low High All sequential cells are driven with the same clock phase Scan shift/scan capture Entry of scan chain Output of scan chain Output Clocks for external circuits Output High Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Low Low Configurable 5 kHz to 40 MHz Image of bias current of PLL B Configurable 5 kHz to 40 MHz Image of bias current of PLL A p_sel_apmc inverted p_sel_apmc inverted Output Output Output Output Output Output System clock divided by 2 System clock divided by 8 System clock divided by 32 System clock divided by 128 System clock divided by 1024 System clock divided by 4096

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Scan Test Configuration

The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to achieve this, the ATPG vectors must be generated on the entire circuit (top-level) which includes the APMC_ARM7. Therefore, all APMC_ARM7 I/Os must have top-level access and ATPG vectors must be applied to these pins.

APMC_ARM7
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APMC_ARM7
APMC_ARM7 Connections
Figure 2. Connecting the APMC_ARM7 to an ARM-based Microcontroller

To AIC

Arbiter

a_reqpdc a_gntarm a_gntpdc a_reqmaster a_reqarbiter

apmc_int

nreset_f

nreset_r

spi_clocks

SPIs

ssc_clocks 32K Crystal clk32768 usart_clocks APMC_ARM7

SSCs

USARTs

Main Crystal

main_clock

pio_clocks

PIOs

PLLs

pll_clock clock_for_pll pll_div pll_enable

pck[7:0]

Pads

syn_arm_clock or hard_arm_clock

p_a[31:0]

Atmel Bus Interface p_write

p_d_out[31:0]

p_d_in[31:0]

p_stb_rising

p_sel_apmc

p_stb

ASB Atmel Bridge

32-bit ARM Core

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Timing Diagram
Although specifically designed for an ARM7 processor, the APMC_ARM7 can be used with any 32-bit microcontroller if the timing diagram in Figure 3 is respected. Figure 3. APMC_ARM7 Timing Diagram: Write/Read Cycle
p_stb

p_stb_rising

tSU_A p_a[13:0] tSU_DIN p_d_in[31:0] tSU_WRITE

tHOLD_A

tHOLD_DIN

tHOLD_WRITE

p_write tPD1 p_d_out[31:0] tHOLD_SEL tHOLD_SEL Valid tPD2

p_sel_apmc

APMC_ARM7
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APMC_ARM7
Functional Description
The Advanced Power Management Controller ARM7 (APMC_ARM7) generates and controls all the clocks of a system. It allows optimization of power consumption by controlling all the clocking elements such as the oscillators, PLLs and system and peripheral clocks. It consists of the following elements: Slow Clock Oscillator. Supplies the slow clock at 32.768 Hz. Main Oscillator. Supplies the main clock; its frequency depends on the connected crystal. Two dividers, A and B, and two Phase Lock Loops, A and B, allowing a wide range of frequencies to be generated from either the slow clock and/or the main clock. Master Clock Controller. Selects the master clock. Processor Clock Controller. Implements the Idle Mode. Peripheral Clock Controller. Permits power-saving by controlling clocks of the embedded peripherals. Programmable Clock Controller. Allows generation of up to eight programmable clock signals on external pins. Additional divider by 2 (can be bypassed) for USB ports.

Figure 4. Advanced Power Management Controller (APMC_ARM7) Block Diagram

Advanced Power Management Controller (APMC_ARM7)

XIN Main Oscillator XOUT

Divider and PLL B

DIV2

UDP Clock

Programmable Clock Controller

PIO Controller

PCK0 PCK7

Divider and PLL A

Master Clock Controller

Master Clock

Peripheral Clock Controller XIN32 Slow Clock Oscillator XOUT32 User Interface Processor Clock Controller

Peripheral Clocks

Processor Clock

Slow Clock

APB APMCIRQ

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Operating Modes

The following operating modes are supported by the APMC_ARM7 and offer different power consumption levels and event response latency times: Normal Mode: The ARM core clock is enabled and peripheral clocks are enabled depending on application requirements. Idle Mode: The ARM processor clock is disabled and waiting for the next interrupt (or a main reset). The peripheral clocks are enabled depending on application requirements. PDC transfers are still possible. Slow Clock Mode: Slow clock mode is similar to normal mode, but the main oscillator and the PLL are switched off to save power and the processor and the peripherals run in slow clock mode. Note that slow clock mode is the mode selected after the reset. Standby Mode: Standby mode is a combination of slow clock mode and idle mode. It enables the processor to respond quickly to a wake-up event by keeping power consumption very low.

Clock Definitions

The APMC_ARM7 makes the following clocks available: Slow Clock (SLCK), typically at 32.768 Hz Master Clock (MCK), programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller. Processor Clock (PCK), typically the MCK but switched off when entering idle mode. Peripheral Clocks, typically the MCK, available to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) UDP Clock (UDPCK), required by USB Device Port operations. Programmable Clock Outputs (PCK0 to PCK7), can be selected from SLCK, main clock, PLL A Output or PLL B Output and driven on the PCKx pins.

Internally, the main clock is used to indicate the output of the main oscillator, PLL A Output indicates the signal being generated by the divider and the PLL A block, and PLL B Output indicates the signal being generated by the divider and the PLL B block.

Slow Clock Generator

The APMC_ARM7 integrates a low-power 32 kHz oscillator. The XIN32 and XOUT32 pins must be connected to a 32.768 Hz crystal. Two external capacitances must be wired as shown in Figure 5. Figure 5. Slow Clock Generator
XIN32
32.768 Hz Crystal

XOUT32

GNDPLL

CL1

CL2

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APMC_ARM7
Slow Clock The slow clock is the output of the slow clock generator and is the only clock considered permanent in a system that includes the advanced power management controller. It is mandatory in the operations of the APMC_ARM7. In all cases, a 32.768 Hz crystal must be connected to the XIN32 and XOUT32 pins in order to ensure that the slow clock is present. Startup time is given in the product Electrical Characteristics datasheet or in the Oscillator datasheet. As it is often higher than 500 ms and the processor requires an assertion of the reset until it has stabilized (more than 10 slow clock cycles), the user must implement an external reset supervisor covering this startup time. Figure 6 shows the main oscillator block diagram for the APMC_ARM7. Figure 6. Main Oscillator Block Diagram
MOSCEN

Startup Time

Main Oscillator

XIN 3 to 20 MHz Oscillator XOUT Main Clock

OSCOUNT

Slow Clock

Main Oscillator Counter Main Clock Frequency Counter

MOSCS

MAINF MAINRDY

Main Oscillator Connections

The APMC_ARM7 features a main oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 7. The 1 k resistor is only required for crystals with frequencies lower than 8 MHz. The oscillator contains 25 pF capacitances on each XIN and XOUT pin. Consequently, CL1 and CL2 can be removed when a crystal with a load capacitance of 12.5 pF is used. Figure 7. Typical Crystal Connection
XIN XOUT GNDPLL

1K

CL1

CL2

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Startup Time

Startup time is given in the Electrical Characteristics datasheet of the product or in the Oscillator datasheet. The startup time depends on the crystal frequency and increases when the frequency rises. To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock mode is selected. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN bit in the Main Oscillator Register (APMC_MOR). When disabling the main oscillator by clearing the MOSCEN bit in APMC_MOR, the MOSCS bit in APMC_SR is automatically cleared, indicating the main clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator. When the MOSCEN bit and the OSCOUNT are written in APMC_MOR to enable the main oscillator, the MOSCS bit in APMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit can trigger an interrupt to the processor.

Main Oscillator Control

Main Clock Frequency Counter

The main oscillator features a main clock frequency counter that provides the quartz frequency connected to the main oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independent of the application. The main clock frequency counter starts incrementing at the main clock speed after the next rising edge of the slow clock as soon as the main oscillator is stable, i.e., as soon as the MOSCS bit is set in APMC_SR. Then, at the 16th falling edge of slow clock, the MAINRDY bit in APMC_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of APMC_MCFR and gives the number of main clock cycles during 16 periods of slow clock.

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APMC_ARM7
Divider and PLL Blocks
The APMC_ARM7 features two Divider/PLL Blocks that permit a wide range of frequencies to be selected on either the master clock, the processor clock or the programmable clock outputs. Additionally, they provide a 48 MHz signal to the embedded USB device and host ports regardless of the frequency of the main clock. Figure 8 shows the block diagram of the divider and PLL blocks. Figure 8. Divider and PLL Blocks Block Diagram
DIVB MULB OUTB

Main Clock

Divider B

PLL B

PLL B Output

PLLRCB PLLBCOUNT

DIV2

USB_96M UDP Clock

UDP
PLL B Counter SRCA DIVA MULA OUTA LOCKB

Slow Clock

Divider A

PLL A

PLL A Output

PLLRCA PLLACOUNT PLL A Counter

LOCKA

PLL Filters

The APMC_ARM7 features two PLLs that require connection to an external second-order filter through the pins PLLRCA and PLLRCB. Figure 9 is a schematic of these filters. Figure 9. PLL Capacitors and Resistors
PLLRC PLL
R

C2 C GND

Values of R, C and C2 to be connected to the PLLRC pins must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time.

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Source Clock Selection

The source of the Divider and PLL B is always the main clock and cannot be selected. The source of the Divider and PLL A can be selected from either the slow clock or the main clock. The SRCA bit in APMC_PLLAR permits this selection. Note that the user must obtain figures for the input frequency range supported by the PLL integrated in the APMC_ARM7 from the product datasheet and/or the PLL datasheet The two dividers of the APMC_ARM7 increase the accuracy of the PLL A and B output, independently of the input frequency. The main clock can be divided by programming the DIVB field in APMC_PLLBR. The source clock selected by SRCA can be divided by the DIVA field in APMC_PLLAR. Each divider can be set between 1 and 255 in steps of 1. When the DIVA and DIVB fields are set to 0, the output of the divider and the PLL outputs A and B are a continuous signal at level 0. On reset, DIVA and DIVB fields are set to 0, thus both PLL input clocks are set to 0. The two PLLs of the APMC_ARM7 allow multiplication of the divider output. The PLL A and the PLL B output signals have a frequency that depends on the respective source signal frequency and on the parameters DIV (DIVA, DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is (MUL + 1)/DIV. When MULA or MULB is written to 0, the corresponding PLL is disabled and its power consumption is economized. Re-enabling the PLL A or the PLL B can be performed by writing a value higher than 0 in the MULA or MULB field, respectively. Whenever a PLL is re-enabled or one of its parameters is changed, the LOCKA or LOCKB bit in APMC_SR is automatically cleared and the values written in the fields PLLACOUNT or PLLBCOUNT in APMC_PPLAR and APMC_PLLBR, respectively, are loaded in the corresponding PLL counter. The PLL counter then decrements at the speed of the slow clock until it reaches 0. At this time, the corresponding LOCK bit is set and can trigger an interrupt to the processor. The user has to load the number of slow clock cycles required to cover the PLL transient time into the PLLACOUNT and PLLBCOUNT field. The transient time depends on the PLL filters, the initial state of the PLL and its target frequency and can be calculated using a specific tool provided by Atmel.

Divider and Phase Lock Loop Programming

Master Clock Controller

The master clock controller permits selection and division of the master clock (MCK). MCK is the clock provided to all the peripherals, the memory controller and the processor. The master clock is selected from either the slow clock, the PLL A output, the PLL B output or the main clock. Selecting the main clock permits a middle-range performance of the processor while saving the power of both PLLs. Selecting the slow clock permits slow clock mode by providing a 32 KHz signal to the whole device. Selecting the PLL B clock economizes the PLL A power when the USB is operational, but limits the speed of the system to 48 MHz. However, if the additional divider by 2 is used, this speed is 96MHz (see Figure 8 on page 13). Finally, the most flexible solution permits the operation of the USB (at 48 MHz) while the processor and the peripheral set are running at their fastest speed. Please refer to Figure 10 on page 15 to see the block diagram of the master clock controller.

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APMC_ARM7
Figure 10. Master Clock Controller
CSS Slow Clock PLL A Output PLL B Output Main Clock To the Processor Clock Controller Master Clock Prescaler PRES Master Clock

The master clock controller is made up of a clock selector and a prescaler. The clock selection is made by writing the CSS field (Clock Source Selection) in APMC_MCKR (Master Clock Register). The prescaler permits the division by a power of 2 of the selected clock between 1 and 64. The PRES field in APMC_MCKR programs the prescaler. Each time APMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in APMC_SR. It reads 0 until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a lower-speed clock to inform the software when the change is done.
Note: New value to be written in APMC_MCKR must not be the same as current value in APMC_MCKR.

USB Clocks

The USB clock is always generated from the PLL B output. If using the USB Device, the usermust program the PLL B to generate a 48 MHz signal with an accuracy of 0.25% or a 96 MHz signal with an accuracy of 0.25% if the additional divider by 2 is used (bit USB_96M in APMC_PLLBR). When the PLL B output is stable, i.e., the LOCKB is set, the USB device UDPCK can be enabled by setting the UDP bit in APMC_SCER. To save power on this peripheral when it is not used, the user can set the same bit in APMC_SCDR. The same bit in APMC_SCSR gives the activity of this clock. The USB port requires the 48MHz signal and the master clock. The master clock must be controlled via the peripheral clock controller.

USB Device Port Suspend

When the USB Device Port detects a suspend condition, the 48 MHz clock is automatically disabled, i.e., the bit UDP in APMC_SCSR is cleared. It is also possible to automatically disable the master clock provided to the USB Device Port on a suspend condition. The MCKUDP bit in APMC_SCSR configures these features and can be set or cleared by writing one in the same bit of APMC_SCER and APMC_SCDR. When receiving a power-down signal from the USB device, if bit USB_PLL is set in APMC_PLLBR, PLLB is automatically switched off to reduce power consumption.
Note: If system clock is PLLB clock, bit USB_PLL must be permanently reset.

USB Power-down

Processor Clock Controller

The APMC_ARM7 features a processor clock controller that facilitates the idle mode. The processor clock can be enabled and disabled by writing the System Clock Enable (APMC_SCER) and System Clock Disable Registers (APMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System Clock Status Register (PMC_SCSR). The clock provided to the processor is the master clock.

Processor Clock Source

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Idle Mode

The processor clock is enabled after a reset and is automatically re-enabled by any enabled interrupt. The idle mode is achieved by disabling the processor clock and is automatically reenabled by any enabled fast or normal interrupt, or by the reset of the microcontroller. When the processor clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent transfers from other masters of the system bus.

Automatic Wake-up on Debug Request

The processor enters debug mode only if it has a valid clock. If the processor has no clock, any debugger request is forbidden. This is particularly inconvenient, as debug becomes impossible when an application uses the idle mode repetitively. To prevent this incorrect behavior, the APMC_ARM7 automatically re-enables the processor clock when the signal DBGRQ is asserted by the ICE Interface. The user software must initiate the automatic wake-up, as the APMC_ARM7 does not automatically reset the processor to enter Idle Mode when the debugger exits debug mode. To facilitate the detection of this type of wake-up, the bit PROC in APMC_SCSR remains at 0 when a debug request causes the processor to exit from Idle Mode.

Peripheral Clock Controller

The APMC_ARM7 facilitates the control of the clocks of each embedded peripheral. The user can individually enable and disable the peripheral clocks by writing into the Peripheral Clock Enable (APMC_PCER) and Peripheral Clock Disable (APMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (APMC_PCSR). When a peripheral clock is disabled, the clock is immediately stopped. When the clock is reenabled, the peripheral resumes action where it left off. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software waits until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the peripheral clock control registers (APMC_PCER, APMC_PCDR, APMC_PCSR) is the peripheral identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.

Programmable Clock Output Controller

The APMC_ARM7 permits control of up to eight signals to be output on external pins. Each signal can be independently programmed via the registers APMC_PCK0 to APMC_PCK7. The clock can be selected between the slow clock, the PLL A output, the PLL B output and the main clock by writing the field CSS. Each output signal can also be divided by a power of 2 between 1 and 64 by writing thePRES field (Prescaler). Each output signal can be enabled and disabled by writing 1 in the corresponding PCK0 to PCK7 bit of APMC_SCER and APMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCK0 to PCK7 bits of APMC_SCSR (System Clock Status Register). Moreover, like the MCK, a status bit in APMC_SR indicates that the clock is actually what has been programmed in the programmable clock register. As the programmable clock controller does not manage pulse generation when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed. Note also that it is recommended to configure output multiplexed in the PIO controller to enable the signal driving on the pin.

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APMC_ARM7
Programming Sequence
1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCEN field (bit 0 in the APMC_MOR register). In some cases it may be interesting to define a start-up time. This can be achieved by writing a value in the OSCOUNT field (bit 8-15 in the APMC_MOR register). Once this register has been correctly configured, the user must wait for MOSCS field (bit 0 in the APMC_SR register) to be set. This can be done either by polling the status register or by waiting the interrupt line (APMC_INT) to be raised if the associated interrupt to MOSCS has been enabled in the APMC_IER register (bit 0). Code Example:
write_register(APMC_MOR,32'h00000701)

The main oscillator is enabled with a start-up time of seven. Once APMC_MOR has been written, MOSCS bit will be set after seven slow clock cycles. 2. Checking the Main Oscillator Frequency (Optional): In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished via the APMC_MCFR register. Once the MAINRDY field is set (bit 16 in APMC_MCFR register) the user must read the MAINF field (bit 0-15 in APMC_MCFR register). This provides the number of main clock cycles within sixteen slow clock cycles (slow clock is 32768 Hz). 3. Setting PLL A and dividerA: All parameters necessary to configure PLL A and dividerA are located in the APMC_PLLAR register (see block diagram in Figure 8 on page 13. The SRCA field (bit 29) is used to select the clock source for the dividerA. This source is either slow clock (32768 Hz) if bit SRCA is reset or main clock if bit SRCA is set. By default dividerA will be driven by the slow clock (32768 Hz). The DIVA field (bit 0-7) is used to control the dividerA itself. The user can program a value between 0 and 255. dividerA output is dividerA input divided by DIVA parameter. By default, DIVA parameter is set to 0 which means that dividerA is turned off. The OUTA field (bit 14-15) is used to select the PLL A output frequency range (default value is 2'b00). The MULA field (bit 16-26) is the PLL A multiplier factor. This parameter can be programmed between 0 and 2047. If MULA is set to 0 (default value) PLL A will be turned off, otherwise PLL A output frequency is PLL A input frequency multiplied by (MULA + 1). The PLLACOUNT field (bit 8-13) specifies the number of slow clock cycles before LOCKA bit is set in the APMC_SR register after APMC_PLLAR register has been written. Once APMC_PLLA register has been written, the user is obliged to wait for the LOCKA bit to be set in the APMC_SR register. This can be done either by polling the status register or by waiting the interrupt line (APMC_INT) to be raised if the associated interrupt to LOCKA has been enabled in the APMC_IER register (bit 1). All parameters in APMC_PLLAR can be programmed in a single write operation. If at some stage one of the following parameters, SRCA, MULA, DIVA is modified, LOCKA bit will go low to indicate that PLL A is not ready yet. When PLL A is locked, LOCKA will be set again. User has to wait for LOCKA bit to be set before using the PLL A output clock. Code Example:
write_register(APMC_PLLAR,32'h20030605)

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PLL A and dividerA are enabled. PLL A input clock is main clock divided by 5. PLL A output clock is PLL A input clock multiplied by 3. Once APMC_PLLAR has been written, LOCKA bit will be set after six slow clock cycles. 4. Setting PLL B and dividerB: All parameters needed to configure PLL B and dividerB are located in the APMC_PLLBR register (see block diagram in Figure 8 on page 13). The DIVB field (bit 0-7) is used to control the dividerB itself. A value between 0 and 255 can be programmed. dividerB output is dividerB input divided by DIVB parameter. By default DIVB parameter is set to 0 which means that dividerB is turned off. The OUTB field (bit 14-15) is used to select the PLL B output frequency range (default value is 2'b00). The MULB field (bit 16-26) is the PLL B multiplier factor. This parameter can be programmed between 0 and 2047. If MULB is set to 0 (default value) PLL B will be turned off, otherwise PLL B output frequency is PLL B input frequency multiplied by (MULB + 1). The PLLBCOUNT field (bit 8-13) specifies the number of slow clock cycles before LOCKB bit is set in the APMC_SR register after APMC_PLLBR register has been written. Once the APMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the APMC_SR register. This can be done either by polling the status register or by waiting the interrupt line (APMC_INT) to be raised if the associated interrupt to LOCKB has been enabled in the APMC_IER register (bit 2). All parameters in APMC_PLLBR can be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is modified, LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB will be set again. The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock. The USB_96M field (bit 28) is used to control the additional divider by 2, which generates the USB device clock. The USB_PLL field (bit 29) is used to automatically disable the PLLB when power-down information is received by the PPMC_ARM7. Note that if the system clock is PLL B output, USB_PLL must be reset permanently. Code Example:
write_register(APMC_PLLBR,32'h00040805)

PLL B and dividerB are enabled. PLL B input clock is the main clock. PLL B output clock is PLL B input clock multiplied by four. Once APMC_PLLBR has been written, LOCKB bit will be set after eight slow clock cycles. 5. Selection of Master Clock and Processor Clock The master clock and processor clock are configurable via the APMC_MCKR register. The CSS field (bit 0-1) is used to select the master clock divider source. There are four clock options available: main clock, slow clock, PLL A clock, PLL B clock. By default, the selected clock source is slow clock. The PRES field (bit 2-4) is used to control the master clock prescaler. The user can choose between different values (1,2,4,8,16,32,64). Master clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 1 which means that master clock is equal to slow clock. Once APMC_MCKR register has been written, The user must wait for the MCKRDY bit to be set in the APMC_SR register. This can be done either by polling the status register or 18

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APMC_ARM7
by waiting the interrupt line (APMC_INT) to be raised if the associated interrupt to MCKRDY has been enabled in the APMC_IER register (bit 3). All parameters in APMC_MCKR can be programmed in a single write operation. If at some stage one of the following parameters, CSS or PRES, is modified, MCKRDY bit will go low to indicate that master clock and processor clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the master and processor clocks.
Note: IF PLL A (or PLL B) clock was selected as master clock and the user decides to modify it by writing in APMC_PLLAR (APMC_PLLBR) MCKRDY flag will go low while PLL A (PLL B) is unlocked. Once PLL A (PLL B) is locked again, LOCKA (LOCKB) high, MCKRDY will be set. During the laps of time where PLL A (PLL B) is unlocked, master clock selection will be automatically changed to slow clock (main clock). For further information: See Clock Switching Waveforms on page 22.

Code Example:
write_register(APMC_MCKR,32'h00000011)

Master clock is main clock divided by 16. Processor clock is the master clock. 6. Selection of Pad clocks Pad clocks are controlled via registers APMC_SCER, APMC_SCDR and APMC_SCSR. Pad clocks can be enabled and/or disabled via registers APMC_SCER, APMC_SCDR and APMC_SCSR. Depending on the system used, up to 8 pad clocks can be enabled or disabled. The APMC_SCSR provides a clear indication as to which pad clock is enabled. By default all pad clocks are disabled. APMC_PCKx registers are used to configure pad clocks. The CSS field (bit 0-1) is used to select the pad clock divider source. Four clock options are available: main clock, slow clock, PLL A clock, PLL B clock. By default, the clock source selected is slow clock. The PRES field (bit 2-4) is used to control the pad clock prescaler. It is possible to choose between different values (1,2,4,8,16,32,64). Pad clock output is prescaler input divided by PRES parameter. By default PRES parameter is set to 1 which means that master clock is equal to slow clock. Once the APMC_PCKx register has been programmed, The corresponding pad clock must be enabled and the user is constrained to wait for the PCKxRDY bit to be set in the APMC_SR register. This can be done either by polling the status register or by waiting the interrupt line (APMC_INT) to be raised if the associated interrupt to MCKRDY has been enabled in the APMC_IER register (bit 8-15). All parameters in APMC_PCKx can be programmed in a single write operation. If modification of one the following parameters becomes desirable, CSS, PRES or MDIV, the corresponding pad clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the pad clock and wait for the PCKxRDY bit to be set. Code Example:
write_register(APMC_PCK0,32'h00000015)

Pad clock 0 is main clock divided by 32. 19

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7. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers APMC_PCER, APMC_PCDR and APMC_PCSR. Depending on the system used, up to 31 peripheral clocks can be enabled or disabled. The APMC_PCSR provides a clear view as to which peripheral clock is enabled.
Note: All enabled peripheral clocks are equal to master clock.

Code Examples:
write_register(APMC_PCER,32'h10000010)

Peripheral clocks 4 and 28 are enabled.

write_register(APMC_PCDR,32'h00000010)

Peripheral clock 4 is disabled. Additional Features Specific features are configurable via registers APMC_SCER, APMC_SCDR, APMC_SCSR.

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APMC_ARM7
Clock Switching Timings
Table 2. Clock Switching Timings (Worst Case)
From To Main Clock 32K Clock PLL A Clock 0,5 x Main Clk + 4,5 x 32K Clk 0,5 x Main Clk + 4 x 32K Clk + plla_start x 32K Clk + 2,5 x Plla Clk 0,5 x Main Clk + 4 x 32K Clk + pllb_start x 32K Clk + 2,5 x Pllb Clk 4 x 32K Clk + 2,5 x Main Clk 3 x Plla Clk + 4 x 32K Clk + 1 x Main Clk 3 x Plla Clk + 5 x 32K Clk 2,5 x Plla Clk + 4 x 32K Clk + pllb_start x 32K Clk 3 x Pllb Clk + 4 x 32K Clk + 1,5 x Plla Clk 3 x Pllb Clk + 4 x 32K Clk + 1 x Main Clk 3 x Pllb Clk + 5 x 32K Clk 3 x Pllb Clk + 4 x 32K Clk + 1,5 x Plla Clk 2,5 x Pllb Clk + 4 x 32K Clk + plla_start x 32K Clk Main Clock 32K Clock PLL A Clock PLL B Clock

2,5 x Plla Clk + 5 x 32K Clk + plla_start x 32K Clk 2,5 x Pllb Clk + 5 x 32K Clk + pllb_start x 32K Clk

PLL B Clock

Note:

Additional time due to mclk prescaler: 64 x selected clock.

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Clock Switching Waveforms

Figure 11. Switch Master Clock from Slow Clock to PLL A Output
Slow Clock

PLLA Output

LOCKA

MCKRDY

Master Clock

Write APMC_MCKR

Figure 12. Switch Master Clock from Main Clock to Slow Clock
Slow Clock

Main Clock

MCKRDY

Master Clock

Write APMC_MCKR

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APMC_ARM7
Figure 13. Change PLL A Programming
Slow Clock

PLLA Output

LOCKA

MCKRDY

Master Clock clk32768 Write APMC_PLLAR

Figure 14. Programmable Clock Output Programming

PLLA Output

PCKRDY

PCK Output

Write APMC_PCKX

clkpll_a is selected

Write APMC_SCER

pckx is enabled

Write APMC_SCDR

pckx is disabled

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APMC User Interface

Table 3. APMC_ARM7 Memory Map
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 Register System Clock Enable Register System Clock Disable Register System Clock Status Register Reserved Peripheral Clock Enable Register Peripheral Clock Disable Register Peripheral Clock Status Register Reserved Main Oscillator Register Main Clock Frequency Register PLL A Register PLL B Register Master Clock Register Reserved Reserved Reserved Programmable Clock 0 Register Programmable Clock 1 Register Programmable Clock 2 Register Programmable Clock 3 Register Programmable Clock 4 Register Programmable Clock 5 Register Programmable Clock 6 Register Programmable Clock 7 Register Interrupt Enable Register Interrupt Disable Register Status Register Interrupt Mask Register Reserved Reserved Reserved Reserved Reserved APMC_PCK0 APMC_PCK1 APMC_PCK2 APMC_PCK3 APMC_PCK4 APMC_PCK5 APMC_PCK6 APMC_PCK7 APMC_IER APMC_IDR APMC_SR APMC_IMR Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read-only 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 APMC_MOR APMC_MCFR APMC_PLLAR APMC_PLLBR APMC_MCKR Read/Write Read-only Read/Write Read/Write Read/Write 0x0 0x3F00 0x3F00 0x0 APMC_PCER APMC_PCDR APMC_PCSR Write-only Write-only Read-only 0x0 Name APMC_SCER APMC_SCDR APMC_SCSR Access Write-only Write-only Read-only Main Reset 0x1

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APMC_ARM7
APMC System Clock Enable Register
Register Name: Access Type: Offset:
31 23 15 PCK7 7 30 22 14 PCK6 6

APMC_SCER Write-only 0x0000

29 21 13 PCK5 5 28 20 12 PCK4 4 27 19 11 PCK3 3 26 18 10 PCK2 2 MCKUDP 25 17 9 PCK1 1 UDP 24 16 8 PCK0 0 PCK

PCK: Processor Clock 0 = No effect. 1 = Enables the processor clock. UDP: USB Device Port Clock 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port. MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend 0 = No effect. 1 = Enables the automatic disable of the master clock of the USB Device Port when a suspend condition occurs. PCK0..PCK7: Programmable Clock Output 0 = No effect. 1 = Enables the corresponding programmable clock output.

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APMC System Clock Disable Register

Register Name: Access Type: Offset:
31 23 15 PCK7 7 30 22 14 PCK6 6

APMC_SCDR Write-only 0x0004

29 21 13 PCK5 5 28 20 12 PCK4 4 27 19 11 PCK3 3 26 18 10 PCK2 2 MCKUDP 25 17 9 PCK1 1 UDP 24 16 8 PCK0 0 PCK

PCK: Processor Clock 0 = No effect. 1 = Disables the processor clock. UDP: USB Device Port Clock 0 = No effect. 1 = Disables the 48 MHz clock of the USB Device Port. MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend 0 = No effect. 1 = Disables the automatic disable of the master clock of the USB Device Port when a suspend condition occurs. PCK0..PCK7: Programmable Clock Output 0 = No effect. 1 = Disables the corresponding programmable clock output.

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APMC_ARM7
APMC System Clock Status Register
Register Name: Access Type: Offset:
31 23 15 PCK7 7 30 22 14 PCK6 6

APMC_SCSR Read-only 0x0008

29 21 13 PCK5 5 28 20 12 PCK4 4 27 19 11 PCK3 3 26 18 10 PCK2 2 MCKUDP 25 17 9 PCK1 1 UDP 24 16 8 PCK0 0 PCK

PCK: Processor Clock 0 = The processor clock is disabled. 1 = The processor clock is enabled. UDP: USB Device Port Clock 0 = The 48 MHz clock of the USB Device Port is disabled. 1 = The 48 MHz clock of the USB Device Port is enabled. MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend 0 = The automatic disable of the master clock of the USB Device Port when a Suspend condition occurs is disabled. 1 = The automatic disable of the master clock of the USB Device Port when a Suspend condition occurs is enabled. PCK0..PCK7: Programmable Clock Output 0 = The corresponding programmable clock output is disabled. 1 = The corresponding programmable clock output is enabled.

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APMC Peripheral Clock Enable Register

Register Name: Access Type: Offset:
31 PID31 23 PID23 15 PID15 7 PID7

APMC_PCER Write-only 0x0010

30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 24 PID24 16 PID16 8 PID8 0

PID2..PID31: Peripheral Identifier 2 to 31 0 = No effect. 1 = Enables the corresponding peripheral clock.

APMC Peripheral Clock Disable Register

Register Name: Access Type: Offset:
31 PID31 23 PID23 15 PID15 7 PID7

APMC_PCDR Write-only 0x0014

30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 24 PID24 16 PID16 8 PID8 0

PID2..PID31: Peripheral Identifier 2 to 31 0 = No effect. 1 = Disables the corresponding Peripheral Clock.

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APMC_ARM7
APMC Peripheral Clock Status Register
Register Name: Access Type: Offset:
31 PID31 23 PID23 15 PID15 7 PID7

APMC_PCSR Read-only 0x0018

30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 24 PID24 16 PID16 8 PID8 0

PID2..PID31: Peripheral Identifier 2 to 31 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled.

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APMC Main Oscillator Register

Register Name: Access Type: Offset:
31 23 15 30 22 14

APMC_MOR Read/Write 0x0020

29 21 13 28 20 12 OSCOUNT 27 19 11 26 18 10 25 17 9 24 16 8

1 OSCTEST

0 MOSCEN

MOSCEN: Main Oscillator Enable 0 = The main oscillator is disabled. 1 = The main oscillator is enabled. OSCTEST: Oscillator Test Please contact Atmel IP Support for further information. OSCOUNT: Main Oscillator Start-up Time Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.

APMC Main Clock Frequency Register

Register Name: Access Type: Offset:
31 23 15 30 22 14

APMC_MCFR Read-only 0x0024

29 21 13 28 20 12 MAINF 27 19 11 26 18 10 25 17 9 24 16 MAINRDY 8

4 MAINF

MAINF: Main Clock Frequency Gives the number of main clock cycles within 16 slow clock periods. MAINRDY: Main Clock Ready 0 = FMAIN value is not valid or the main oscillator is disabled. 1 = The main oscillator has been enabled previously and MAINF value is available.

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APMC_ARM7
APMC PLL A Register
Register Name: Access Type: Offset:
31 23 30 22

APMC_PLLAR Read/Write 0x0028

29 SRCA 21 28 20 MULA 27 19 26 25 MULA 17 24

18

16

15 OUTA 7

14

13

12

11 PLLACOUNT

10

4 DIVA

Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the APMC_ARM7. DIVA: Divider A
DIVA 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIVA.

PLLACOUNT: PLL A Counter Specifies the number of slow clock cycles before the LOCKA bit is set in APMC_SR after APMC_PLLA is written. OUTA: PLL A Output Frequency Range
OUTA 0 0 1 1 0 1 0 1 PLL A Frequency Output Range Please refer to PLLA datasheet Please refer to PLLA datasheet Please refer to PLLA datasheet Please refer to PLLA datasheet

MULA: PLL A Multiplier 0 = The PLL A is deactivated. 1 up to 2047 = The PLL A output frequency is the PLL A input frequency multiplied by MULA + 1. SRCA: PLL A Source 0 = The Divider A source is the slow clock. 1 = The Divider A source is the main clock.

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APMC PLL B Register

Register Name: Access Type: Offset:
31 23 30 22

APMC_PLLBR Read/Write 0x002C

29 USB_PLL 21 28 USB_96M 20 MULB 27 19 26 25 MULB 17 24

18

16

15 OUTB 7

14

13

12

11 PLLBCOUNT

10

4 DIVB

Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the APMC_ARM7. DIVB: Divider B
DIVB 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIVB.

PLLBCOUNT: PLL B Counter Specifies the number of slow clock cycles before the LOCKB bit is set in APMC_SR after APMC_PLLB is written. OUTB: PLL B Output Frequency Range
OUTB 0 0 1 1 0 1 0 1 PLL B Output Frequency Range Please refer to PLLB datasheet Please refer to PLLB datasheet Please refer to PLLB datasheet Please refer to PLLB datasheet

MULB: PLL B Multiplier 0 = The PLL B is deactivated. 1 up to 2047 = The PLL B output frequency is the PLL B input frequency multiplied by MULB + 1. USB_96M: Divider for USB Ports 0 = USB 48 MHz clock is PLL B output, therefore PLL B output must be programmed at 48 MHz. 1 = USB 48 MHz clock is PLL B output divided by 2, therefore PLL B output must be programmed at 96 MHz. USB_PLL: PLL Use 0 = PLL B is not used to drive the USB Ports. However, PLLB output can be used to drive pckx and/or processor clock. 1 = PLL B is used to drive the USB Ports.
Note: If system clock is PLL B output, USB_PLL must be reset permanently.

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APMC_ARM7
APMC Master Clock Register
Register Name: Access Type: Offset:
31 23 15 7 30 22 14 6

APMC_MCKR Read/Write 0x0030

29 28 20 12 4 27 19 11 3 PRES 26 25 17 9 1 CSS 24 16 8 0

21 13 5

18 10 2

Value to be written in APMC_MCKR must not be the same as current value in APMC_MCKR. CSS: Master Clock Selection
CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected Clock from PLL A is selected Clock from PLL B is selected

PRES: Master Clock Prescaler

PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved

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APMC Programmable Clock Register

Register Name: Access Type: Offset:
31 23 15 7 30 22 14 6

APMC_PCK0 - APMC_PCK7 Read/Write 0x0040 - 0x005C

29 28 20 12 4 27 19 11 3 PRES 26 25 17 9 1 CSS 24 16 8 0

21 13 5

18 10 2

CSS: Programmable Clock Selection

CSS 0 0 1 1 0 1 0 1 Clock Selection Slow Clock is selected Main Clock is selected Clock from PLL A is selected Clock from PLL B is selected

PRES: Programmable Clock Prescaler

PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved

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APMC_ARM7
APMC Interrupt Enable Register
Register Name: Access Type: Offset:
31 23 15 PCK7RDY 7 30 22 14 PCK6RDY 6

APMC_IER Write-only 0x0060

29 21 13 PCK5RDY 5 28 20 12 PCK4RDY 4 27 19 11 PCK3RDY 3 MCKRDY 26 18 10 PCK2RDY 2 LOCKB 25 17 9 PCK1RDY 1 LOCKA 24 16 8 PCK0RDY 0 MOSCS

MOSCS: Main Oscillator Status 0 = No effect. 1 = Enables the main oscillator status interrupt. LOCKA: PLL A Lock 0 = No effect. 1 = Enables the PLL A Lock interrupt. LOCKB: PLL B Lock 0 = No effect. 1 = Enables the PLL B Lock interrupt. MCKRDY: Master Clock Ready 0 = No effect. 1 = Enables the MCK ready interrupt. PCK0RDY..PCK7RDY: Programmable Clock Ready 0 = No effect. 1 = Enables the corresponding programmable clock ready interrupt.

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APMC Interrupt Disable Register

Register Name: Access Type: Offset:
31 23 15 PCK7RDY 7 30 22 14 PCK6RDY 6

APMC_IDR Write-only 0x0064

29 21 13 PCK5RDY 5 28 20 12 PCK4RDY 4 27 19 11 PCK3RDY 3 MCKRDY 26 18 10 PCK2RDY 2 LOCKB 25 17 9 PCK1RDY 1 LOCKA 24 16 8 PCK0RDY 0 MOSCS

MOSCS: Main Oscillator Status 0 = No effect. 1 = Disables the main oscillator status interrupt. LOCKA: PLL A Lock 0 = No effect. 1 = Disables the PLL A Lock interrupt. LOCKB: PLL B Lock 0 = No effect. 1 = Disables the PLL B Lock interrupt. MCKRDY: Master Clock Ready 0 = No effect. 1 = Disables the MCK Ready interrupt. PCK0RDY..PCK7RDY: Programmable Clock Ready 0 = No effect. 1 = Disables the corresponding programmable clock ready interrupt.

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APMC_ARM7
APMC Status Register
Register Name: Access Type: Offset:
31 23 15 PCK7RDY 7 30 22 14 PCK6RDY 6

APMC_SR Read-only 0x0068

29 21 13 PCK5RDY 5 28 20 12 PCK4RDY 4 27 19 11 PCK3RDY 3 MCKRDY 26 18 10 PCK2RDY 2 LOCKB 25 17 9 PCK1RDY 1 LOCKA 24 16 8 PCK0RDY 0 MOSCS

MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. LOCKA: PLL A Lock Status 0 = PLL A is not locked. 1 = PLL A is locked. LOCKB: PLL B Lock Status 0 = PLL B is not locked. 1 = PLL B is locked. MCK_RDY: MCK_RDY Flag Status 0 = MCK Clock is not ready to be turned on. 1 = MCK Clock is ready to be turned on. PCKx_RDY: PCKx_RDY Flag Status 0 = Pad Clockx is not ready to be turned on. 1 = Pad Clockx is ready to be turned on.

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APMC Interrupt Mask Register

Register Name: Access Type: Offset:
31 23 15 PCK7_RDY 7 30 22 14 PCK6_RDY 6

APMC_IMR Read-only 0x006C

29 21 13 PCK5_RDY 5 28 20 12 PCK4_RDY 4 27 19 11 PCK3_RDY 3 MCK_RDY 26 18 10 PCK2_RDY 2 LOCKB 25 17 9 PCK1_RDY 1 LOCKA 24 16 8 PCK0_RDY 0 MOSCS

MOSCS: MOSCS Interrupt Mask 0 = MOSCS interrupt is enabled. 1 = MOSCS interrupt is disabled. LOCKA: PLL A Lock Interrupt Mask 0 = LOCKA interrupt is enabled. 1 = LOCKA interrupt is disabled. LOCKB: PLL B Lock Interrupt Mask 0 = LOCKB interrupt is enabled. 1 = LOCKB interrupt is disabled. MCK_RDY: MCK_RDY Interrupt Mask 0 = MCK_RDY interrupt is enabled. 1 = MCK_RDY interrupt is disabled. PCKx_RDY: PCKx_RDY Interrupt Mask 0 = PCKx_RDY interrupt is enabled. 1 = PCKx_RDY interrupt is disabled.

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Atmel Headquarters
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Microcontrollers
Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60

Asia
Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369

Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom

Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80

ASIC/ASSP/Smart Cards
Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743

Japan
Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581

e-mail
literature@atmel.com

Web Site
http://www.atmel.com
Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Companys standard warranty which is detailed in Atmels Terms and Conditions located on the Companys web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmels products are not authorized for use as critical components in life support devices or systems.

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