CSEN 402: Computer Org. & Sys.

Programming Lecture 2
Slides prepared by: Dr. Ihab Amer Lecturer: Dr. Cherif Salama

Three-state Bus Buffers

Input A Control Input C
Output Y = High impedance if C=0 A0 B0 C0 D0 s1 s0 Enable 0 1 2 3 Bus line with three-state buffers A if C = 1

A three-state buffer

Bus line for bit 0

24 DEC
En

Random Access Memory

content

Memory Transfer
Read: DR M[AR]

Transfer of info into DR from the memory word M selected by the address in AR. Write: M[AR] R1

Transfer of info from R1 into the memory word M selected by the address in AR.

Types of Microoperations

Register transfer Os
Transfer Perform

binary info from one register to another

Arithmetic Os
arithmetic operations on numeric data stored in registers bit manipulation operations on non-numeric data stored in registers shift operations on data stored in registers
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Logic Os
Perform

Shift Os
Perform

Arithmetic Microoperations
Add:

R3 R1 + R2

Subtract:

R3 R1 +

+1

Refer to TABLE 4.3 of textbook for other arithmetic Os

Binary Adder
4-bit binary adder

Refer to Figures 4.7 & 4.8 of textbook for diagrams of binary adder-subtractor and binary incrementer respectively
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4-bit Arithmetic Circuit

Function Table

Thoughts! Can you reverse-engineer this circuit?

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Logic Microoperations
P: R1 R1 R2
1010 1100 Content of R1 Content of R2 Content of R1 after P = 1

Logic OR in control function

0110

Add O

OR O

P + Q:

R1 R2 + R3, R4 R5 R6
Refer to TABLE 4.6 of textbook for other logic Os 9

Hardware Implementation

One stage of a logic circuit

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Applications of Logic Os (1/2)

Selective Set 1010 1100 1110 A before B (logic operand) A after; A A B Selective Complement 1010 1100 0110 A before B (logic operand) A after; A A B

Selective Clear 1010 1100 0010 A before B (logic operand) A after; A A

Mask Operation 1010 1100 1000 A before B (logic operand) A after masking; A A B

Clear Operation (1/2) 1010 1010 0000 A B A after; A A B

Clear Operation (2/2) 1010 1000 0010 A B A after; A A B

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Applications of Logic Os (2/2)

Insert Operation
Step 1: Mask Operation 0110 1010 0000 1111 0000 1010 A before B (mask) A after masking; A A B

Step 2: Insert Operation 0000 1010 1001 0000 1001 1010 A before B (insert) A after insertion; A A B

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Shift Microoperations
Symbolic designation Description

R shl R R shr R R cil R R cir R R ashl R R ashr R

Shift-left register R Shift-right register R Circular shift-left register R Circular shift-right register R Arithmetic shift-left register R Arithmetic shift-right register R

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Arithmetic Shift (for signed numeric values)

Arithmetic Shift Right (by definition, typically related to a division by 2) Rn-1 Rn-2
Sign bit (-6)decimal (-3)decimal

R1

R0

Example 1: R before ashr = 1010

R after ashr = 1101

Overflow FF

Arithmetic Shift Left (by definition, should correspond to a mult. by 2)

Vs = 0 (no overflow) (2)decimal

Vs = Rn-1
(4)decimal

Rn-2

Example 2: R before ashl = 0010

Vs = 1 (overflow occurs) (6)decimal

R after ashl = 0100

(-4)decimal

Example 3: R before ashl = 0110

R after ashl = 1100

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Hardware Implementation

4-bit combinational circuit shifter

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Arithmetic Logic Shift Unit

To select between the arithmetic, logic, or shift outputs To select different Os among the arithmetic and the logic outputs

One stage of an arithmetic logic shift unit

Refer to TABLE 4.8 of textbook for functional description of the diagram

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Reading Assignment
Chapter

4 of textbook

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