IEEE TRANSACTIONS ON EDUCATION , VOL. 30 , NO.

4 , NOVEMlitlt lY3

Noise Margin Criteria for Digital Logic Circuits

J o h n R . Hauser, Pello~, IEEL
Abstract-The concept of noise margin is very important in the design and application of digital logic circuits. Most engineers realize that is it in some way related to the transfer characteristics of inverter circuits and most textbooks have some discussion of noise margin as related to different logic families. However, most textbook descriptions of noise margin are very incomplete and in many cases both contradictory and misleading. This discussion reviews the noise margin issue, discusses many different criteria which have been used to characterize logic gates and discusses the standard treatments of noise margin in typical textbooks. Finally, a noise margin criteria is proposed as a replacement for the standard textbook approaches.

HE first detailed publications dealing with noise margin and its relationship to logic gate transfer characteristics appear to be those of Hill in 1067 and 1968 [l], [2]. His discussion is very good and should be read by anyone interested in noise margin and noise immunity problems. About 10 years after Hills work, a series of papers appeared [3]-[h] describing different approaches to dealing with noise margin and proposing many methods of defining a noise margin criteria. This work was somewhat unified in 1983 by Lohstroh [7] who showed that most of the rxwly proposctl noise margin criteria were all cquivalcnt. Marc will bc said about this e a r l y w o r k later, b u t i t appca~-s to bc mrinly ignorcrl by contemporary textbook authors in favor of more questionable and less complete discussions of noise margin concepts. The concept of noise margin for a logic family is simple, but there are very subtle implications and restrictions. If one has a logic gate, an invertor for example, which satisfied the relationships

Input Voltage

(v)

~hc unshaded arca. such as the solid curve, will have noise m a r g i n s ;rt Icast 25 good 2s given by (4) 2nd (5). For positive noise margins, the ordering of the voltages will be as given in the figure, i.c., \;,I, (output low) < I;,, (input low) < \,rfr (input high) < 1 ;l~ (output high). It is thus relatively easy to dcterminc if a logic family satisfies a given set of logic level, and noise margin relationships by seeing if all the transfer characteristics fall within the required voltage ranges which would be the unshaded area in Fig. 1. If one wants definitions and noise margins which are valid for some temperature range or statistical variation in transfer characteristics, then all characteristics must fall within the required unshaded area of Fig. 1. To accommodate a range of characteristic curves, the logic levels must typically be shifted at the expense of the stated noise margins. The inverse of the problems shown in Fig. 1 is less straightforward. This is the problem of given a logic family or a transfer characteristic, what is the set of optimum logical levels and the corresponding optimum or worst-case noise margins 7 This is a problem addressed, to some extent, by most . modern textbooks on digital electronics. It is an important question and concept since not all logic families have the same noise margins, and the relative magnitudes of the noise margins are important in many applications.

and VI,{ > \,.I 1, (3)

then one can define high and low state noise margins by the definitions

These relationships can be graphically illustrated as in Fig. I. Any invcrtor transfer charxtcristic I[( Ii) which falls within
Mnnuscr~pt rcccivcd July lYc)l, The a u t h o r is with the Ekxtric;d antI (omputcr Eng~nccr~n&! I)~p.~rtmcn~. North Carolina State University, Raleigh, NC 27695. IEEE Log Number 92 I 1752.

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