Xay Dung Cac He Thong Nhung V4-8.2011-BCVT

HC VIN CNG NGH BU CHNH VIN THNG
Khoa Cng ngh thng Tin B mn Khoa hc my Tnh
XY DNG CC H THNG NHNG
H Ni, thng 7 nm 2010
Xy dng cc h thng nhng: M u v Mc lc
Li ni u
Dy v hc h thng nhng l cp ti mt ch c phm vi rng bao gm thit k, mi trng ng dng, loi hnh cng ngh, qui tc cn thit tip cn mt cch c h thng. Lnh vc thit k v ng dng cc h thng nhng bao gm : cc h thng vi iu khin (microcontroller) nh v n gin, cc h thng iu khin, h thng nhng phn tn, h thng trn chip, mng my tnh (c dy v khng dy), cc h thng PC nhng, cc h thng rng buc thi gian, robotic, cc thit b ngoi ca my tnh, x l tn hiu, h thng lnh v iu khin Nn tng cng ngh hin i l k thut vi in t vi mt tch hp ln v rt ln. Khi mun thit k h thng nhng, c nhiu yu t cn tun th ging nh khi thit k my tnh, nhng li b rng buc bi c th ng dng. Thm vo l s an cho ca cc k nng rt cn thit cho thit k h thng nhng, c lp vn hnh, thit k vi tiu ch tiu hao nng lng thp, cng ngh phn cng, cng ngh phn mm (h thng v ng dng), h thi gian thc, tng tc ngi my v i khi c vn an ninh h thng. Nh vy o to v hc h thng nhng cn mt khi lng kin thc tp hp t nht t cc b mn khc nh khoa hc my tnh (computer science), khoa hc truyn thng (communication), k thut thit k in t: cc mch tng t v s, s dng tt cc phn mm thit k bo mch (nh Protel, Proteus), kin thc v ch to bn dn. V l b mn cng ngh c tnh ng dng cao vi bi ton c th, nn li cn c chuyn mn ca ngnh ngh, m h thng nhng s ng dng. Tm li y l mt ch hp nht v vic thc hin ch ny thc khng d dng. Vi lng thi gian nht nh, mn hc XY DNG CC H THNG NHNG s mang li cho ngi hc nhng vn c bn nht v h thng nhng Chng 1. Chng 2 cp ti kin trc phn cng h thng, cch thit k mt s khi chc nng c s c tnh thc t cao. Chng 3 ch yu gii thiu v phn mm ci t trn h thng nhng, bao gm cc trnh iu khin thit b, cc phn mm trung gian, v phn mm h thng c ci t . c bit nhc li mt s yu cu v khi nim ca cc h thng thi gian thc v h iu hnh thi gian thc. Chng 4 gii thiu cc tiu ch v phng php thit k h thng nhng. Cui chng l mt s cc bi tp ln kiu D n thit k, c th la chn cho thc hnh vi cc kiu kin trc h thng nhng khc nhau. Nh nu, y l ch rng, mang tnh k thut v kin thc li c tng hp t cc mn khc, nn ti liu ny chc khng th tht s y . Cc phn kin thc no khng c cp su y, ngi hc cn tham kho thm cc ti liu khc, hay t cc mn hc lin quan.

Tc gi xin chn thnh cm n cc cn b, ging vin Khoa Cng ngh thng tin v b mn Khoa hc my tnh, Hc vin Cng ngh BCVT H Ni gp tc gi hon thnh gio trnh. Tc gi cng xin n nhn cc kin ng gp, ph bnh t ngi c, ngi hc, sao cho ti liu ny c ch hn. a ch theo e-mail: htcuoc@ioit.ac.vn. H Ni, thng 7 nm 2010. Tc gi Hunh Thc Cc, Vin Cng ngh thng tin, VAST, 18, Hong Quc Vit, H Ni.

Mc lc
CHNG 1 ................................................................................................................................... 13 GII THIU CHUNG V CC H THNG NHNG .............................................................. 13 1.1 KHI NIM V H THNG NHNG (HTN) ........................................................... 13 1.2 C IM CA HTN ................................................................................................. 14 1.3 CC YU CU VI HTN ........................................................................................... 16 1.4 M HNH TNG TH HTN ........................................................................................ 17 1.5 PHN LOI HTN ........................................................................................................ 28 1.6 KT CHNG V CU HI ..................................................................................... 34 1.7 CU HI CUI CHNG.......................................................................................... 34 CHNG 2 ................................................................................................................................... 35 CC THNH PHN PHN CNG CA H THNG NHNG ............................................. 35 2.1 B X L TRUNG TM (Central Processing Unit-CPU) .......................................... 35 2.1.1 Cc loi CPU v nguyn l hot ng ................................................................... 36 2.1.2 V d v mt CPU v nguyn l hot ng ............................................................ 36 2.2 CPU 8085 V H THNG BUS ................................................................................. 45 2.2.1 Khi nim v bn cht vt l ca cc BUS............................................................ 46 2.2.2 Bus Driver v Bus Receiver .................................................................................. 48 2.2.3 Bus ng b (Synchronous bus): ........................................................................... 49 2.2.4 Bus khng ng b (Asynchronous bus) ............................................................... 51 2.2.5 Trng ti BUS (bus arbitration) ............................................................................. 53 2.2.6 Bus m rng (Expansion bus) ............................................................................... 55 2.2.7 Thc hin k thut ca BUS .................................................................................. 59 2.3 BO MCH HTN VI CU HNH TI THIU .......................................................... 62 2.4 HTN VI CC CPU KHC NHAU ............................................................................ 66 2.4.1 CPU a nng 16 bit ................................................................................................ 66 2.4.2 Bo mch vi CPU HARVARD-microcontroller (MCU), h Intel 8051/8052/8xC251 ................................................................................................ 70 2.4.3 Vi mch H thng kh trnh trong mt Chip (Programmable System-on-a-chipPsoC) v Vi iu khin (Programmable Intelligent Computer-PIC) ..................... 82 2.5 B NH V THIT K B NH .............................................................................. 96 2.5.1 Mt s thng s chnh ca mch nh .................................................................... 96 2.5.2 Phn loi b nh .................................................................................................... 99 2.5.3 Phn cp b nh .................................................................................................. 107 2.5.4 T chc b nh vt l v thit k b nh ............................................................ 108 2.6 GHP NI VI THIT B NGOI VI ...................................................................... 120 2.6.1 Tng quan ............................................................................................................ 120 2.6.2 Ghp ni CPU ch ng ...................................................................................... 124 2.6.3 Ghp ni I/O ch ng ........................................................................................ 129 2.6.4 Cng vo/ra ......................................................................................................... 143 2.6.5 Ghp ni vi th gii tng t (analog) .............................................................. 148 2.6.5.1 Mt s khi nim lin quan ti s ha............................................................. 149 2.6.5.2 Bin i tng t thnh s (s ha) ................................................................ 150 2.6.5.3 Bin i s thnh tng t (DAC) .................................................................. 150 2.7 KT CHNG ........................................................................................................... 151 4

2.8 CU HI V BI TP ............................................................................................. 151 2.8.1 Cu hi cui chng ............................................................................................ 151 2.8.2 Bi tp cui chng ............................................................................................. 152 CHNG 3 ................................................................................................................................. 154 CC THNH PHN PHN MM CA H THNG NHNG ............................................. 154 3.1 TRNH IU KHIN THIT B ( vit tt: TKTB) ................................................ 154 3.1.1 Tng quan ............................................................................................................ 154 3.1.2 Cc loi TKTB.................................................................................................. 158 3.1.3 Hot ng ca TKTB ....................................................................................... 158 3.1.4 Pht trin TKTB ............................................................................................... 159 3.1.5 Mt s v d v TKTB ...................................................................................... 160 3.2 H THNG NHNG THI GIAN THC ................................................................ 162 3.2.1 H iu hnh a nhim (multitasking) ................................................................ 162 3.2.2 H thng thi gian thc ....................................................................................... 179 3.2.3 H iu hnh thi gian thc (RTOS) ................................................................... 183 3.3 PHN MM TRUNG GIAN (middleware) ............................................................... 189 3.4 PHN MM NG DNG ......................................................................................... 191 3.5 KT CHNG ........................................................................................................... 192 3.6 CU HI CUI CHNG........................................................................................ 192 CHNG 4 ................................................................................................................................. 194 THIT K V CI T CC H THNG NHNG ............................................................. 194 4.1 THIT K H THNG ............................................................................................... 194 4.1.1 Cc nn tng c bn khi xy dng kin trc HTN .............................................. 198 4.1.2 Phn hoch thit k phn cng, phn mm ......................................................... 203 4.1.3 Xy dng bo mch khi pht trin h thng ......................................................... 208 4.2 CI T V TH NGHIM HTN ........................................................................... 212 4.2.1 Chn CPU cho thit k ............................................................................................... 212 4.2.2 Pht trin HTN .................................................................................................... 213 4.2.3 H pht trin, cng c xy dng phn mm v np vo HTN ch ..................... 214 4.2.4 Khi ng h thng ............................................................................................. 218 4.2.5 V d pht trin HTN ........................................................................................... 236 4.3 KT CHNG ........................................................................................................... 236 4.4 CU HI CUI CHNG........................................................................................ 237
PH LC p n cc bi tp cui chng.

Mt s ch vit tt CPU ROM EPROM
Central Processing Unit Read Only Memory Erasable programmable readonly memory n v x l trung tm B nh chi c B nh ch c xa v lp trnh c b nh truy cp ngu nhin B nh bn daaxnkhoong b mt ni dung ngay c khi khng cung cp ngun nui
RAM FLASH
Random Access Memory non-volatile computer storage (memory cards, USB flash drives, solid-state drives SSD)
OS RTOS ES HTN OS hay HH TKTB PLC
Operating System Real Time Operating System Embedded System Embedded System Operating System Device Driver Programmable Logic Controller
H iu hnh H iu hnh thi gian thc H thng nhng H thng nhng H iu Hnh Trnh iu khin thit b b iu khin logic kh trnh
PIC
Programmable Intelligent Computer
My tnh kh trnh thng minh
PSoC
Programmable System - on Chip Application-Specific Integrated Circuit
H thng kh trinh trn vi mch ASIC l mt vi mch c thit k dnh cho mt ng dng c th. 6
ASIC

MCU CICS RISC SPI
Vi iu khin Tp lnh y Tp lnh rt gn ng lin kt d liu ni tip, ng b, hot ng theo kiu Ch/t (Master/Slave)
Microcontroller Unit Complex Instruction Set Reduced Instruction Set Serial Peripheral Interface
I2C
Inter-Integrated Circuit
Bus dng ni gia cc vi mch in t B thu/pht ni tip di b a nng Chng trnh con x l ngt hay Dch v x l ngt iu khin truy nhp mi trng (mng my tnh). V d: MAC address: a ch vt l ca thit b mng.
USART
Universal Serial Aynchronous Receiver/Transmitter Interrupt Service Routine
ISR
MAC
Media Access Control
MIPS IDE
Million instructions per second Integrated Development Environment, hoc: Integrated Design Environment hoc: Integrated Debugging Environment
Triu lnh my trong mt giy L tp cc phn mm h tr cc cng c, tin ch pht trin phn mm my tnh, bao gm: Son tho m ngun, trnh thng dch, trnh bin dch, trnh g ri
ICE
In-Circuit Emulator
L loi thit b phn cng dng g ri khi pht trin 7

phn cng v phn mm hp nht, nh HTN. Vid d nh Logic anlyzer, phn mm MPLAB ca Microchip
Danh sch cc hnh v

Hnh Chng 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 M hnh tng qut bo mch ch Ngun nui cho h my tnh HTN xy dng t xy dng t vi x l (Microprocessor-based) v vi iu khin (microcontroller based) Hai kiu HTN vi 2 loi kin trc CPU M hnh nhn ca kin trc Havard Havard CPU ARM 920T ca Amtel M hnh tng qut HTN Kin trc tru tng HTN S khi CPU DSP-MP3 B MP3 vi CPU BlackFin ca ANALOG DEVICES Mt s HTN thng mi Chng 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Intel CPU 8085 Cc khi chc nng ca CPU 8080/8085 Cc khi nin qui chiu theo CPU Clock Lu thi gian c s ca CPU 8085 (Theo ti liu ca hng Intel) Biu thi gian ca chu k tm lnh Cu hnh ti thiu: CPU 8085 v to BUS h thng CPU Bus v BUS h thng 34 35 41 42 43 44 46 8 Trang 17 18 19 21 21 22 23 24 27 27 29
2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29 2.30 2.31 2.32
Chu k c ng b BUS khng ng b, hot ng ng b bi i thoi gia cc tn hiu iu khin. BUS chui quay vng (daisy chaining) Trng ti BUS Trng ti Bus khng tp trung trong multibus Lin kt qua bus SPI Lin kt qua bus I2C Cc mch logic thng dng trong thit k k thut s Cc kiu ni u ra, u ra tr khng cao Vi mch 3 trng thi: hai trng thi logic v trng thi th 3 HZ: u ra b tch khi BUS. Mch cht (hay nh, gi li) kiu D, lm vic theo mc hay sn ln ca xung ng h CK. (Xem thm chi tit mach SN 7474). Cht 4 bit vi D-Flip/flop Cng khuych i (driver) cht hai chiu Cu hnh ti thiu bo mch CPU 8085, RAM/ROM/Ports Mch in cho hnh 2.21 CPU Intel x86 24 Bo mch vi ti thiu vi CPU 8086:BUS controller, Ngt controller, RAM CPU 8086 timing: lnh c M hnh kin trc Havard Cc khi chc nng ca CPU 8051/8052 CPU 8051:EEPROM, RAM bn trong v kh nng m rng b nh ti 64 KB Bo mch vi CPU 8051/8052 Cc khi chc nng ca nhn 8Xc251 CPU 8051 Phn hoch a ch trong CPU 8051
47 50 52 52 53 56 56 57 58 59 59 60 60 62 63 64 67 67
69 70 72 73 75 76 9
2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.40 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.56 2.57 2.58 2.59 2.60
Bo mch vi CPU Intel 8051 v RAM, ROM m rng bn ngoi M hnh mt vi iu khin kiu PsoC hay PIC Vi iu khin PSoC CY8C29466 Vi iu khin PIC 16F882/883/886/887 M hnh u vo/ra ca phn t nh Phn loi b nh Cc loi b nh ROM Cc loi RAM 1 chip RAM 32K x 8 (32K byte) Phn t DRAM M hnh hot ng ca RAM cache S v ngoi mt vi mch (chip) nh (pin-out) S khi chc nng bn trong chip 16K x 1 bit S thit k bng nh SRAM 16K x 8, vi Chip 16Kx1 S khi chc nng ca 1 chip DRAM thng mi 4164Kb Quan h cc tn hiu iu khin DRAM 4164x1 thng mi CPU 8080/8085 Module DRAM 64 KB ton phn Chip ROM 2764 thng mi S thit k ROM 32KB t 4 Chip 2764 V d v cch phn b b nh trong my tnh PC M hnh k thut ghp ni Cc kiu ghp ni c d liu vo: D liu_t thit b vo ACC sau vo RAM a d liu t RAM vo ACC sau ACC ra thit b Trao i d liu c vo c iu kin Lu iu khin c d liu v c iu kin Lu iu khin c d liu kiu quay vng Cc kiu ngt
77 80 82 84 87 88 89 89 90 91 93 94 96 96 97 98 99 100 102 103 106 106 107 108 109 110 111 112 10
2.61 2.62 2.63 2.64 2.65 2.66 2.67 2.68 2.69 2.70 2.71 2.72 2.73 2.74 2.75 2.76
Thit kt vi ngt cng che c INTR ca CPU Vector ngt v chuyn x l ti ISR T chc ngt vi iu khin ngt M rng s ngt vi 2 vi mch 8259 Nguyn l DMA DMA v hot ng ca CPU l c lp Lu DMA ghi d liu t RAM ra thit b ngoi Cng song song trn PC v gii ngha cc chn cng Lu cc tn hiu cng song song Cng song song hai chiu u ni RS 232 cc loi DB9, DB 25 v DEC MMJ PC lm h pht trin phn mm cho HTN, ph hp tn hiu gia RS-232 ca PC v cng SI-P ca HTN ang pht trin Cng SI-P n gin, dng ngun t RS 232 ca PC ADC v ghp vo HTN HTN v DAC Bi tp thit k ghp ni ADC, cng LPT vo my tnh PC Chng 3 M hnh tng qut cc phn mm trn my tnh M hnh tng qut cc cc kiu sp xp phn mm trn my tnh Cc kiu tc v Biu thc hin mt tc v Phn loi cc gii thut lp lch thc hin tc v Quay vng kt hp u tin v chen ngang Gii thut vi gim st nh thi (ch canh chng) S kin v p ng RTOS nhn thi gian thc v RTOS a nng Cc chc nng nhn RTOS
113 114 115 116 118 119 120 122 122 123 124 126 126 128 128 131
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10
133 134 141 143 144 146 148 151 155 156 11
3.11 3.12 3.13 3.14 3.15
Cc h iu hnh RTOS H thng nhng thi gian thc V tr cua PMTD HTN M hnh cc lp mng theo TCP/IP, OSI v nh x vo HTN Cc ng dng WEB trong HTN, t lp phn mm ng dng Chng 4 Kch bn m phng hiu nng khi thit k HTN Cc cu trc kiu 4+1 Cc pha thit k HTN Gii thut thit k my in laser: phn hoch cng/mm Phn hoch thit k phn cng v phn mm Xy dng m hnh hnh thc: Bc sng lc s dng cch tng hp phn cng v phn mm chuyn ha xc nh chc nng vo m hnh phn cng ca thit k. Bo mch HTN H pht trin HTN Qui trnh pht trin phn mm cho HTN S n gin h thng v nh x b nh vo HTN ch nh x thc thi chuyn vo b nh ca h thng
156 157 158 159 160
4.1 4.2 4.3 4.4 4.5 4.6
164 165 166 167 168
171 172 176 177 177 178
4.7 4.8 4.9 4.10 4.11
12
Chng 1: Gii thiu chung v h thng nhng

CHNG 1 GII THIU CHUNG V CC H THNG NHNG
1.1 KHI NIM V H THNG NHNG (HTN) Nhn li nhng nm 70 th k trc, x l thng tin thng phi s dng cc my tnh ln hay my tnh mini (v d dng my mini PDP 11 ca hng DEC mt h thng thng tr trong truyn thng). Cho ti nhng nm 80, khi vi x l v my tnh c nhn (PC bn v xch tay) ra i, my tnh tr thnh cng c c dng cho x l thng tin bi kh nng tnh ton nhanh, gn nh v di ng linh hot. Giai on tip theo l kh nng ch to vi mch kch thc vi trm micro mt v nano mt ca nhng nm chn mi, thc y xu hng nh ha (miniaturization) v a dng cc dng vi x l, pht trin mnh m. Cc b vi x l a nng v s xut hin cc vi x l chuyn bit (ASIC- application-specific integrated circuit) c ch to vi s lng ln cha tng thy. Vic s dng cc b vi x l chuyn bit to ra cc thit b chuyn x l mt hay mt vi bi ton k thut, to ra mt nghnh cng ngh mi, gi l cng ngh nhng. Sn phm ca cng ngh nhng ny l cc h thng nhng. Vy h thng nhng (HTN- Embedded system) l g ? C nhiu nh ngha v HTN, nhng nu ta ly tiu ch m t HTN lm ci g v s dng n nh th no, th c th ni v HTN nh sau: H thng nhng l mt thut ng ch mt h thng c kh nng hot ng t tr c nhng vo trong mt mi trng hay mt h thng khc qui m phc tp hn. l cc h thng tch hp c phn cng (l mt h thng my tnh c xy dng trn c s s dng vi x l microprocessor-based system) v phn phm nhng trong phn cng , thc hin cc bi ton chuyn bit. Hay theo nh ngha ca t chc IEEE th h thng nhng l mt h tnh ton (my tnh s) nm trong (hay c nhng vo) sn phm khc ln hn v rng thng thng n i vi ngi s dng. Ni rng ra, v n gin hn, khi mt h tnh ton (c th l PC, IPC, PLC, vi x l, vi h thng (microcontroller), DSP v.v...) c nhng vo trong mt sn phm hay mt h thng no v thc hin mt s chc nng c th ca h thng , th ta gi h tnh ton l mt h thng nhng. Tuy nhin tht khng d g nh ngha cho tht ng v HTN, nh ngha trn rt t ni ti cng ngh v cng rt n gin. Hin nay cha c nh ngha no tht tha ng v HTN, v d nu ly chc nng x l thng tin, th HTN l mt phn x l thng tin nhng trong cc h thng ln hn v phc tp hn, hay cng c th l mt h thng c lp vn hnh t ng. V d gn gi ta c: my tnh c nhn, hay my ch, l mt h thng phc tp c xy dng t cc thnh phn hot ng c lp nhng c ng b vi nhau. V iu khin ha, 13

c vi iu khin rt mnh x l ha, v iu khin trn a cng c vi iu khin chuyn dng x l tn hiu, ghi/c d liu t a t tnh theo yu cu ca h iu hnh, v mng cng l mt vi iu khin tinh vi x l tn hiu l cc h thng con c nhng trong h thng my tnh ni chung. Mc d vy ta cng s nu ra y mt s im chung v HTN.
1.2 C IM CA HTN hiu r hn v HTN, ta nu ra mt s c im nhn bit v mt h thng nhng: L mt kiu my tnh ng dng c bit, rt gii hn v phn cng v phn mm khi so snh vi cc my tnh a nng, nh my tnh c nhn, my ch, siu my tnh. iu ni ln rng hiu nng x l, nng lng tiu th, b nh, cc phn cng khc u hn ch. Cn phn mm hn ch, hay phn mm l c nh, c ngha h iu hnh c thit k ph hp vi cc x l nh. Hin nay h iu hnh thng s dng l h iu hnh a nhim (nh DOS 6.X h tr a nhim trn cc loi HTN dng PC 104), hay h iu hnh thi gian thc. Nu khng c h iu hnh, th cng l mt kiu chng trnh iu khin chung (monitor) no . Phn mm vit ra khng c cc phn m c mc tru tng hay c cng mc thp. M thc thi (gm h iu hnh v cc ng dng) c np vo b nh ROM. Nhn chung m thc thi c kch thc nh v ti u v ROM c dung lng nh. Tuy nhin vi s pht trin nhanh chng ca cng ngh, cch nu trn c th thay i, bi s c cc HTN rt tinh xo v mc phc tp rt cao, b nh c th n vi chc mega bytes. HTN c thit k thc hin mt hay vi ng dng xc nh, chuyn bit (Application specific), v d cc thit b nhng cng nghip nh robot thuc loi ny. Tuy nhin c nhng thit b nhng khc nh cc PDA, in thoi di ng, l cc HTN c kh nng thc hin nhiu chc nng hn. Hay cc Tivi k thut s li c th thc hin cc ng dng tng tc vi mn hnh cm ng, v.v Tuy nhin xu hng hin nay l to ra cc HTN kh trnh c giao din kt ni vi mt h pht trin khc nng cp phn mm. HTN tng tc vi mi trng ng dng qua nhiu phng thc: Qua cc b cm bin (sensor), ghp ni vo HTN bng dy dn, hay khng dy; Pht trin cc giao thc truyn tin ring bit, hay theo cc giao thc chun trao i thng tin vi cc thit b khc, c th c h tr ni mng LAN; HTN thuc loi thit b thng minh t phn ng (reactive), b ng nhng tng tc lin tc vi mi trng v c p ng kp thi vi nhng tin trin (s kin) m mi trng xc lp. Tng tc ngi-my rt n gin nu c v HTN chy c lp v thng tin vi h thng ln hn l chnh. Ngy nay xu hng WEB ha giao din tng tc l ph bin, v d cc thit b kt ni mng Internet nh ADSL dng SOHO (Small 14

Office-Home Office), c WEB lm cu hnh v qun tr. Tng t, cc HTN cng nghip cng pht trin theo xu hng ny d qun tr t trung tm iu khin. HTN hot ng c lp, do cc c im sau y: tin cy, l tng l khng c s c hng hc. Bo tr: thi gian bo tr nhanh chng. C tnh sn sng cao, l kt qu ca s tin cy v bo tr. An ton: nu c s c xy ra, HTN khng gy ra nhng tc hi khc ca ton h thng. An ninh: d liu ca HTN c bo mt, truy nhp phi c xc nhn (v d, HTN l cc thit b truyn thng, SOHO). HTN l mt kiu my tnh c yu cu v cht lng v tin cy rt cao, hot ng c trong cc mi trng khc nghit v nhit (cao, hay rt thp), m cao, rung ng ln, nhiu sng in t v.v V d cc my tnh trong cng nghip, cc thit b truyn thng, trm BTS chng hn, hay cc my tnh iu khin trn my bay (fly by wire) Phn ln cc h thng nhng hot ng vi s rng buc thi gian: yu cu c thi gian cho (p ng) u ra nhanh, ng thi im, trong mi tng quan vi thi im xut hin ca (s kin) u vo. Kiu hot ng nh vy gi l to p ng theo thi gian thc. Thi gian thc c th chia ra lm hai kiu: Nhy cm vi thi gian (time- sensitive): s kin ch c x l trong mt khung thi gian nht nh; Thi gian ti hn (time critical): khi c s kin, h thng phi phn ng ngay, chuyn nhanh nht n m chng trnh ng vi s kin x l, ni cch khc trong mt ca s thi gian cho php, x l phi c thc hin v phi c p ng u ra. V d nu vng phn hi trong cc h c iu khin HTN l b iu khin chy gii thut iu khin khng nhanh (x l, tnh ton qu lu), h thng tr nn khng n nh.
C hiu nng cao. Cc s o sau y se phn nh c tnh ny: S dng nng lng thp v hiu qu. C th thy im ny cc thit b di ng. M phn mm c kch thc rt ti u, v m phi ci ton b trn HTN. Thi gian x l tc v (run-time) phi nhanh, s dng t ti nguyn phn cng (v lin quan ti tiu hao nng lng). Trng lng nh. y l mt trong nhng lc chn khi mua mt HNT. Gi thnh rt cnh tranh. Mun vy thit k v s dng phn cng, phn mm cn quan tm ti hiu qu.
15

Di y l cc v d v cc HTN nhn gc s dng:
Lnh vc ng dng t in t tiu dng
Thit b nhng nh la in t, iu khin ng c, h thng phanh, h s Tivi analog, Tivi s, CD, DVD, VCR, PDA, in thoi di ng, CAMCODER, GPS, t iu ha, t lnh, l vi sng
Cng nghip Y t Mng thng tin (WAN, LAN, thoi) Vn phng Cc lnh vc khc: an ninh, quc phng, hng khng, hng hi
Robot, dy chuyn sn xut t ng, SCADA agents My thm tch, my pha-lc, my th, my tr tim, my qut ct lt, rt nhiu thit b y t hin i B nh tuyn, gateway, chuyn mch mng, cc thit b truyn thng-mng, trm chuyn tip, BTS di ng My Fax, my potocopy, my in (kim, laser, phun), my qut, mn hnh LCD c hp nht trong rt nhiu kh ti hin i ca tt c cc binh chng .
1.3 CC YU CU VI HTN HTN thc t l mt loi my tnh dng x l thng tin dng s. HTN c th l mt h thng c lp nh mt thit b tch cc trong m hnh iu khin, tc HTN l mt regulator s, thc hin cc chc nng ca PID regulator, khi cc chc nng ny c th hin bi thut ton v chuyn ha dng m chng trnh trong HTN. Trong khi HTN li l mt phn ca mt qui trnh cng ngh trong cng nghip. Nh trn lit k cc c im chung m cc h thng nhng thng c, t nhin ta c th rt ra c nhng yu cu cn c trn mt h thng nhng. 1. Kh nng p ng vi s kin bn ngoi (t cc tc nhn b kim sot) phi nhanh nhy, kp thi, tc l kh nng theo thi gian thc: Cc tc v c p ng rng buc bi thi hn cht (deadline); 16

Thi gian pht hin li phi rt ngn (ti thiu); Khi chy cc chu trnh vng lp iu khin bng phn mm phi c p ng u ra ng thi hn; 2. 3. 4. 5. 6. C kh nng lm mi trng khc nghit. C gi thnh thp hay hiu qu hot ng/gi thnh hp l. Kch thc nh gn, nh, d mang d vn chuyn, lp t. Tiu th nng lng thp, kh nng s dng ngun pin, c qui (tt nhin ph thuc vo dung lng ca pin, c qui). Hot ng tin cy, chu li cao Tin cy: p ng dch v yu cu ng thi hn sau thi gian t t0 n t; Cho hng s ca t s s c trong thi gian 1 gi ng h l e (e/h), th biu din t s s c l R(t)=exp , sau thi gian gia 2 ln s c (Mean Time To Failure- MTTF) s l 1/R(t); tin cy cao nu t ~10-9 s c /gi. Tnh sn sng cao: Nu thi gian sa cha s c trung bnh l MTTR, th tnh sn sng (availability) A=MTTF/(MTTF+MTTR). 7. 8. An ton v bo mt. Kh nng nng cp phn mm v d phng nng cp phn cng (m rng qua khe cm d tr, v d cc thit b mng thng c tnh nng ny).
(-e(t-t0))
1.4 M HNH TNG TH HTN Nh nu trong nh ngha ca HTN, th HTN c kin trc ca mt my tnh s, do vy s khng c g khc bit khi m t m hnh kin trc ca HTN ni chung. C khc chng l chi tit ca tng HTN c th. M hnh chc nng ca my tnh Di y ta nu ra m hnh tng qut ca my tnh theo nguyn l Von Neumman. HTN cng chia s kin trc ny trong mt s trng hp. M hnh cho thy cc khi chc nng c bn cn c. Trong thc t c nhng CPU nhng c kin trc c th khc nhau, nhng khi m t cc khi chc nng, th hon ton thng nht.
17

ng h thch anh nhp chun
B nh Ghi/c (RAM)
B nh ch c (ROM)
H thng ng
dy a ch (ADDRES BUS
B vi x l trung tm (CENTRAL PROCESSING UNIT)
H thng ng dy iu khin (CONTROL BUS)
H thng ng
dy d liu (DATA BUS)
Ghp ni ra (O) Ngun nui mt chiu
Ghp ni vo (I)
Hnh 1.1- M hnh tng qut bo mch ch
n v x l trung tm (Central Processing Unit CPU) l khi chc nng c bn nht to nn mt h vi x l, HNT hay my tnh c nhn (Personal Computer PC). CPU thc hin chc nng x l d liu theo nguyn tc thc hin chng trnh my tnh ci trong b nh ROM hay np vo b nh RAM. Vic thc hin nh sau:CPU c m lnh (OPCODE) t b nh (ROM hay RAM) . Gii m lnh, to cc tn hiu (xung) iu khin tng ng vi m lnh iu khin hot ng ca cc khi chc nng khc trong CPU v bn ngoi CPU. Thc hin tng bc cc thao tc x l d liu nh ngha trong m lnh. b) B nh chnh (ROM/RAM) c t chc t cc t nh n, kp. Theo chun ca IBM/PC t nh n (c s) c di 1 byte (8 bits). B nh ny gm cc chip nh ch c ROM (Read Only Memory) v cc chip nh truy xut ngu nhin RAM (Random Access Memory) c tc truy cp nhanh. B nh c s dng cha cc chng trnh v cc d liu cn x l. Cc chng trnh ng dng v d liu c th c cha ROM hoc RAM, cc kt qu trung gian hay kt qu cui cng ca cc thao tc x l c th c cha trong cc thanh ghi a dng hoc trong RAM. Cc mch ghp ni vo/ra (I/O) l cc mch in t cho php CPU trao i d liu vi cc thit b ngoi vi nh bn phm, mn hnh, my inlm giao din vi ngi dng hoc cc b chuyn i s-tng t DAC (Digital/Analog Converter), chuyn i tng t-s 18

ADC (Analog/Digital Converter), cc mch vo/ra d liu dng s DO (Digital Outputs), DI (Digital Inputs) H vi x l cn c mt mch to xung nhp gi l CPU Clock. B to xung ny c iu khin bng mt mch thch anh c tn s thch hp v m bo tn s lm vic n nh, vi tn s chnh xc cao. CPU c mt chn pht xung cho cc vi mch cn li, gi l ng h h thng (System Clock), ng h ny ni ti tt c cc vi mch iu khin chnh trn bo mch, ng b ton b hot ng vi CPU. Mt khi ngun nui (Power Supply) cung cp nng lng cho h thng t mng in li, hay s dng pin. B ngun ca cc h vi x l thng thng l b ngun xung vi k thut ng-ngt dng linh kin bn dn cng sut (Switching Power Supply), va gn nh, cng sut ln, hiu sut cao.
Hnh 1.2-Ngun nui cho h my tnh Phn loi trn c s vi mch Tuy nhin khi cp ti cu trc ca HTN c xy dng trn cng ngheejnvi mch, c th c hai loi khc bit: H thng nhng da trn b vi x l trn bo mch Microprocessor-based Embedded System C CPU c lp, c th l CPU a nng ph bin (Intel 8080/8085, Motorola 6800), C RAM, ROM, nh thi , I/O c lp, Kh nng m rng RAM, ROM, Microcontroller-based Embedded System CPU dng li chuyn bit, RAM, ROM, nh thi, I/O trong mt vi mch n, RAM, ROM c dung lng c nh, I/O cho mc ch s dng, n mc ch, ng dng xc nh, 19 Vi vi iu khin trn bo mch

I/O ty , a nng, t tin. Kin trc gn nh mt my tnh nhng c kch thc nh. Thit k chc nng: Cn phi c cc vi mch RAM, ROM hp thnh t bn ngoi vi mch. Khng th kt ni vi ngoi vi ngoi vi, cn c thm cc vi mch h tr cho chc nng ny. Tuy nhin nng lc tnh ton mnh. tiu hao t nng lng, gi c hp l cho ng dng nhng. Kch thc nh, gn. Thit k chc nng: c thit k c tt c trong mt Chip ! Nng lc tnh ton c thit k ti u cho ng dng xc nh. Rt ph hp xy dng cc HTN Tit kim gian thit k.
Microcontroller differs from a microprocessor in many ways. First and the most important is its functionality. In order for a microprocessor to be used, other components such as memory, or components for receiving and sending data must be added to it. In short that means that microprocessor is the very heart of the computer. On the other hand, microcontroller is designed to be all of that in one. No other external components are needed for its application because all necessary peripherals are already built into it. Thus, we save the time and space needed to construct devices.
Hnh 1.3
HTN xy dng t xy dng t vi x l(Microprocessor-based) v vi iu khin (microcontroller based) 20
Microcontroller v cc thnh phn c bn, BUS kt ni bn trong.
Kin trc ca CPU
Phn nhiu cc ti liu khi cp ti thit k HTN, u dnh mt s ch v kin trc v cch thit k ch to CPU. y l mt vn chuyn v rt su, ti liu ny s khng dn xut. Ti liu ch gii hn gii thiu cc kiu CPU c th s dng thit k HTN. Cc kiu CPU ny rt ph bin trn th trng, rt a dng vi nng lc x l khc nhau v ph hp cho mi loi ng dng nhng. Di y l mt trong cc quan im nhn nhn CPU: Tp lnh: c th l CISC hay RISC, trong RISC l ph bin. Hot ng theo kiu Von Neumman, v d in hnh nh hnh v trn, trong H thng BUS a ch v BUS d liu, BUS iu khin chung cho ton b h thng, b nh chia s chung cho ton h thng vi vng m lnh (code) v d liu (data) trn cng khng gian a ch b nh v BUS d liu khng th truyn ng thi m lnh v d liu cng mt thi im. Qu trnh thc hin mt lnh my nh sau: 21

1) c m lnh t ROM/RAM qua BUS d liu vo CPU, gi m xc nh lm g tip theo; 2) c d liu tip theo l mt phn ca lnh (operands) nu c qua BUS d liu; 3) Thc hin lnh khi c ht cc operands ca lnh; 4) Lu kt qu ra RAM qua Data BUS. Nh vy BUS d liu l knh duy nht trao i d liu, do vy ta ni BUS d liu b bo ha, hiu nng tnh ton b hn ch. Vi cc CPU hin i BUS d liu c ci tin rt nhiu, c bit l giao thc BUS v ng h BUS c nng cao ci thin hn ch ni trn. V hot ng kiu Harvard vi mt s c im khc bit : Howard Aiken (1900-1973) khi xy dng my tnh vi cc rel tch cc b nh d liu (RAM) v b nh chng trnh vi cc bus ring r truy cp vo b nh d liu (RAM) v b nh chng trnh (NVM Non Volatile Memory: ROM, FLASH) cha phn mm nhng (h iu hnh, Device drivers, ng dng nhng ). Cc bus iu hnh c lp, cc ch dn chng trnh v d liu c th c a ra cng mt lc, ci thin tc so vi thit k vi ch mt bus. Phn bit r rng b nh d liu v b nh chng trnh, CPU c th va c mt lnh, va truy cp d liu t b nh cng lc. Do cc BUS c lp, CPU c kh nng tm trc (instruction prefetch), nn vi kin trc Harvard chng trnh chy nhanh hn, bi v n c th thc hin ngay lnh tip theo khi va kt thc lnh trc . Tuy nhin v kin trc c phn phc tp hn trong phn cng, nhng cho hiu qu hn cho cc ng dng nhng. L loi ph bin thit k cc HTN.
22
Hnh 1.4-Hai kiu HTN vi 2 loi kin trc CPU
Harvard, Modified Harvard, or von Neumann?

Three characteristics may be used to distinguish Modified Harvard machines from Harvard and von Neumann machines:
Instruction and data memories occupy different address spaces. For pure Harvard machines, there is an address 'zero' in instruction space that refers to an instruction storage location and a separate address 'zero' in data space that refers to a distinct data storage location. By contrast, von Neumann and modified Harvard machines store both instructions and data in a single address space, so address 'zero' refers to only one thing and whether the binary pattern in that location is interpreted as an instruction or data is defined by how the program is written. This characteristic unambiguously identifies a pure Harvard machine. o By a strict interpretation of this distinction, for example, the Microchip PIC17 and PIC18 architectures, as well as the Atmel 8-bit AVR architecture, would be regarded as pure Harvard Architecture machines because they do, in fact, maintain a distinct separation between code and data spaces, and address 'zero' of each does, in fact, refer to a physically different piece of memory. However, the distinction is made ambiguous by the colloquial use of the term "modified Harvard Architecture" to refer to such machines' inclusion of special instructions to read and/or write the contents of code space as though it were data.[1] Instruction and data memories have separate hardware pathways to the central processing unit (CPU). This is the point of pure or modified Harvard machines, and why they co-exist with the more flexible and general von Neumann architecture: separate memory pathways to the CPU allow instructions to be fetched and data to be accessed at the same time, improving throughput. The pure Harvard machines have separate pathways with separate address spaces. Modified Harvard machines have such separate access paths 23

for CPU caches or other tightly coupled memories, but a unified address space covers the rest of the memory hierarchy. A von Neumann processor has only that unified address space. From a programmer's point-of-view, a modified Harvard processor is usually treated as a von Neumann machine until cache coherency becomes an issue, as with selfmodifying code and program loading. This can be confusing, but such issues are usually visible only to systems programmers and integrators.[clarification needed]
Instruction and data memories may be accessed in different ways. The original Harvard machine, the Mark I, stored instructions on a punched paper tape and data in electro-mechanical counters. This, however, was entirely due to the limitations of technology available at the time. Today a Harvard machine such as the PIC microcontroller might use 12-bit wide flash memory for instructions, and 8-bit wide SRAM for data. In contrast, a von Neumann microcontroller such as an ARM7TDMI, or a modified Harvard ARM9 core, necessarily provides uniform access to flash and SRAM (as 8 bit bytes, in those cases).
Modern uses of the Modified Harvard architecture

Outside of applications where a cacheless DSP or microcontroller is required, most modern processors have a CPU cache which partitions instruction and data. Accordingly, they are hybrids of the Harvard and von Neumann models, and are best viewed as implementing a Modified Harvard Architecture. Examples include the x86 processors found in most desktop computers, and ARM cores embedded as applications processors in cell phones. MIPS, Blackfin, PowerPC, and many other processor families implement this flavor of Modified Harvard Architecture. There are also processors which are Harvard machines by the most rigorous definition (that program and data memory occupy different address spaces), and are only modified in the weak sense that there are operations to read and/or write program memory as data. For example, LPM (Load Program Memory) and SPM (Store Program Memory) instructions in the Atmel AVR implement such a modification. Similar solutions are found in other microcontrollers such as the PIC and Z8Encore!, many families of digital signal processors such as the TI C55x cores, and more. Because instruction execution is still restricted to the program address space, these processors are very unlike von Neumann machines. Having separate address spaces creates certain difficulties in programming with high-level languages such as C, which don't directly support the notion that tables of read-only data might be in a different address space than normal writable data (and thus need to be read using different instructions).[1] V d Havard CPU ARM 920T, l loi CPU ci tin vi mt nh cache cho lnh v mt cache cho d liu.
24
Hnh1.6-Havard CPU ARM 920T ca Amtel M hnh tng qut ca mt HTN: Cc khi chc nng: Mi trng hot ng: ni s dng HTN, Chp hnh: l cc thit b cng ngh, Cm bin: thit b c bit ghi nhn thng tin cng ngh (v tr, vng quay, tc , nhit , p sut, kch thc (cao, di, su) ) , Ghp ni: l cc thit b phi hp, chuyn ha cc thng tin t cm bin thnh tn hiu in s ha, Cc b s ha (A/D) v tng t ha (D/A), Ghp ni vi cc h thng khc: lin kt cc HTN khc, mng d liu, Trung tm iu khin SCADA, Ghp ni BUS h thng CPU, RAM, ROM (FLASH),
25
Hnh 1.7- M hnh tng qut HTNM hnh vi cc khi chc nng
26
Hnh 1.7- M hnh tng qut HTN-Vi cc khi ngoi vi v phn mm Kin trc tru tng: lp xp chng Khi ni v kin trc mt h thng, thng ta cp tnh tng qut v nhng chc nng c bn. Nh vy mc tng qut, cc lp phn cng v phn mm c cp nh cc thnh phn (element) hp thnh. Cc thnh phn kin trc c th hp nht bn trong thit b nhng hoc tn ti bn ngoi v tng tc vi cc thnh phn bn trong theo mt cch no . cch nhn kin trc, th kin trc c biu din bi cc cu trc. Mi cu trc bao gm mt tp hp cc thnh phn c trng, cc thuc tnh v nhng c t v mi quan h bn trong cc thnh phn . Kin trc lp xp chng c c tnh l mi lp ch s dng chc nng(hay dch v) ca tng di n, ng thi ch cho php tng trn s dng cc chc nng (dch v) ca mnh. Kin trc ny c li th v an ninh, bn vng, n gin v thit k, d nng cp (cc dch v), thc hin mi lp v kh nng nng cp nng ngay c khi h thng ang hot ng. V d nguyn l 27

ny ta thy m hnh mng chun OSI (Open Systems Interconnection), kin trc ca h iu hnh Unix/Linux. M hnh mt NTH cng c c t theo lp kin trc m bo v tin cy, n gin khi hot ng:
Hnh 1.8- Kin trc tru tng HTN - Lp phn cng: Nh Cc khi chc nng. - Lp phn mm h thng: H iu hnh hay Monitor - Lp ng dng: L mt s chng trnh ng dng xc nh m HTN thi hnh.
1.5 PHN LOI HTN Phn loi HTN c th theo nhiu tiu ch khc nhau v c th khng hon ton ging nhau (ging nh khi nu nh ngha v HTN). Tuy nhin c th nu ra y mt s tiu ch phn loi HTN. HTN hot ng u: Hot ng c lp: nhn u vo t cc tc nhn b iu khin, x l v cho u ra. Thi gian c u ra (p ng) phi trong mt khung thi gian nht nh theo khi thit k. Hot ng c lin kt vi nhau gia cc HTN v cc trung tm kim sot khc. Loi ny gi l HTN mng. V d cc HTN cc b ti cc thit b chp hnh u cui ca mt qui trnh cng ngh phc tp lin kt qua mng cc b ca nh my hay ca mt c my phc tp. H thng mng in thoi di ng l mt v d kiu HTN mng: my ngi dng <> cc trm BTS <> tng i <> tng i <> BTS <> my ngi dng. Tn chung ca HNT li ny l HTN di ng. Lnh vc ng dng: 28

Cng c tnh ton nh cc my tnh nhng ch chy cc bi ton nht nh. X l tn hiu: cc thit b video thi gian thc, DVD player, thit b y t Truyn thng, mng: thit b mng nh router, chuyn mch (switch), firewall. H thng iu khin v thu thp d liu. Kin trc v qui m: HTN qui m nh (Small Scale Embedded Systems) vi cc xc nh nh sau: Phn cng t phc tp, thit k vi CPU n, loi 4, 8 bits; Phn mm n gin, dng mt monitor kim sot hot ng; Cng c pht trin phn mm: son tho chng trnh, hp ng v hp ng cho (asembler, cross asembler), mi trng pht trin hp nht (integrated developememt enviroment) s dng vi vi iu khin hay CPU chn. Ngn ng pht trin l C, m C c dch ra nh phn ti u, nh v m thc thi trong b nh ROM, dung lng b nh gii hn. Tiu th nng lng rt t.
V d : HTN n gin, ch c mt vi phm bm a thng tin vo, mt vi n LED hin u ra (trng thi no ). V d: HTN my iu ha nhit , l nhit v.v. HTN qui m phc tp: Phn cng phc tp: Thit k vi CPU 8,16 hay32 bits, hay s dng vi iu khin; H thng c cu trc vi BUS m rng ghp ni vi cc thit b ngoi vi; Phn mm nhng tinh vi, c h iu hnh thc hin cc nhim v, thao tc ng thi. C th l loi RTOS. Cng c lp trnh: C/C++/Visual C++/Java, RTOS, m ngun, cng c ki thut: Simulator, Debugger. Mi trng pht trin hp nht (Integrated Development Envirinment-IDE. Cng c soft xy dng phn cng phc hp. V d: cc HTN trn cc my gia cng (kim loi, khun nha v.v). HTN tinh vi (Sophisticated Embedded Systems) Phn cng v phn mm rt c bit; Nhiu CPU v c th m rng, hay cc CPU c th cu hnh c (configurable CPUs), hay mng logic lp trnh c (programable logic arrayPLA); Pht trin cho cc lp ng dng mi nht khi cc ng dng loi ny cn phi c qu trnh thit k ng thi gia phn cng v phn mm, hp nht cc linh 29

kin h thng cui cng, s dng cng ngh ASIC ch to CPU, vi mch ng x l (cn gi l ChipSet hay Co-processor). V d cc h thng hng khng qun s mi nht trn cc my bay (military/civil avionic ), cc thit b mng cao cp. Cc HTN kiu ny b ch ng bi tc x l ca phn cng (CPUs), Cc chc nng phn mm nh cc gii thut m ha/gii m, gii thut chuyn i tn hiu s (Fourrier transformation), giao thc TCP/IP stack, cc hm chc nng mng nhng trong phn cng tng tc x l; Mt s chc nng phn mm c cng ha ( nh DSP). Cng c pht trin thng khng c sn v t tin, do phi pht trin ring khi d n c chp nhn. HTN phn cng hay HTN phn mm; HTN theo An ton s c (fail-safe), hay t an ton (fail-safe operational); HTN p ng c bo m hay p ng vi n lc ti a; HTN vi ngun ti nguyn y hay ngun ti nguyn hn ch; HTN phn ng ngay vi s kin hay phn ng vi s kin c thi hn. Ti sao cc HTN li c s khc nhau ? C th tr li n gin l do cc ng dng khc nhau v h thng phi hot ng hiu qu. V d: 1. HTN l dnh thc hin cc tc v ring bit. Cc tc v ring bit y phn ln lin quan ti cc x l khc nhau chuyn bit, cc s kin, cc trng thi ca mt qui trnh cng ngh, v d qui trnh iu khin my cng c, robot Khi thay i qui trnh, thng dn ti thay i hay thit k li c h thng. Nh vy c th thy cn c mt loi b x l thch hp cho li tc v nu. B x l nh vy gi l b x l chuyn bit (dedicated microprocessor), n khng mnh nh b x l a nng ta s dng trong my tnh, nh my tnh PC chng hn. V d in hnh l b x l tn hiu s DSP (Digital Signal Processor) dng TMS320 (TMS320C6000 Multicore DSPs, TMS320DM6446 DaVinci Video Processor ) ca Texas Instruments, hay cc b x l MP3 (x l d liu m thanh nn v gii m a vo khuych i m thanh ri ra loa). V d s khi chc nng ca CPU DSP:
30
Hnh 1.9- S khi CPU DSP-MP3.
Hnh 1.10- B MP3 vi CPU BlackFin ca ANALOG DEVICES 2. Nh im 1. nu trn, v phn cng, cc HTN c thit k t rt nhiu loi CPU nhng v cc CPU nhng bn thn chng li c kin trc khc nhau. Hin trn th trng c th lit k cc kiu CPU nhng nh: CPU vn nng rt gn ph hp cho ng dng nhng, cc vi iu khin (microcontroller, PIC), cc kin trc kiu h thng trn mt vi mch (PSoC-Programmable System on Chip) 3. V phn mm c s c th t n gin cho ti tinh xo, h iu hnh thi gian thc (RTOS-Real Time Operating System). 4. V d mt s HTN 31

Phn cng thng mi l cc sn phm nh bo mch HTN y , thit k hon chnh v i cng c phn mm h thng (h iu hnh, hay monitor) ci t trong EEPROM, flash, c RAM hay cn c a cng bn dn (DiskOnChip dung lng 32MB hay ln hn), vi d nh dng PC 104 di y:
32
TMZ104 PC/104 Computer with Transmeta Crusoe TM5500 CPU TMZ104 Photo Features: Low power fanless x86 compatible Embedded BIOS Linux OS Watchdog timers Dual EIDE & floppy support USB, parallel port, PS2 keyboard & Mouse Dual RS-232 serial
Hnh 1.11- Mt s HTN thng mi Cc loi vi iu khin dng bo mch Cc loi vi x l ri thit k THN theo yu cu ng dng:
CPU : Intel 80X51, PIC 12F 675, Amtel 8051, PSoC (Programmable System on Chip) : CY8C29466 c im chung ca cc loi ny l c kin trc y ch trong mt vi mch c mc tch hp c ln v rt ln (VLSI: Very large Scale Integration). Bng di y lit k s loi CPU cho HTN t cc hng khc nhau (cha y ):
33

1.6 KT CHNG Chng ny gii thiu v HTN t nh ngha, m hnh, phn loi, cc c th v kin trc ca HTN. Chng cng nu ra nhng lnh vc cng ngh m HTN c s dng. T cng bt ra nhng yu cu k thut trn HTN ni chung v HTN cho ng dng ring bit.
Tham kho mt s nh ngha HTN t cc ngun ti liu: HTN l mt h thng c phn cng c xy dng trn nn tng phn cng my tnh chuyn bit vi phn mm c nhng trong phn cng , nh mt trong cc thnh phn quan trng nht ca HTN. HTN do c th l mt h c lp hay l mt phn ca mt h thng ln hn. Mt s nh ngha v HTN: Wayne Wolf: what is an embedded computing system ? Loosly defined, it is any device that includes a programmable computer but is not itself intended to be general-purpose computer [Computers as Components Principal of Embedded Computer System Design]. Told D. Morton: Embedded Systems are electronic systems that contain a microprocessor or microcontroller, but we do not think od them as computers the computer is hidden or embedded in the system [Embedded Microcontrollers] Tim Wilmshurst: Embedded system is a system whose primcipal function is not computational, but which is controlled by a computer embedded within it. The computer is liklly to be a microprocessor or micro controller. The word embedded implies that it lies inside the overal system, hidden from view, forming an integral part of greater whole [ An Introduction to the Design of Small Scale Embedded System with PIC, 80c51 and 68HC05/08 Microcontroller] 1.7 CU HI CUI CHNG 1) 2) 3) 4) 5) 6) nh ngha tng i v HTN. Nhng thch thc no phi i mt khi thit k mt HTN ? Nhng cch nu m hnh kin trc ca mt HTN ? Th no l HTN kiu vi x l HTN kiu vi iu khin ? Nu cc khi chc nng trong hnh 1.7 m t v m hnh mt HTN. C bao nhiu loi kin trc CPU c s dng khi xy dng HTN ? Mi loi khc nhau im no ch yu ? 7) Nu cc thnh phn phn cng thng c trong mt HTN ? 8) Cc thnh phn nh bin i tng t-s (ADC), s-tng t (DAC), nh thi (timer), cng (port) nht thit cn c trn mt HTN ? Ti sao ? 9) C cc loi phn mm no trn mt HTN ? 34
Chng 2: Cc thnh phn phn cng ca h thng nhng
CHNG 2 CC THNH PHN PHN CNG CA H THNG NHNG

Chng 2 cp ti cc thnh phn phn cng, nn tng c s ca HTN. Bao gm: b x l trung tm (CPU) vi kin trc Von Neumman v kin trc Harvard, BUS ca CPU v BUS h thng, b nh, cng. Tip theo l k thut ghp ni cc thit b ngoi vi vo vi CPU, cc chng trnh iu khin ghp ni. i vi CPU, ti liu nu nguyn l kin trc, cc c tnh k thut v biu thi gian hot ng ca CPU, gip cho vic thit k phn cng sau ny. Ring v tp lnh khng cp ti, do vy khi s dng mt CPU no cn nm c tp lnh ca CPU c th lp trnh, vit cc trnh iu khn bng hp ng. Chng cung cp cc kin thc phn cng v k nng thit k, c bit l thit k ghp ni vi thit b Cui chng l mt s bi tp thit k n gin nh thit k b nh ROM, RAM, cng vi CPU, to thnh mt bo mch nh mt HTN cha c cc thit b ngoi. 2.1 B X L TRUNG TM (Central Processing Unit-CPU) Cc h thng s dng k thut tnh ton s x l thng tin u cn mt t hp cc mch s to ra mt h thng c kh nng: thc hin cc php tnh l lun l (logic), cc php ton s hc, cc quyt nh chuyn hng thc hin c hay khng c iu kin v quan trng l hot ng theo mt h m vi lnh (micro-instruction code) theo mt trnh t nht nh. tng to ra mt h thng in t s nh vy chnh l to ra mt b x l trung tm. B x l trung tm ngy nay rt tinh xo, kch thc rt nh ( ch ln hn 1 cm ) nhng cha vi triu transistor, hot ng vi tn s t vi MHz ti vi GHz, cng sut tiu tn t vi Watt ti vi chc Watt ,v d: Intel Pentium G6950 cng ngh: Clarkdale (32 nm), tn s: 2.8 GHz, Power dissipation :73 W . (Theo: http://en.wikipedia.org/wiki/List_of_CPU_power_dissipation#Intel_Pentium_DualCore). i li tc tnh ton t hn 1 t lnh my trong mt giy (MIPS: milions Instruction per second). V d: Intel Core i7 Extreme Edition i980EE :147.600 MIPS at 3,3 GHz , 44.7 lnhmy/ chu k xung ng h(vi f=3,3GHz, Tchuk=0,303 ns). (Theo: http://en.wikipedia.org/wiki/Instructions_per_second). y l ni ti cc b x l vn nng, dng ch to cc my tnh ( bn, my ch). i vi cc CPU dng trong thit k cc HTN, tn s lm vic ca CPU c thp hn, c vi chc MHz. Ti sao vy ? n gin khng phi lc no cng cn tc tnh ton tht nhanh, v cn ty vo ng dng nhng l g. Tt nhin cng nhanh cng tt, nhng i li gi thnh cao, mi trng hot ng khng th tha mn (v d nhit mi trng cao, bi, rung ng c hc ). 35

2.1.1 Cc loi CPU v nguyn l hot ng Hin nay trn th trng rt nhiu nh sn xut CPU vi nhiu chng loi ph hp cho cc ng dng. C th lit k mt s nt phn bit: a) Cch t chc v thc hin lnh my: - Vi tp lnh y (CICS). - Vi tp lnh rt gn (RISC). b) Cch x l thng tin v truy nhp b nh: - Von Neumman: b nh chung, truy cp tun t theo tng lnh my. - Harvard: b nh lnh v b nh d liu c lp, truy cp ng thi. c) Cng ngh ch to hng ng dng: - CPU a nng: ch to my tnh a nng - CPU chuyn dng: cc ng dng c th ( nh cho ng dng nhng). Trong phm tr ny li c mt vi cng ngh tiu biu: Vi iu khin (microcontroller v PIC-Programmable Intelligent Computer" (My tnh kh trnh thng minh)) H thng trong mt vi mch lp trnh c (PSoC- Programmable System on Chip: integrating configurable analog and digital peripheral functions, memory and a microcontroller on a single chip). Lp cng ngh ny c s dng ph bin trong cc HTN. 2.1.2 V d v mt CPU v nguyn l hot ng c th thc hin thit k mt HTN, cn tm hiu chi tit v cu trc, cch lm vic v lp trnh cho mt CPU chn. Phn ny gii thiu dng Intel CPU 808X, 8 bits hay 16 bits, a nng, c lp ca Intel c s dng rt ph bin trn th gii cng nh Vit Nam. u im ni bt ca CPU ny l tnh ph bin, a nng, d trin khai, cng c pht trin rt a dng v sn c. a) S hnh thc bn ngoi:
Hnh 2.1-Intel CPU 8085

36

b) Kin trc: M hnh chc nng bn trong CPU, v d Intel 8080/8085
8085 l 8-bit microprocessor, trong d liu x l l 8 bits, khng gian a ch c xc nh bi 16 bits, cho dung lng a ch l 65.535 (gi l 64K) nh. Cc thnh phn chc nng bao gm: Tp cc thanh ghi (Register). n v thc thi cc php tnh s hc v lun l (Arithmetic logic unit- ALU). H thng cc dy ni gia cc vi mch chc nng( BUS). Khi nh thi v iu khin (Timing & Control unit).
Hnh 2.2-Cc khi chc nng ca CPU 8080/8085 1) Tp cc thanh ghi (Registers): Cc thanhg ghi s dng cha d liu v a ch. Co hai loi thanh ghi: Thanh ghi a nng c dng nh chc nng nh d liu tm thi hay ch tc thi qui chiu ti b nh (ROM/RAM). Cc thanh ghi 8 bits l B, C, D, E, H v L. Khi ghp li s thnh thanh ghi 16 bits vi tn kp: BC, DE or HL. Thanh ghi c bit l cc thanh ghi gn cho chc nng c bit (hay chuyn dng): 37

Thanh ghi tch ly (Accumulator (A)): 8 bit dng cha d liu, ton hng, kt qu php ton khi thc hin lnh. - Thanh m a ch chng trnh (Program counter (PC)): 16 bit cha a ch ca lnh my tip theo s c th hin. - Thanh ghi ch s (Index register): c dng lm ch s cho qui chiu a ch, cch dng ph thuc vo ch a ch ha. - Thanh ghi trng thi (Status register): ghi li trng thi cua CPU sau khi thc hin mi lnh s hc, logic gm: carry, auxiliary carry, sign, zero and odd/even parity. - Thanh ghi ngn xp (Stack pointer): 16 bit s dng qui chiu vo vng nh ngn xp. - Thanh ghi lnh my (Instruction register): 8 bit cha m lnh (OPCODE) t ROM/RAM, u vo cho khi Timing&Control gii m thnh cc tn hiu iu khin ca CPU. 2) n v thc thi cc php tnh s hc v lun l (ALU): Thc hin cc php tnh: Cng, tr, nhn, chia, logis AND, OR, XOR, NOT, dch tri/phi, quay vng tri/phi. 3) H thng cc dy ni gia CPU vi cc vi mch chc nng, thit b ngoi (BUS) (Hnh 1.1.1- M hnh tng qut bo mch ch) Tp hp cc tn hiu pht ra t CPU v ni ti cc vi mch chc nng trn bo mch chnh. m t ngha ca tng tn hiu ta nhm li theo chc nng nh sau: a) BUS a ch (Address bus): Mang thng tin v da ch qui chiu ti ROM/RAM, b gii m chn vi mch. Vi CPU 8080/8085 c tt c 16 ng hay 16 bit. BUS ny ch c mt hng (chiu) i ra t CPU. b) BUS d liu (Data bus) : D liu trao i gia CPU v cc vi mch bn ngoi, cc thit b ngoi s dng BUS ny. Ty loi CPU c th l 8 bit, 16 bit, 32 bit, 64 bit. S bit ny thng dng ni ti loi CPU. c im c bn ca BUS l hai chiu. c) BUS iu khin (Control bus): Cc tn hiu iu khin pht ra t CPU ti cc vi mch chc nng khc nhau trn bo mch ch, cc thit b ngoi ni vi CPU. Cc tn hiu ny c dng ng b mi bc hot ng ca my tnh. 4) nh thi v iu khin: Khi ny to ra tt c cc tn hiu ng h, cc tn hiu iu khin bn trong CPU, CPU vi bn ngoi qua Bus iu khin (Control bus). c) B nh (Memory) Chng trnh ng dng, h iu hnh, d liu, ngn xp u dng chung khng gian nh. Vi h 8080/8085 c 16 dy a ch (A15 ... A0) cho dung lng nh ti a l 65.535 a ch nh. Nu mi nh l 1 byte s c 65.535 byte hay 64 KB. Kin trc s dng 64 bytes u tin (000F-0000) t cc vector ngt ca cc lnh RST. d) Ngt (Interrupts) 38 -

CPU 8085 c 5 u vo tn hiu ngt (interrupt), trnh by theo th t u tin t thp n cao: INTR, che c. Khi c ngt xut hin, CPU s tm lnh trn BUS, lnh c th l trong cc lnh RESTART (u c hiu lc khi ng li CPU) loi RST (RST 5.5, RST 6.5, RST 7.5 v TRAP). CPU bo lu gi tr ca PC vo ngn xp, chuyn ti nh c gi tr N*8, trong N c gi tr t 0 n 7 m lnh RST cung cp. nh ny cha a ch ca chng trnh x l cho ngt nh sau: Tn ca ngt a ch chng trnh khi ng ti: TRAP 24 Hex RST 5.5 2C Hex RST 6.5 34 Hex RST 7.5 3C Hex (u tin cao nht, tc dng sn ln ca xung ngt) Lnh gi CALL (lnh c 3 byte ). CPU gi mt chu trnh con c a ch xc nh byte th 2 v th 3 ca lnh ny. RST5.5, che c. Khi c ngt ny, CPU bo lu gi tr ca PC vo ngn xp, nhy ti a ch c nh 002Ch (h-hexadecimal). RST6.5, che c. Khi c ngt ny, CPU bo lu gi tr ca PC vo ngn xp, nhy ti a ch c nh 0034h. RST7.5 che c. Khi c ngt ny, CPU bo lu gi tr ca PC vo ngn xp, nhy ti a ch c nh 003Ch. Trap, khng che. Khi c ngt ny, CPU bo lu gi tr ca PC vo ngn xp, nhy ti a ch c nh 0024h. Tt c cc ngt che c c th lp khng che hay che lp trnh qua lnh EI v DI. RST 5.5, RST6.5 v RST7.5 lp trnh bng lnh SIM. e) Cng vo/ra (I/O ports) H 8080/8085 c tt c 256 cng vo v 256 cng ra chy theo lnh IN hay OUT. f) Thanh ghi (Registers) ACC (Accumulator) hay A, l thanh ghi 8-bit, a dng cho cc thao tc v cc php tnh s hc, lun l, I/O, np/ nh d liu. C (Flag), l thanh ghi 8-bit, cha cc bit c ngha sau: Sign, ln 1 nu bit ln nht ca kt qu php tnh c gi tr = 1. Zero, lp gi tr = 0, nu kt qu php tnh = 0. Auxiliary carry, vi php tnh 4 bit (D3-D0), ln 1 nu kt qu php tnh c s mang t D4 chuyn sang D4. Parity, ln 1 nu s parity (l tng ca cc bit trong kt qu) l s chn. Carry, ln 1 nu c s mang khi thc hin php cng s hc hay borrow khi thc hin php tr s hc hay php so snh gi tr. Thanh ghi a nng (General registers ) 8-bit B v 8-bit C hay kt hp thnh cp 16-bit. 39

8-bit D v 8-bit E hay kt hp thnh cp 16-bit. 8-bit H v 8-bit L hay kt hp thnh cp 16-bit. Cc thanh ghi ny dng c lp hay kt hp cha d liu hay a ch qui chiu vo b nh (ch da ch ha gin tip qua thanh ghi). Con tr ngn xp (Stack pointer), 16 bit. Thanh ghi ny mi ln tng hay gim 2 (+/2). Thanh m chng trnh (Program counter), 16-bit, tr trc tip vo b nh ni cha m lnh ca mi lnh. g) Tp lnh (Instruction Set) Tp lnh ca CPU Intel 8085 gm cc nhm sau y: - Lnh chuyn d liu. - Lnh s hc cng, tr, tng, gim. - Logic - AND, OR, XOR v quay vng. - Chuyn iu khin i c/khng iu kin, gi chu trnh, tr v ch c khi thot khi chu trnh, khi ng li. - Lnh vo/ra (I/O). - Cc lnh thao tc bit, c, cho php/khng cho php ngt, ngn xp, h) Ch a ch (Addressing modes) - Kiu thanh ghi: qui chiu d liu trong 1 thanh ghi hay i thanh ghi. - Gin tip qua thanh ghi: Thanh ghi cha a ch o nh ni c d liu. Qui chiu trc tip D liu 8 hay 16 bit. i) Cc nhm tn hiu trong CPU 8080/8085 A8 A15. Nhm tn hiu ra: 8 bit cao ca a ch, cc chn ny l cc chn c ni vi bn ngoi qua mch 3 trng thi. Cc phn t 3 trng thi s c t trng thi trng thi tr khng cao (cn gi l trng thi khng kt ni) trong cc trng hp mt trong cc tn hiu HOLD hay HALT l tch cc. AD0 AD7. Nhm tn hiu dn knh cho cc tn hiu a ch v tn hiu d liu theo chia s thi gian, 3 trng thi. giai on u ca chu k my, T1 ca M1, s l byte thp ca 16 bit a ch t A0 n A7. ALE (Address Latch Enable). Tn hiu ra qua mch 3 trng thi. c s dng cht byte thp ca tn hiu a ch (A0 A7) t nhm AD0-AD7. Tn hiu ny c to ra trong giai on u tin ca chu k my, T1 ca M1, v cng c dng cht cc tn hiu trng thi S0 v S1 khi cn thit. S0, S1 (Data BUS Status). L cc tn hiu ch trng thi ca cc chn thuc BUS d liu trong mi chu k my. T hp ca hai tn hiu ny cng cho bit trng thi ca CPU nh sau: S1 S0 Trng thi hot ng ca BUS d liu 0 0 Trng thi HALT
40

0 1 1 1 0 1 CPU ang thc hin thao tc WRITE CPU ang thc hin thao tc c (READ) CPU ang thc hin thao tc nhn lnh (Instruction Fetch)
RD (Read). Chn ra 3 trng thi. Nm trong nhm tn hiu iu khin. Tn hiu tch cc khi CPU tin hnh c d liu t b nh hoc t thit b ngoi vi. Trong ch HALT hoc DMA, chn ra ny trng thi trng thi tr khng cao. WR (Write). Chn ra 3 trng thi. Nm trong nhm tn hiu iu khin. Tn hiu tch cc khi CPU tin hnh ghi d liu vo b nh hoc a d liu ra thit b ngoi vi. Trong cc ch HALT hoc DMA, chn ra ny trng thi trng thi tr khng cao. IO/M. Trng thi logic ca u ra ny cho bit CPU ang lm vic vi thit b ngoi vi hay vi b nh. Nu l logic 1, CPU ang truy cp thit b vo/ra, cn nu l 0, CPU ang truy cp b nh. Kt hp vi hai u ra RD v WR to ra cc tn hiu I/OR, I/OW, MEMR, v MEMW trong trng hp s dng a ch tch bit i vi thit b vo/ra. Nm trong nhm tn hiu iu khin, IO/M cng l u ra 3 trng thi. Interrupts. P8085 c ngt a mc. C 5 chn ngt tt c: (INTR, RST5.5, RST6.5, RST7.5 v TRAP). Ngoi chn ngt khng che c l TRAP, cc chn khc u c th che hoc khng che nh lp trnh phn mm. INTR: Chn nhn yu cu ngt t bn ngoi, c p ng theo nguyn tc quay vng (polling) hoc vector thng qua lnh RST Cc yu cu ngt RST: C 3 u vo yu cu ngt vi cc mc u tin khc nhau l RST7.5, RST6.5 v RST5.5. Khi yu cu ngt xut hin ti cc chn ny, CPU t ng chuyn n cc vector ngt tng ng. C th nh sau: RST5.5 l mc u tin thp nht, phn ng theo mc in p trn chn yu cu ngt, a ch vector ngt ny nm nh c a ch 2CH. RST6.5: Ngt u tin thp th 2, phn ng theo mc in p trn chn yu cu ngt, a ch vector ngt ny nm nh 34H RST7.5: Mc u tin cao nht. Phn ng theo sn ln ca xung yu cu ngt. Sn ln ca xung ny tc ng ln mt Flip-Flop, mch ny gi li yu cu ngt cho n khi c xo nh tn hiu p ng nhn bit yu cu ngt (Acknowledge). a ch ca vector ngt ny nm nh 3CH - TRAP: L chn nhn yu cu ngt khng che c (d nhin l n c mc u tin cao nht). a ch ca vector ngt ny nh 24H. INTA. Tn hiu ra nhn bit yu cu ngt ti chn INTR. Cc yu cu ngt RST5.5, RST6.5, RST7.5 v TRAP khng tc ng n INTA. HOLD. Trng thi logic 1 chn ny l yu cu ca thao tc DMA. Cc u ra RD, WR, IO/M v ALE s c a v trng thi tr khng ra cao. 41

HLDA. Tn hiu nhn bit yu cu HOLD. RESET IN. Logic thp 0 u vo ca chn ny yu cu ti khi ng h vi x l. Do tc ng ca tn hiu RESET IN tch cc, gi tr ca thanh m chng trnh PC s c np li l 0000h. Cc mt n ngt v tn hiu HLDA cng c ti thit lp v gi tr mc nh. RESET OUT. u ra nhn bit h vi x l c ti khi ng. Dng tn hiu ny ti khi ng ton b h thng. READY. Logic 1 u vo ny thng bo trng thi sn sng cung cp d liu cho CPU hoc nhn d liu t CPU ca cc thit b ngoi vi. SID (Serial Input Data). L cng vo ca d liu ni tip ca h Vi x l. Bit hin din ti cng ny c c vo CPU nh lnh RIM, bit s c a vo bit cao ca Acc (MSB). SOD (Serial Output Data). Bit cao (MSB) ca Acc c truyn ra ngoi chn ny khi s dng lnh SIM. X1, X2. Li ni thch anh hoc mt mch dao ng to xung nhp cho CPU. C th s dng thch anh c tn s dao ng trong khong t 0.5 n 3MHz. CLK. u ra ca xung nhp, c th lm xung nhp cho cc thnh phn chc nng khc trong h vi x l. Vcc, Vss. Li ni ngun +5V v GND cho CPU 8085. Cng cn nhc li rng, CPU 8085 ch cn mt ngun nui duy nht l +5V, kh nng cung cp dng ca ngun cn c thit k tu theo nhu cu ca ton h vi x l. j) Biu thi gian (system timing) Khi thit k phn cng ca mt HTN ni ring hay mt thit b k thut s ni chung, khi nim v biu thi gian l ht sc quan trng. Nm bt c ngha ca biu thi gian s c ch khi tin hnh hiu chnh v tm li phn cng. Li phn cng thng xy ra khi cc tn hiu hot ng khng ng thi im u vo mch s, gy ra li, t bit hay xy ra cc mch t hp. Di y l mt s nh ngha cc b x l: Trng thi my: T (machine State): c nh ngha l thi gian ca mt chu k xung ng h h thng (CPU Clock-out). V du nu Clock-out=10 Mhz, th T=200ns. Cc sn xung ln/xung c s dng bn trong CPU cho cc thao tc khc nhau. Chu k my (hay chu k BUS): M (machine cycle): L tp hp ca mt s cc T CPU hay mt vi mch ( nh DMAC 8237) khi nm quyn kim sot BUS h thng, thc hin xong mt thao tc (mt phn ca qu trnh gi ra hay c vo mt d liu) trn BUS h thng. Chu k lnh: (Instrution cycle): l tp cc M cn thit hon thnh mt lnh my.
42

Hnh sau y m t thc thi ca lnh STA cua CPU Intel 8085: Ct ni dung trong thanh ghi ACC ca CPU v nh tr trc tip bi 2 byte tip theo ca lnh: ([byte 3], [byte 2]) <- ACC. V d: c php hp ng nh sau: STA 0610h, gi nh trong ACC c mt gi tr no , ta s ct (STore) gi tr vo nh 1006: Trong STA=00110010: OPCODE a ch thp ca nh RAM: 00000110 a ch cao ca nh RAM: 00010000 Biu thi gian thc hin nh sau:
Chu k lnh M1 M2 M3 M4
T1
CPU Clock-CLK Kiu chu ki my BUS a ch BUS D liu
T2
T3
T4
T1
T2
T3
T1
T2
T3
T1
T2
T3
c b nh PC tr ti byte u tin l m lnh (OPCODE) ca lnh

OPCODE
c b nh PC=PC+1, tr ti bute th 2 ca lnh Byte thp ca a ch trc tip
c b nh PC=PC+2, tr ti byte th 3 ca lnh Byte cao ca a ch trc tip
Ghi b nh Pht a ch ly M2 va M3 tr ti b nh Ghi ni dung ca ACC vo nh
Mi: Chu k my , Ti: trng thi my V d thc hin lnh c di 3 byte, ct ni dung ca ACC vo nh tr bi a ch trong lnh: STA [ a-ch-thp, a-ch-cao]
Hnh 2.3-Cc khi nin qui chiu theo CPU Clock Ta c th theo di cc xung in ny khi s dng my hin sng (OSCILOSCOPE) vi t nht 2 tia cp vo v tr thch hp trn bo mch, ly xung ng h CPU CLK lm chun ng b cc tn hiu. Vic thc hin mt lnh trong CPU P8085 thc t l mt chui cc thao tc READ v WRITE. Mi thao tc READ hay WRITE tng ng vi mt chu k my M. Mi lnh c thc hin qua 1 n 5 chu k my. Mi chu k my cn t 3 n 5 nhp ng h. V d lnh STA ni trn c 5 chu k my, 13 trng thi my. Sau y l m t hot ng ca CPU 8085 vi cc chu k ng h h thng v cc thao tc khc. chu k my th nht, CPU thc hin np m lnh (Instruction Code Fetch) trong RAM, cn gi l chu k Opcode Fetch. Hnh di cho thy rng vic thc hin chu k my M1 (Opcode 43

Fetch), CPU gi ra cc tn hiu IO/M, S1 v S0 (tng ng 0, 1, 1 trn biu thi gian) xc nh thao tc ca chu k.
Hnh 2.4-Lu thi gian c s ca CPU 8085 (Theo ti liu ca hng Intel) CPU cng ng thi gi 16 bit a ch ra chu k my u tin, ngay t nhp u tin (T1) xc nh nh hay thit b I/O. Phn a ch byte thp t trn AD7-AD0 (Program Counter Low byte-PCL) ch tn ti trong thi gian 1 nhp nn cn phi c cht li nh tn hiu ALE mc cao. Cn phn a ch byte cao t trn A16-A8. Khi D7 D0 n nh trn cc dy d liu, CPU gi tn hiu RD. Khi nhn c d liu, RD chuyn ln mc cao cm v tr nh hay thit b I/O. S lng chu k my v trng thi cn cho thc hin mt lnh l c nh, song s lng ny khc nhau i vi cc lnh khc nhau, tu theo di ca t lnh (1 byte, 2 bytes, 3 bytes). S lng chu k my ph thuc vo s ln CPU phi lin lc vi cc phn t khc trong h thng, ch yu l vi cc chip khc.
44
Hnh 2.5-Biu thi gian ca chu k tm lnh. 2.2 CPU 8085 V H THNG BUS Vic u tin trong thit k mt HTN l la chn CPU v hnh thnh BUS h thng trc khi m rng vi cc thnh phn khc nh ROM, RAM v cc cng ghp ni. Tip tc vi t duy s dng h Intel 808X, ta s thit k h thng BUS nh sau: c im ca cc chn/tn hiu pht ra t CPU: Nh trn lit k, CPU a ra 3 tp hp tn hiu chnh, bao gm: - Tp tn hiu a ch trn cc chn AD7 AD0 v A8 A15, trong AD7 AD0 l cc chn 2 chc nng : Lc (M1, T1) l a ch phn thp, sau l d liu. Do to ra 16 ng a ch ta cn cht cc gi tr ny li vi h tr ca tn hiu ALE (Address Latch Enable) vi vi mch SN74373. Tp hp ny to thnh BUS a ch . - Tp cc chn d liu AD7 AD0 cc chu ki M/T tip theo ca chu k lnh. Tp hp ny to thnh BUS d liu. BUS d liu c rng khc nhau theo loi CPU, c th l 4, 8, 16, 32, 64, hay trn mt loi BUS c bit chung ghp ni vo vi mch ng x l (ChipSet), gi l BUS pha trc (Front Side Bus-FSB) cc mt PC hin i, rng co th ln 128, 256 hat 1024 bit. - Tp cc tn hiu iu khin pht ra t CPU, l BUS iu khin. 45

Do cn ghp ni vi cc thit b bn ngoi, cn mt BUS khc gi l BUS h thng m rng, v du: ISA, EISA, v ph bin l PCI. Cc BUS ny cn c nh ngha tng minh v c giao thc hot ng rt phc tp.
ng h thch anh nhp chun
A15 A8 ALE
A15 A8 L STB A7 a t A0 c h D7 D0 DATA BUS Address BUS A7 A0
CPU 8085
AD7 AD0 RD/ WR IO/M INTA
Control BUS
Ngun nui mt chiu
Hnh 2.6- Cu hnh ti thiu: CPU 8085 v to BUS h thng Do chc nng ca BUS l truyn thng tin gia cc thnh phn hp thnh ca my tnh v do c vai tr rt quan trng nh hng ti hiu nng ca my tnh, nn i khi phi xem xt ti mt khi nim v thng lng ca BUS (nh bt k loi thit b truyn thng tin no). l gi tr v lng d liu ti a c chuyn qua BUS trong mt khon thi gian no , thng thng qui theo CPU clock (hay chu k lnh): Tc BUS (MHz) x s byte mt ln truyn Tc truyn ti a = S chu k Clock cho mt ln truyn 2.2.1 Khi nim v bn cht vt l ca cc BUS Hot ng ca mt h k thut s thc cht l vic trao i v x l cc gi tr nh phn gia cc thnh phn, cc khi v cc mch vi in t trong ton b h thng. Nh bit, cc gi tr nh phn (hoc 0 hoc 1) c th hin qua mc in p so vi mt chun nht nh, v d chun TTL(transistor-transistor logic) gi tr 0 tng ng vi mc in p thp (t 0V n +0,8V) v 46

gi tr 1 tng ng vi mc in p t khong +3V n +5V. biu din mt s liu nh phn, cc phn t mang thng tin c lin kt k nhau theo nhm (v d 1byte l 8 bits). m nhn cng vic di chuyn cc d liu ny trong ton b h thng, c cc ng dy truyn dn in c ghp song song thnh h thng, mi dy truyn dn dnh ring cho 1 bit. Tp cc ng truyn dn dnh ring cho cc tn hiu c cng chc nng (d liu, a ch, iu khin v trng s (2n)) c gi l BUS. BUS gii quyt mt vn k thut c s quan trng l: ni c hai u ra ca hai mch in t khc nhau m khng lm cho u ra no b hng. Yu t c bn y l cc u ra phi c iu khin bng chng trnh my tnh a u ra ca vi mch vo mt trong hai ch lm vic c bit (hay gi l trng thi) sau: hot ng bnh thng, ti nng lng ln dy kt ni v trng thi khng hot ng v c tr khng u ra cao (Tri-state) khng on mch u ra ca vi mch kia. Lm c nh vy tn hiu s i c c hai chiu trn cng mt dy ni. V h qu l gim i mt na cc chn ni ra/vo ca vi mch s. Nh vy, trong mt h my tnh BUS c mt s tiu ch sau y: - BUS phi tun theo 1 chun no . Tp cc quy tc ca chun cn c gi l giao thc bus (bus protocol) - C th c nhiu loi bus khc nhau c s dng, cc bus ny ni chung l khng tng thch vi nhau. - Bus thng phn loi theo 3 cch sau: Theo t chc phn cng Theo giao thc truyn thng ( bus ng b v khng ng b) Theo loi tn hiu truyn trn bus : BUS d liu, l BUS hai chiu, c trng thi tr khng cao. BUS a ch: l BUS mt chiu v thng thng a ch pht sinh ra t CPU. Tuy nhin phi c kh nng trng thi tr khng cao khi cn thit. BUS iu khin, cc tn hiu iu khin t CPU hay vi mch chc nng khc.. Cc BUS ny hp li thnh BUS ca CPU. BUS ca CPU thng c ti u ra yu, nn BUS ny c khuych i, cn c CPU Clock_out (hay BUS Clock) to thnh BUS h thng. S khc nhau l ch: BUS ca CPU: i ra trc tip t CPU BUS dn knh BUS h thng: Khng ni trc tip vo CPU, m qua khuych i BUS Khng cn dn knh, cc BUS tch bit Ph ti ln hn 47

C BUS Clock trn BUS
Hnh 2.7-CPU Bus v BUS h thng T khi nim trn, d dng suy ra bn cht vt l ca cc BUS trong mt h my tnh: l cc ng truyn dn in, c th di cc dng cp nhiu si, ng dn trong cc bng mch in v.v Kh nng v cht lng dn in ca cc ng truyn dn ny ng vai tr quan trng v quyt nh i vi hot ng ca mt h my tnh. ng truyn dn km, in tr thun cao c th gy ra s suy gim ca tn hiu in dn n cc hin tng mt hoc sai d liu. BUS l ng dn in ni b m theo cc tn hiu c truyn t b phn ny n cc b phn khc trong h my tnh. 2.2.2 Khuych i BUS (bus driver) Tn hiu pht sinh t CPU thng c cng sut thp ch cho mt s ti danh nh (fanout), khng m rng BUS, nht l khi bus kh di v c nhiu thit b ni vi n. Chnh v th m hu ht cc BUS c ni mt s vi mch khuych bus (bus driver), v c bn l cc vi mch khuych i tn hiu s. Hu ht vi mch khc ni vi BUS qua vi mch u vo (bus receiver). i vi cc thit b khi th ng vai tr a tn hiu ln BUS (master), khi th ng vai tr nhn tn hiu t BUS (slave), ngi ta s dng mt vi mch kt hp c kh nng pht ra v nhn v, gi l vi mch pht v thu tn hiu (bus transceiver). Cc chip ny ng vai tr ghp ni v l thit b 3 trng thi, cho php n c th trng thi th 3 tr khng cao. Cc vn quan trng nht lin quan n thit k bus l: xung ng h bus (clock bus: s phn chia theo thi gian, hay cn gi l bus blocking), c ch trng ti bus (bus arbitration), x l ngt v x l li. 48

Cc bus c th c chia theo giao thc truyn thng thnh hai loi ring bit l bus ng b v bus khng ng b ph thuc vo vic s dng clock bus. 2.2.3 Bus ng b (Synchronous bus): Bus ng b c mt tn hiu trn ng dy BUS clock dng sng vung, vi tn s v d, trong khong vi MHz GHz. Mi hot ng bus xy ra u qui chiu vo BUS Clock, trong mt s nguyn ln chu k ny v c gi l chu k bus. Hnh sau gin thi gian ca mt bus ng b vi tn s xung BUS clock l 4MHz, nh vy chu k bus l 250ns. Gi s c 1 byte t b nh chim 3 chu k bus (750 ns), tng ng vi T1, T2, T3 nh hnh v. V tt c cc bng bn dn khi chuyn mc khng phi l tc thi, m c qu v mt mt khon thi gian, nn trn hnh v c cc sn xung, ta gi s cc sn xung ko di 10ns. Con s ny rt quan trng khi thit k mch k thut s !
Hnh2.8-Chu k c ng b T1 bt u bng cnh dng ca xung clock, trong mt phn thi gian ca T1, vi x l t a ch byte cn c ln bus a ch. Sau khi tn hiu a ch c xc lp, vi x l t cc tn hiu MREQ v RD tch cc mc thp, tn hiu MREQ (Memory Request) - xc nh truy xut b nh ch khng phi thit b I/O, cn tn hiu RD - chn c ch khng phi ghi d liu. T2: thi gian cn thit b nh gii m a ch v a d liu ln bus d liu. T3: ti cnh m ca T3, vi x l nhn d liu trn bus d liu, cha vo thanh ghi bn trong vi x l v cht d liu. Sau vi x l o cc tn hiu MREQ v RD. Nh vy thao tc c hon thnh, ti chu k my tip theo vi x l c th thc hin thao tc khc. Cc gi tr c th v thi gian ca hnh v trn c th c gii thch chi tit nh sau:
49

TAD: TAD <110ns, ngha l nh sn xut vi x l m bo rng trong mi chu k c ton hng t b nh, vi x l s a ra tn hiu a ch khng nhiu hn 110 ns tnh t thi im cnh dng ca T1. TDS: gi tr nh nht l 50ns, c ngha l nh sn xut b nh phi m bo rng d liu n nh trn bus d liu t nht l 50ns trc im gia cnh m ca T3. Yu cu ny m bo cho vi x l c d liu tin cy. Khong thi gian bt buc i vi TAD v TDS xc nh rng trong trng hp xu nht, b nh ch c 250 + 250 + 125 110 50 = 465 ns tnh t thi im c tn hiu a ch cho ti khi to ra d liu trn bus d liu. Nu b nh khng c kh nng p ng nhanh, n pht tn hiu WAIT trc cnh m ca T2. Thao tc ny a thm cc trng thi ch wait state (tc l a thm vo 1 chu k bus), khi b nh a ra tn hiu n nh, n s o WAIT thnh WAIT TML: m bo tn hiu a ch s c xc lp trc tn hiu MREQ t nht 60ns. Khong thi gian ny s quan trng nu tn hiu MREQ iu khin qu trnh to tn hiu chon chip CS hay CE do mt s chip nh i hi phi nhn c tn hiu a ch trc tn hiu chn chip. Nh vy, khng th chn chip nh vi thi gian thit lp 75ns. TM, TRL cho php hai tn hiu MREQ v RD tch cc trong khong thi gian 85ns tnh t thi im xung ca xung clock T1. Trong trng hp xu nht, chp nh ch c 250 + 250 85 50 = 365ns sau khi 2 tn hiu trn tch cc a d liu ra bus d liu. S bt buc v thi gian ny b sung thm s bt buc thi gian vi tn hiu clock. TMH, TRH : thi gian cc tn hiu MREQ v RD c o sau khi d liu c vi x l nhn vo. TDH: Thi gian b nh cn gi d liu trn bus sau khi tn hiu RD o. Gin thi gian mt chu k c trn bus ng b c n gin ho so vi thc t, trong cc tn hiu cn s dng ln hn nhiu. Gi tr ti hn ca cc thng s cho trong bng sau: K hiu TAD TML Tham s Thi gian tr ca a ch Thi gian a ch n nh trc MREQ b Thi gian tr ca MREQ so vi cnh m ca T1 Thi gian tr ca RD b so sn xung ca tn hiu ng b T1 60 Min (ns) Max (ns) 100
TM
85
TRL
85
50
TDS
Thi gian thit lp d liu trc sn xung ca tn hiu xung clock( tn hiu ng h) Thi gian tr ca MREQ b so vi sn xung ca tn hiu ng h T3 Thi gian tr ca RD b so vi sn xung ca tn hiu ng h T3 Thi gian lu tr d liu t lc o tn hiu RD b
50
TMH
85
TRH
85
TDH
Truyn theo khi: Ngoi cc chu k c/ghi, mt s bus truyn d liu ng b cn h tr truyn d liu theo khi. Khi bt u thao tc c khi, vi mch lm ch bus (bus master) bo cho vi mch khc (slave) bit s byte cn c truyn i, th d truyn con s ny i trong chu k T1, sau ng l truyn i 1 byte, slave a ra trong mi chu k 1 byte cho ti khi s byte c thng bo. Nh vy, khi c d liu theo khi, n byte d liu cn n+2 chu k clock ch khng phi 3n chu k. Mt cch khc cho truyn d liu nhanh hn l gim chu k. v d trn: 1 byte c truyn i trong 750ns, vy bus c tc truyn 1.33MBps. Nu xung clock c tn s 8MHz, thi gian 1 chu k ch cn mt na, tc s l 2.67MBps. Tuy nhin, gim chu k bus dn n kh khn v mt k thut, cc tn hiu truyn trn cc ng khc nhau khng phi lun c cng tc , dn n hiu ng mo dng tn hiu. iu quan trng l thi gian chu k phi di hn so vi s tn ti ca mo dng tn hiu trnh vic nhng khong thi gian c s ho li tr thnh cc i lng bin thin lin tc. 2.2.4 Bus khng ng b (Asynchronous bus) Bus khng ng b khng s dng xung BUS clock, chu k ca n c th ko di tu v c th khc nhau i vi cc cp thit b khc nhau, gi l i thoi tun t bi cc tn hiu iu khin. Lm vic vi cc bus ng b d dng hn do n c nh thi mt cch gin on , tuy vy chnh c im ny cng dn n nhc im. Mi cng vic c tin hnh trong khong thi gian l bi s ca xung clock, nu 1 thao tc no ca vi x l hay b nh hon thnh trong 3,1 chu k th n cng s phi ko di trong 4 chu k. Khi chn chu k bus v xy dng b nh, I/O card cho bus ny th kh c th tn dng nhng tin b ca cng ngh. Chng hn sau khi xy dng bus vi s nh thi nh trn, cng ngh mi a ra cc vi x l v b nh c 51

thi gian chu k l 100ns ch khng cn l 750ns nh c, th chng vn chy vi tc thp nh cc vi x l, b nh loi c, bi v giao thc bus i hi b nh phi a c d liu ra v n nh trc thi im cnh m ca T3. Nu c nhiu thit b khc nhau cng ni vi 1 bus, trong c th c mt s thit b hot ng nhanh hn hn cc thit b khc th cn phi t bus hot ng ph hp vi thit b c tc thp nht. Bus khng ng b ra i nhm khc phc nhng nhc im ca bus ng b. Trc ht master pht ra a ch nh m n mun truy cp, sau pht tn hiu MREQ b tch cc xc nh cn truy xut b nh. Tn hiu ny cn thit khi b nh v cc cng I/O s dng chung min a ch. Sau khi pht a ch, bn master cng phi pht tn hiu RD tch cc bn slave bit rng master s thc hin thao tc c ch khng phi ghi. Cc tnh hiu MREQ b v RD b c a ra sau tn hiu a ch mt khong thi gian ph thuc tc hot ng ca master. Sau khi 2 tn hiu ny n nh, master s pht ra tnh hiu MSYN (master synchrization) mc tch cc bo cho slave bit rng cc tn hiu cn thit sn sng trn bus, slave c th nhn ly. Khi slave nhn c tn hiu ny, n s thc hin cng vic vi tc nhanh nht c th c, a d liu ca nh c yu cu ln bus d liu. Khi hon thnh slave s pht tn hiu SSYN (slave synchronization) tch cc.
Hnh 2.9-BUS khng ng b, hot ng ng b bi i thoi gia cc tn hiu iu khin. Master nhn c tn hiu SSYN tch cc th xc nh c d liu ca slave sn sng nn thc hin vic cht d liu, sau o cc ng a ch cng nh cc tn hiu MREQ, RD, v SSYN. Khi slave nhn c tn hiu MSYN khng tch cc, n xc nh kt thc chu k v o tn hiu SSYN lm bus tr li trng thi ban u, mi tn hiu u khng tch cc, ch bus master mi. Trn gin thi gian ca bus bt ng b, ta s dng mi tn th hin nguyn nhn v kt qu MSYN tch cc dn n vic truyn d liu ra bus d liu v ng thi cng dn n vic slave pht ra tn hiu SSYN tch cc, n lt mnh tn hiu SSYN li gy ra s o mc ca cc ng a ch, MREQ b, RD b, v SSYN. Cui 52

cng s o mc ca MSYN li gy ra s o mc tn hiu SSYN v kt thc chu k. Tp cc tn hiu iu khin phi hp vi nhau nh vy c gi l kt ni hon ton (full handshake), ch yu gm 4 tn hiu sau: MSYN tch cc. SSYN b tch cc p li tn hiu MSYN. MSYN c o p li tn hiu SSYN b (tch cc). SSYN b c o p li tnh hiu MSYN khng tch cc. Ta c th nhn thy bt tay ton phn l c lp thi gian, mi s kin c gy ra bi 1 s kin trc ch khng phi bi xung BUS clock. Nu 1 cp master-slave no hot ng chm th cp master-slave k tip khng h b nh hng. Tuy u im ca bus bt ng b rt r rng, nhng trong thc t phn ln cc bus ang s dng l loi ng b. Nguyn nhn l cc h thng s dng bus ng b vi cc vi mch ng b v tiu chun k thut, tc nhanh, khi lng bit ln, khon cch BUS ngn (trn mt bo mch ch) v d thit k hn. CPU ch cn chuyn cc mc tn hiu cn thit sang trng thi tch cc l b nh p ng ngay, khng cn tn hiu phn hi. Ch cn cc la chn ph hp th mi hot ng u tri chy, khng cn phi bt tay. 2.2.5 Trng ti BUS (bus arbitration) Trong h thng my tnh khng phi ch c CPU lm bus master, cc chip I/O cng c lc lm bus master c th c hay ghi b nh v gi ngt. Cc b ng x l cng c th lm bus master. Nh vy ny sinh ra vn : iu g s xy ra khi 2 thit b tr ln ng thi cn lm bus master? T cn c mt c ch phn x trnh s hn lon ca h thng. C ch phn x c th l tp trung hay khng tp trung. Trng ti BUS tp trung Nhiu vi x l c n v phn x c ch to nm ngay trong chip CPU, trong mt s my tnh mini, n v ny nm ngoi chp CPU. Theo c ch ny th b trng ti (arbiter) ch c th bit c yu cu chim dng bus hay khng m khng bit c bao nhiu n v mun chim dng bus. Khi arbiter nhn c yu cu, n s pht ra 1 tn hiu cho php trn ng dy (bus grant: cho php s dng bus). ng dy ny ni qua tt c cc thit b I/O theo kiu ni tip. Khi thit b nm gn arbiter nht nhn c tn hiu cho php, n kim tra xem c phi chnh n pht ra yu cu hay khng. Nu c th n s chim ly bus v khng truyn tip tn hiu cho php trn ng dy. Nu khng th n s truyn tn hiu cho php ti thit b k tip trn ng dy, vi thit b ny s vic xy ra ging thit b trc n, qu trnh c tip din cho n khi c mt thit b chim ly bus. S x l nh vy c tn gi l chui quay vng (daisy chaining). im ni bt ca s ny l cc thit b c gn th t u tin tu thuc vo v tr ca n so vi arbiter, thit b gn hn th mc u tin cao hn.
53
Hnh 2.10 BUS chui quay vng (daisy chaining) Trng ti BUS Mt s loi bus c nhiu mc u tin, vi mi mc u tin c ng yu cu bus (bus request) v ng dy cho php bus (bus grant). V d: gi s 1 bus c 2 mc u tin 1 v 2 (cc bus thc t c 4, 8 hay 16 mc). Mi thit b trong h thng my tnh ni vi 1 trong cc mc yu cu bus, cc ng thng c s dng nhiu hn c gn vi ng dy c mc u tin cao hn. v du, cc thit b 1, 2 s dng mc u tin 1, cn cc thit b 3, 4 s dng mc u tin 2.
Hnh 2.11- Trng ti BUS Nu c mt s thit b cc mc u tin khc nhau cng yu cu, arbiter ch pht ra tn hiu grant i vi yu cu c mc u tin cao nht. Trong s cc thit b c cng mc u tin, thit b no gn arbiter hn s u tin hn. V mt k thut, khng cn ni ng grant level 2 gia cc thit b v chng khng bao gi i hi bus mc 2. Tuy nhin, trong thc t thun tin cho vic lp t ngi ta hay lm nh sau: ni tt c cc ng grant thng qua tt c cc thit b, nh vy s d dng hn l ni cc ng grant mt cch ring bit, v t cn c vo thit b no c quyn u tin cao hn. Mt trng ti BUS c ng dy th 3 ni ti cc thit b cc thit b xc nhn nhn c tn hiu grant v chim dng bus ng tn hiu xc nhn ACK (acknowledgement). Ngay sau 1 thit b pht tn hiu tch cc trn ng dy ACK, c th o tn hiu trn cc 54

ng dy request v grant xung mc khng tch cc. Cc thit b khc c th yu cu bus khi thit b u tin ang dng bus. Khi s truyn thng kt thc, bus master k tip s c la chn. Cch lm vic nh vy lm tng hiu qu s dng bus, nhng cn thm 1 ng truyn tn hiu v cu trc thit b cng phc tp hn. Cc chip trong my tnh PDP-11 v cc chip Motorola lm vic vi cc bus nh vy. Trng ti BUS khng tp trung Trong Multibus, ngi ta cho php c th la chn s dng phn x bus tp trung hay khng tp trung, c ch phn x bus khng tp trung c thc hin nh sau:
Hnh 2.12-Trng ti Bus khng tp trung trong multibus C ch s dng 3 ng dy, khng ph thuc vo s lng thit b ni vi bus: Bus request: yu cu chim dng bus. Bus busy: ng bo bn, c bus master t mc tch cc khi c thit b ang chim dng bus Bus arbitration: c mc ni tip thnh 1 chui xch qua tt c cc thit b ngoi vi. u ca chui ny c gn vi mc in p 5V ca ngun nui. Khi khng c n v no yu cu chim dng bus, ng dy phn x bus truyn mc tch cc ti tt c cc thit b trong chui xch. Khi 1 n v no mun chim dng bus, u tin n kim tra xem bus c rnh khng v u vo In ca ng trng ti bus c mc tch cc hay khng. Nu khng (not active) th n khng tr thnh bus master. Ngc li, n s o u Out thnh khng tch cc, lm cho cc thit b ng sau n trong chui xch c u In khng tch cc. Khi trng thi c th hiu lm (khong thi gian tn hiu trn u In v Out ang thay i) qua i, ch cn li duy nht 1 thit b c u In tch cc v Out khng tch cc. Thit b ny tr thnh bus master, n s t bus busy tch cc v bt u truyn thng tin trn bus. 2.2.6 Bus m rng (Expansion bus) Bus m rng cho php bo mch ch lin lc c vi cc thit b ngoi vi, cc thit b ny c ci t qua cc khe cm m rng (expansion slot). Cc thng s chnh ca bus m 55

rng: tc truyn ti a gia cc thit b vi nhau v gia cc thit b vi b nh chnh, s ng a ch (s lng nh c th c truy xut bi 1 thit b), s ng ngt cng, v.v. Bus theo kin trc chun cng nghip (ISA - Industry Standard Architecture) Bus ISA dng cho h thng ch c iu khin bi 1 CPU trn bng mch chnh, tc l tt c cc chng trnh v thit b u ch c iu khin bi CPU . Tn s lm vic cc i l 8.33 MHz ( tc chuyn ti cc i l 16.66 MBps vi s liu 2 bytes). B rng d liu l 8 hay 16 bits. ISA c 24 ng a ch nn qun l c 16 MB b nh. Bus ISA tng thch 90% vi bus AT. Bus ISA m rng (EISA) v kiu kin trc vi knh ( MCA- Micro Channel Architecture S dng cho cc CPU 32 bits ( s liu v ng a ch) t 80386 tr i. Bus EISA: y l chun m rng ca ISA b tr cc d liu 32 bits nhng vn gi c s tng thch vi mch ni ghp c. Bus EISA c 2 nc, cc tn hiu ISA c gi qua nc trn v cc tn hiu ph tr EISA qua nc di. Cc c trng ca EISA nh sau: V mt c kh: c nhiu chn cm hn nhng vn tng thch vi ISA rng d liu: c th truy xut 2 ng 8 bits (tng thch vi ISA), hay 2 ng 16 bits Do. , n v qun l bus 32 bits c th chuyn ti 4 byte vi b nh hoc thit b ngoi vi. iu ny gp phn tng tc truyn ti ln khong 33 MBps so vi 16.66 MBps ca ISA. rng a ch: ngoi 24 ng nh ISA cn thm 8 ng b sung na, do c th nh a ch trong 4 GB b nh. Phn cng c thit k theo h thng EISA phc tp hn ISA v n cng phi thc hin cc chu k bus tng thch vi ISA. EISA c th thc hin phn x bus, n cho php vi x l nm ngoi bng mch chnh c th iu khin ton b bus. iu ny rt hiu qu trong cc h thng a x l (multiprocessor). Hng Intel pht trin 4 chip in t phc v cho bus EISA nh sau: o ISP (Intergrated system peripheral) o BMIC (Bus master interface controller) o EBC (EISA bus controller) o EBB (EISA bus buffer) Bus MCA: Phc v cho h thng IBM PS/2 khng tng thch vi bus ISA, c th hot ng vi 16 hay 32 bits d liu. N c nhiu ng dn hn ISA, thit k phc tp cho php gim bt cc nhiu cao tn ca PC ti cc thit b xung quanh. Tc truyn d liu c th ln ti 160 MBps. Bus cc b (Local Bus): 56

Nhc im ca cc bus chun trn l mc d xung clock ca CPU rt cao nhng cng ch lm vic vi cc ngoi vi vi tc truyn ti khng qu 33MBps. iu ny khng th p ng c tc ca cc card ho cm vo khe cm ca bus m rng trong ch ha. Chun cc bus cc b to thm cc khe cm m rng ni trc tip vo bus cc b (bus ni gia CPU v cc b m). Do vy, bus m rng loi ny cho php truy xut ln trn 32 bit cng nh tn dng c tc xung clock ca chnh CPU, trnh c ro cn 8.33MHz ca bus h thng. Theo hng gii quyt ny, Intel pht trin bus PCI v U ban VESA (Video Electronics Standards Association) pht trin bus VL. Bus PCI (Peripheral Component Interconnect) L loi BUS vi nhiu ci tin v dng ph bin trn PC hin i. Bus PCI l bus trong d liu v a ch c gi i theo cch thc dn knh (multiplexing), cc ng a ch v d liu c dn chung trn cc ng ca PCI. Cch ny tit kim c s chn PCI nhng li hn ch tc v phi cn 2 xung clock cho mt qu trnh truyn d liu (1 cho a ch v 1 cho d liu). Vic ni gia CPU, b nh chnh, v bus PCI c thc hin bng cu PCI (PCI bridge), qua bus PC s phc v cho tt c cc n v ca bus PCI. Ti a l 10 thit b c th c ni ti bus PCI, trong cu PCI c coi l mt. PCI c th hot ng vi rng 32 bits d liu v tc 33MHz : PCI = 33Mhz x 4 bytes (32 bits) = 133MB/s. Hin ti PCI pht trin PCI-X 2.0, chy 64 bit vi BUS clock=266/533 MHz cho thng bng ti 2,15 GB/s v 4,3 GB/s. Mt im mnh ca PCI l d liu c truyn ti theo kiu cm (burst), trong a ch ch truyn i 1 ln, sau n s c hiu ngm bng cch cho cc n v pht hoc thu m ln trong mi xung clock. Do , bus PCI hu nh c lp y bi d liu. Khi thit k cn xem li chi tit cc tiu chun/nh ngha chn ca tng loi BUS s s dng cho bo mch. Bus SPI (Serial Peripheral Interface ) L loi bus lin kt d liu ni tip, ng b, hot ng theo kiu ch/t (Master/Slave). V kt ni bao gm mt thit b lm ch (master) iu phi v ng b hot ng, cung cp xung ng h (clock) chung cho ton bus v mt hay vi thit b khc hot ng th ng (t), nhn xung ng h. Ngoi ra cn c cc dy d liu. Bus c 4 dy ni. Bus c s dng ph bin trong cc h c vi iu khin ni vi cc vi mch khc, tc cao, s dng t dy ni lin kt. Giao thc vn hnh do phn mm hay cng ha trong cc chip s dng SPI. Mt s kt ni in hnh nh sau: Chn vi mch ngha ng dng MOSI Master out/Slave in P ASIC MISO Master in /Slave out ASIC P SCK Serial clock P ASIC SSn/CS Chip select (low active) P ASIC
57

Xem thm http://www.vti.fi/midcom-serveattachmentguidb469d17c67e60d4e3dbb25b0d099ad68/TN15_SPI_Interface_Specification.pdf
Hnh 2.13 Lin kt qua bus SPI Bus I2C (Inter-Integrated Circuit): La bus lin kt gia cc vi mch trn bo mch ch, trong cc HTN, thit b nh USB-my tnh, in thoi di ng, tc c 3.4 M bit/giy. Nguyn l hot ng theo kiu ch/t (Master/Slave), ni tip, tc thp. M hnh kt ni:
Hnh 2.14 Lin kt qua bus I2C Trong : SCL l xung ng h pht ra t chip lm ch (Master), SDA l ng d liu vi 7 bit a ch cc vi mch tham gia (vi mch ch v t). Rp l in tr ni ln ngun nui VDD. 58

C 4 ch lm vic, tuy nhin 2 ch sau l ph bin: master pht d liu cho slave master nhn d liu t slave slave pht d liu ti master slave nhn d liu t master Chi tit giao thc hot ng xem thm ti liu: http://en.wikipedia.org/wiki/I2C 2.2.7 Thc hin k thut ca BUS Cc mch 3 trng thi, mch cht v mch khuych i BUS 2 chiu. Trc tin, cng cn nhc li mt s linh kin in t s c bn s dng trong my vi tnh. Nh cng ngh cao, cc linh kin c tch hp ln v rt ln ra i, nhng khng th khng nhn li mt s mch t hp thc hin nhng hm logic c bn nht. a) Cc cng logic K hiu cc mch c ch ra trn Hnh II.2, cng biu thc hm logic gm: mch m (buffer), mch o (NOT), mch v (AND), mch NAND, mch hoc (OR), mch NOR v mch XOR.
Hnh 2.13-Cc mch logic thng dng trong thit k k thut s Cc loi mch ny thng c s dng to nn cc mch t hp logic thc hin cc chc nng lp m, gii m, dn knh v phn knh. Cng cn lu rng, mt s mch chc nng nh gii mm dn knh v phn knh c cc hng tch hp di dng cc mch MSI. Mt s mch c th k ra nh mch gii m 3/8 SN74138 to tn hiu chn port (Chip Select hay CS), mch dn knh 74151-74257, mch cng, v mch nhn v.v b) Mch 3 trng thi (Tri-state Component) 59

Trong h my tnh s, c nhiu khi chc nng cn thng tin, nhng ti mt thi im, bao gi cng ch c mt khi a tn hiu ra (d liu) v mt s hn ch cc khi thu nhn tn hiu c iu khin (ng b) bng chng trnh my tnh. Thay v ni dy dn lin kt cc khi qua tng i phn t mt, cc tn hiu ny c a ln BUS. Vi cc cng logic thng thng, khng th ni trc tip chng ln cng mt ng dy v s xy ra tranh chp BUS v on mch. V d u ra ca phn t A l 1 trong lc u ra ca phn t B l 0. Cc u ra ca loi mch ny u theo cu trc y ko (pull-up), ngha l c hai transistor c ni ni tip vi nhau (xem hnh v), emitter ca transistor ny qua mt diode ri n u ra, n collector ca transistor kia. Vi hai trng thi logic 1 v 0, tng ng s l T1 m, T2 ng v ngc li, T2 m v T1 ng. Trn hnh v hin tng nguy him xy ra khi li ra ca phn t logic A l 1, cc kho m hay ng tng ng vic transistor thng bo ho hay ngt, li ra ca phn t logic B l 0 v hin tng on mch xy ra.
Hnh 2.16 Cc kiu ni u ra, u ra tr khng cao trnh hin tng ny, mt loi cng logic gi l cng 3 trng thi (tri-state gate HZ, hay 3 trng thi: 0, 1 logic v tr khng cao) c s dng cho li ra ca cc khi ni chung vo BUS. Hnh sau l mt phn t o (invertor) vi u ra 3 trng thi.
60
Hnh 2.17 Vi mch 3 trng thi: hai trng thi logic v trng thi th 3 HZ: u ra b tch khi BUS. c) Mch cht, thanh ghi: Mch cht l mt mch gm cc phn t c kh nng lu gi cc gi tr 0 hoc 1 li ra. C th dng D Flip-Flop lm mt mch cht vi tn hiu cht d liu CK ti u ra Q theo bng gi tr chn l sau: D l u vo, Q l u ra, CK l ng h iu khin. Bit rng Qn+1 = D vi tn hiu iu khin l s xut hin sn dng ca xung nhp CK. Nh vy, gi tr logic (0 hoc 1) ti D c chuyn sang u ra Q (cht). Nu CK gi nguyn trng thi bng 1, th trng thi u ra Q c gi nguyn. Nh vy, gi tr logic ca D c lu gi Q (nh).
Hnh 2.18 Mch cht (hay nh, gi li) kiu D, lm vic theo mc hay sn ln ca xung ng h CK. (Xem thm chi tit mach SN 7474). cht 4 bit ta s dng 2 vi mch 7474 v c s nh sau:
Hnh2.19-Cht 4 bit vi D-Flip/flop 61

Vi mch SN 74374 s cht c 8 bit D7-D0. Vi 2 mch SN 74374 s cht 16 bit. Mch ny thng dng cho BUS a ch. d) Mch khuych i BUS 2 chiu
Hnh 2.20- Cng khuych i (driver) cht hai chiu Trn c s ca cc mch 3 trng thi, cc mch khuych i BUS hai chiu c xy dng theo nguyn l sau: Hai phn t 3 trng thi s c ghp ngc vi nhau, chn iu khin s dng tn hiu chn chiu v o tn hiu , v d tn hiu c RD. Khi xut hin tn hiu RD, d liu c php i t Q0 sang D0, ngc li, tn hiu ch c php i t D0 sang Q0 v cho php CPU a tn hiu ghi d liu ra ngoi. Ghp ni s phn t cho tt c cc dy d liu, ta c mch khuych i BUS hai chiu. Trong thc t, mch c chc nng trn c tch hp theo chun ca TTL, c k hiu l SN 74244 hay SN 74245 (hoc Intel 8288- Octal BUS Transceiver). 2.3 BO MCH mt HTN VI CU HNH TI THIU Tuy cha cp chnh xc v thit k phn cng ca mt HTN, nhng v d sau y hon ton c th c s dng nh mt HTN. H c xy dng theo kiu HTN duqja trn bo vi x l v cc linh kin khng cng trong mt chip nu Chng 1. Di y l mt m hnh ti thiu xy dng vi CPU Intel 8085, c ROM Monitor v chng trnh ng dng, RAM d liu v vi mch ghp ni vi thit b ngoi. Mt thit k ti thiu vi CPU, ROM. RAM v Cng I/O Cc linh kin cho bo mch MSC-85: 1 CPU 8085A Xtal cho f=3.0 Mhz 1 8755 2048 byte PROM 1 8156 256 bye RAM Programmable Timer/Counter x Port 8 bit programmable
62

1 x Port 8 bit programmable. Cc cng s dng ghp cc thit b ngoi vo bo mch. Phn mm Monitor np vo ROM
Mt thit k ti thiu vi CPU, ROM, RAM v Cng I/O. Cc cng s dng khi thit k ghp ni vi cc thit b ngoi vi. B nh c th m rng khi c tng phn hoch khng gian nh cho ROM v RAM m rng phn mm, bao gm HH v ng dng. CPU 8085 l CPU rt mnh, h 8 bt. S chun t ngun ca Intel:
63
Hnh 2.21- Cu hnh ti thiu bo mch CPU 8085, RAM/ROM/Ports
64
Hnh 2.22- Mch in cho hnh 2.21 Khi xy dng xong phn cng (mch in, hn cm, vi mch ), to phn mm np vo ROM.
65

2.4 HTN VI CC CPU KHC NHAU 2.4.1 CPU a nng 16 bit Khi nhu cu x l s liu i hi c chnh xc cao v thc hin cc chc nng bi cc gii thut tinh xo v i hi x l nhanh, th cc CPU 8 bit c th khng p ng c, c bit khi HTN c s dng cc h iu hnh nh RTOS. Trong trng hp ny cn b x l vi s bit biu din s liu ln n 16, 32 bit. Vi h CPU a nng, c th chn Intel 8086/8088. Di y l m hnh kin trc ca Intel 8986:
Hnh 2.23- CPU Intel x86 Cc thanh ghi bn trong:
66
Cc CPU h 80x86 c pht trin trn c s cng ngh ch to CHMOS vi mt tch hp rt cao (VLSI), c tiu hao cng sut rt nh. S khi chc nng ca CPU 8086 c th hin trn nh hnh trn, gm hai thnh phn ch yu l n v ghp ni BUS (BIU BUS Interface Unit), n v thc thi lnh (EU Execute Unit). Tt c cc thanh ghi v ng truyn d liu trong EU u c di 16 bits. BIU thc hin tt cc cc nhim v giao tip vi BUS bn ngoi: thit lp khu lin kt vi BUS d liu, BUS a ch v BUS iu khin. D liu c trao i gia CPU vi b nh khi EU c yu cu, song khng c truyn trc tip ti EU m thng qua mt vng nh RAM dung lng nh (6 bytes) c gi l hng nhn lnh trc (Instruction Stream Byte Queue PQ - PreFetch Quere) ri mi c truyn cho h thng thc thi lnh EU. BUI bao gm cc thanh ghi on nh, con tr lnh, v b iu khin BUS. EU chnh l li ca h CPU X86 v gn ging nh CPU 8085 cp. C th m t cch lm vic n gin nh sau: Khi EU ang thc hin mt lnh th BUI tm v ly lnh sau t RAM ngoi v t sn vo PQ. y l c ch ng ng (pipeline), mt k thut tng tc cho CPU. K thut ng ng s dng mt vng nh RAM cc nhanh (PQ), lm tng ng k tc ca b x l thng qua vic truy tm lnh PQ thay v tm t b nh RAM bn ngoi. Nu so vi cch thc truyn thng, c th coi thc t thi gian ly lnh bng 0. C th tm hiu thm v CPU loi ny t cc ti liu chuyn mn khc. Cho d CPU hot ng bn trong c khc, nhng nhng nguyn l my tnh th khng c g thay i khi thit k. Khi tm hiu k ti liu thit k vi CPU c th ta c th ln c mt s cho bo mch. Vi CPU 8086, mt thit k vi qui m ti thiu s nh sau: - CPU - Mch to xung nhp ng h 8284 - Mch to cc tn hiu cho BUS iu khin 8288 - Mch cht a ch latch 16 bit vi xung ALE 67

- Mch khuych i BUS d liu 3 trang thi 8286 Mch iu khin ngt (s dng vi mch chuyn dng 8259 cho 8 ngt, m rng ti 16 ngt, t chc theo vector, khc vi CPU 8085 !). Cc vector ngt c nh ngha nh sau: S ca vector ngha ca vector 0 Divide error 1 Debug exception 2 Non-masked interrupt NMI 3 One byte interrupt INT 4 Interrupt on overflow INTO S Array bounds check BOUND 6 Invalid opcode 7 Device not available 8 Double fault 9 Coprocessor segment overrun 10 Invalid TSS 11 Segment not present 12 Stack fault 13 General protection fault 14 Page fault 15 Reserved 16 Coprocessor error 17-32 Reserved 33-255 INT n trap instructions
68
Hnh 2.24 Bo mch vi ti thiu vi CPU 8086:BUS controller, Ngt controller, RAM Biu thi gian. bit chc nng cc tn hiu trong s , ly v d v chu k c b nh sau y:
Hnh 2.25 CPU 8086 timing: lnh c 69

T1: a ch t ln BUS dn knh AD Address/Data bus. Tn hiu iu khin M/ IO , ALE and DT/ R s cho bit thao tc l ttruy nhp b nh hay thao tc vo/ra (do m lnh OPCODE). Cht a ch li, lp hng truy d liu trn B d liu. T2 : 8086 pht tn hiu RD hay WR, DEN. ghi dua liu,DEN cho php b nh hay thit b IO nhn d liu ghiv CPU nhn d liu c. T3 : B nh nhn d liu. READY dng ko di s trng thi ch nu s dng RAM c thi gian truy nhp lu (access time). READ c CPU ghi nhn cui T Nu READ=low, T 3 thnh T i (ko di trng thi truy nhp RAM RD hay WR. READY=high, d liu c ghi nhn cui T3. T4 : BUS treo, chun b cho chu k tip theo. Lu : Khi thc hnh c k ti liu CPU 8086 ! 2.4.2 Bo mch vi CPU HARVARD- (microcontroller Unit-MCU), h Intel 8051/8052/8xC251 Intel pht trin chip n vi iu khin (microcontroller - C, VK) 8051 vi kin trc Harvard vo nm 1980 v ph bin cho ti nhng nm 1990. Nhng nm sau mt s hng khc trn th gii tip tc pht trin v nng cao, a dng, ph bin rt rng ri, dng hu nh trong mi lnh vc u cn t ng ha x l d liu. Vi iu khin c mt s c im nh sau: V phn cng, VK ging nh mt my vi tnh c nh, c ch to ch trong mt vi mch (chip n). Nh vy c ngha cc thnh phn cu trc cho my vi tnh u c y. Nhng cn hn th na, l cc vi mch chc nng rt a dng, bao gm: cc b bin i tng t-s (Analog-Dital converter), s-tng t (Digital-Analog converter), rt nhiu cng ghp ni cho tn hiu vo/ra cc ch song song, ni tip, ng thi, mt vi b nh thi (Time counter), cc b ngun p chun, c ROM (hay EPROM, hay FLASH), RAM ngay trong vi mch. Cch khai thc ROM, RAM cng khc, l t l dung lng ROM/RAM cao hn (tc l ngc vi my vi tnh, my tnh). l v chng trnh x l cn c trong ROM, trong khi RAM ch l ni nhp s liu. ROM y l cc b nh khng b mt d liu (non-volatile memory) vi cc cng ngh khc nhau, c dung lng
70

rt ln, c th cha c cc h iu hnh (v d cc router, chuyn mch SW c IOS, ADSL hp nht cc lp 1, 2, 3 cng ngh mng, ). Tp lnh ca cc VK thng khng a ch nh CPU a nng, nhng va cho cc lp ng dng, sao cho hiu nng x l l cao nht, c bit l x l cho p ng u ra nhanh nht (tm gi l p ng kiu thi gian thc). Do c mt tch hp cao nh vy, v xut pht t thc t, vi cng ngh ch to chip tng thi k pht trin, tn s lm vic ca CPU thng khng cao nh cc vi x l a nng. Do c cu trc nh vy nn thi gian pht trin cho lp ng dng ngn hn, gi thnh sn phm thp hn, cng sut tiu th thp hn, hiu sut ng dng cao hn, tin cy cao hn. L t nhin l chu k pht tin mi, ci tin, nng cp, a dng sn phm ngn hn. Thm ch trong khi khng nng cp phn cng, ch nng cp phn mm, cng mang li s thay i ng k ca sn phm. Kin trc ca CPU cng c khc, kin trc c tn l kiu Havard, vi cc c im nh sau: M hnh kin trc Havard nh sau:
Hnh 2.26 M hnh kin trc Havard: BUS cho b nh chng trnh: Code Bus v Code Address; BUS cho RAM d liu: Data Bus v Data Address; SRC1, SRC2:ngun, DST: ch, l cc Bus ni b. 71

Tch ring cc b nh d liu (RAM) v b nh chng trnh vi cc bus ring r truy cp vo b nh d liu (RAM) v b nh chng trnh (NVM Non Volatile Memory: ROM, FLASH) cha phn mm nhng (h iu hnh, Device drivers, ng dng nhng ). Cc bus iu hnh c lp, cc ch dn chng trnh v d liu c th c a ra cng mt lc, ci thin tc so vi thit k vi ch mt bus. Phn bit r rng b nh d liu v b nh chng trnh, CPU c th va c mt lnh, va truy cp d liu t b nh cng lc. Do cc BUS c lp, CPU c kh nng tm trc (instruction prefetch), nn vi kin trc Harvard chng trnh chy nhanh hn, bi v n c th thc hin ngay lnh tip theo khi va kt thc lnh trc . Tuy nhin v kin trc c phn phc tp hn trong phn cng, nhng cho hiu qu hn cho cc ng dng nhng. L loi ph bin thit k cc HTN.
Hin nay Intel khng cn cung cp cc loi Vi iu khin h MCS-51 na, thay vo cc nh sn xut khc nh Atmel, Philips/signetics, AMD, Siemens, Matra&Dallas, Semiconductors c cp php lm nh cung cp th hai cho cc chip ca h MSC-51. Chip Vi iu khin c s dng rng ri trn th gii cng nh Vit Nam hin nay l Vi iu khin ca hng Atmel vi nhiu chng loi vi iu khin khc nhau. Atmel c cc chip Vi iu khin c tnh nng tng t nh chip Vi iu khin MCS-51 ca Intel, cc m s chip c thay i cht t khi c Atmel sn xut. M. s 80 chuyn thnh 89, chng hn 80C52 ca Intel khi sn xut Atmel thnh 89C52 (M s y : AT89C52) vi tnh nng chng tr.nh tng t nh nhau. Tng t 8051,8053,8055 c m. s tng ng Atmel l 89C51,89C53,89C55. Vi iu khin Atmel sau ny ngy cng c ci tin v c b sung thm nhiu chc nng tin li hn cho ngi dng.
72

V d bo mch xy dng trn CPU 8051 c tn chung l h C MCS 51.
Hnh 2.27 Cc khi chc nng ca CPU 8051/8052
73
Hnh 2.28 CPU 8051: EEPROM, RAM bn trong v kh nng m rng b nh ti 128 KB (64 KB code+64 KB data) Mt HTN: Bo mch vi iu khin MCU (hay C) vi CPU 8052 v cc vi mach h tr cho ng dng nhng: (http://www.keil.com/dd/docs/datashts/silabs/c8051f52x.pdf)
Hnh 2.29 Bo mch vi CPU 8051/8052 Di y l cc thng s cho thy cc thnh phn ca bo mch HTN hp nht SBS 8051F530: 74

Ngoi vi tng t: - 12-Bit ADC Sai s 1 bit nh nht (LSB INL) (C8051F52x/C8051F53x); Lp trnh ly mu vi tc ti a n 200.000 mu trong mt giy (2000 ksps) S knh u vo: 6/16 Giao din kt ni dng ngt C cm bin nhit bn trong vi mch - B so snh Lp trnh c vi tr p ng Ci th cu hnh lm thit b nh thc hay ngun to tn hiu RESET Dng in tiu th thp - Kh nng ti khi ng khi ngun nui thay i theo ngng nht nh (POR/Brownout Detector) - in p chun 1 .5 n 2.2 V (lp trnh c) - Gi ri ngay trn chip (On-Chip Debug) Ngun nui cho hot ng 2.7 to 5.25 V - C n p gi tr thp (LDO regulator) Nhn 8051 c tc x l cao - C ch ng ng (Pipelined instruction architecture), 70 % cc lnh thc hin ngay 1 hay 2 ng h h thng; - Tc x l ti 25 MIPS xung ng h h thng 25 MHz - C kh nng m rng ngt B nh - 8/4/2 kB Flash; In-system byte programmable in 512 byte sectors - 256 bytes internal data RAM Ngoi vi s - 16/6 cng I/O; u ra c ch d y ko, 5 V - Cng SPI, v UART - Giao tip mng tc thp qua b LIN (Hardware LIN - Local Interconnect Network, c hai ch ch/t, tng thch vi chun V1.3 v V2.0) - C 3 b m/nh thi a nng 16-bit kh trnh, kh so snh theo module, lm ch canh cng (WDT-Watch Dog Timer) Ngun ng h - ng trong vi b giao ng 24.5 MHz , chnh xc 0.5% h tr cho cc giao hot ng ca UART v LINMaster - B giao ng ngoi dng thch anh hay b giao ng RC, hay xung ng h ni vo qua kiu ni 1 hay 2 chn u vo - C th chuyn i ngun ng h ngay khi ang hot ng (on-the-fly) Cch ng gi: - 10-chn hn dn QFN (3 x 3 mm) - 20-chn hn dn QFN (4 x 4 mm) - 20-chn hn dn TSSOP Thang nhit mi trng lm vic: 40 to +125 C
C th tm hiu thm bo mch Bo mch 8052.com SBC tai www.8052.com Bo mch 8052.com Single Board Computer (SBC) s dng CPU Atmel AT89S8252/AT89S8253 v Dallas DS89C420, nhng c th cm bt k chip 40-pin 8052 tng thch ( 8052, 8051, 8032, 75

8031, etc.); SBC cng s dng c vi CPU mi AT89S8253 (loi thay th chip AT89S8252). C th s dng SBC cho nghin cu, thit k hay trin khai cc d n ng dng HTN. Hin ti Cs MCS 51 nng cp ln vi CPU 8XC251Sx v gi l h MCS 251. H MCS 251 c mt s c t sau y: Khng gian a ch ha tuyn tnh 24 bit cho bo nh ti 16MB, CPU c xy dng trn c s cc thanh ghi v cc thanh ghi truy nhp c theo kiu byte, t (2 byte), t kp (4 byte), Truy nhp b nh lnh theo ch d trang, tng tc chu k tm lnh, Thc hin lnh kiu ng ng (pipeline), Tp lnh mnh, thc hin lnh s hc v logic 16 bit, M rng ngn xp ti 64 KB, Tc hin lnh (chu k lnh) trong 2 clock (trong khi MSC51 cn 12 clock), 3 gii php cho trng thi i (wait state): real-time, RD#/WR#/PSEN#, and ALE, M nh phn tng thch hon ton vi MSC 51 do khng gian a ch ca MSC51 c nh x vo khng gian a ch ca MSC251. Vi b nh ln, h tr chng trnh c m ln (H iu hnh + ng dng phc tp), Chy rt hiu qu vi m vit t ngn ng C iu khin BUS ng qua s dng cc thao tc trng thi i thi gian thc (real-time wait state). CPU tin tin h 8XC251Sx:
76
Hnh 2.30 Cc khi chc nng ca nhn 8XC251Sx
77

a) Tng quan v CPU Intel 8051
Hnh 2.31 CPU 8051 Ngoi cc trung tm vi x l h x86, Intel cn thit k v sn xut cc vi x l chuyn dng phc v cc mc ch o lng v iu khin t ng, m thc cht l cc h thng nhng. Cc chip vi x l loi ny vt ra ngoi khun kh ca mt trung tm vi x l n thun, tr thnh mt my tnh kiu vi iu khin (MicroController- C). B qua kin trc bn trong l kiu Harvard, v nhn theo kin trc xy dng bn ngoi v d m t v lp trnh, ta c th coi nh hot ng nh mt my vi tnh, th ging nh kin trc my tnh ca Von Neumann. CPU c trang b thm b nh chng trnh (ROM hoc EPROM) v b nh d liu, cng nh cc cng vo/ra ni tip, vo/ra song song, ngay trong vi mch. Vi mch ch yu ca h MCS - 51 l chip C8051/8052, linh kin u tin ca h ny c a ra th trng. Chip C8051 c cc c trng c tm tt nh sau: - 4 KB ROM v 128 byte RAM - 4 port 8- bt, 32 li vo/ra - 2 b nh thi (Timmer) 16 bt - Mch giao tip ni tip - Khng gian nh chng trnh ngoi (m rng) 64K - Khng gian nh d liu ngoi 64K - B x l bt (thao tc trn cc bt ring r) - 210 v tr bit nh c nh a ch Cc thnh vin khc ca h MCS-51 c cc t hp ROM (EPROM), RAM trn chip vi dung lng khc nhau, b bin i tn hiu tng t-s v s-tng t, v c th c thm b nh thi th ba. Mi mt chp ca h MCS-51 u c phin bn CMOS tiu th cng sut thp. 78

Khi thit k HTN vi CPU 8051, cn tham kho ti liu k thut. Mt s lu cn quan tm bao gm: b) Phn hoch a ch Do thu nh kin trc to ra vi iu khin cho cc ng dng c bit, nn 8051 s dng cch a ch ha khc thng (so vi cc CPU a nng) m ha cho cc thanh ghi v khng gian b nh. Di y l m hnh din t cch a ch ha :
Hnh 2.32 Phn hoch a ch trong CPU 8051 c) V d thit k m rng b nh vi CPU 8051 V dung lng b nh trong Chip nh i khi khng cha m chng trnh, nn cn m rng b nh qua mt thit k m rng. Di y l mt thit k to ra 64KB ROM v 64KB RAM qua cc cng t CPU 8051: 79
Hnh 2.33 Bo mch vi CPU Intel 8051 v RAM, ROM m rng bn ngoi. Truy xut b nh chng trnh ngoi B nh chng trnh ngoi l b nh ch c, c cho php truy xut bi tn hiu PSEN. Khi c mt EPROM ngoi c s dng, c hai port 0 v port 2 khng c s dng cho mc ch vo/ra. Kt ni 8051vi b nh ngoi EPROM c trnh by hnh trn. Mt chu k my ca 8051 c 12 xung nhp. Nu b giao ng trn chip c tn s 12MHz, mt chu k my di 1sec. Trong mt chu k my in hnh, ALE c 2 xung v 2 byte ca lnh c c t b nh chng trnh (nu lnh ch c mt byte, byte th hai c loi b). B nh d liu ngoi l b nh c/ghi c cho php bi cc tn hiu RD v WR cc chn ca P3. Lnh dng truy xut b nh d liu ngoi l: MOVX, s dng hoc con tr d liu 16-bt DPTR hoc R0, R1 lm thanh ghi cha a ch. RAM c th giao tip vi 8051 theo cch nh EPROM ngoi tr ng RD ni vi ng cho php xut (OE) ca RAM v WR ni vi ng ghi (WR) ca RAM. Cc kt ni vi bus d liu v bus a ch ging nh EPROM. Bng cch s dng cc port 0 v port 2 v cc chip nh, ta c dung lng RAM v ROM ngoi ln n 64K
80

d) Lp trnh cho C8051 lp trnh cho 8051, ngi lp trnh cn nm tht vng cch t chc rt hu hiu nhng tng i phc tp ca b nh RAM tch hp trong chip. Khng n thun ng vai tr b nh d liu trong MCS51, n cn s dng mt phn b nh RAM lm thanh ghi a nng v thanh ghi vi cc chc nng c bit. Tn ti chng trnh Assembler ring cho h MCS51, lp trnh hp ng tng ng nh lp trnh hp ng cho h 80x86. im mnh tng ng l tn ti mt phin bn ngn ng C cho MCS51, to iu kin cho nhng ai quen vi lp trnh C c th to cc phn mm ng dng ci t vo trong b nh ROM ca MCS 51 cho nhng ng dng thc t. C th tham kho ti liu 1. Nguyn Tng Cng, Phan Quc Khnh: Cu trc v lp trnh h Vi iu khin 8051. NXB KH&KT H Ni-2004 v lp trnh cho C8051 c nu cui cun gio trnh ny. 2. B Kit 8051/251 Evalution Kit ca KEIL Software l ti lii c s dng ph bin vi cc cng c pht trin. e) Cc kh nng ng dng ca C8051 Thng thng, cc trung tm vi x l c dng xy dng nn cc my tnh. Ring cc trung tm ca Single Chip Microcomputer, do nhng cu trc c trng v tnh nng k thut, c ng dng nhiu trong cc thit k nh, c bit l trong cc h thng nhng, vi s thnh phn ph tr thm vo ti thiu nht. Nh cu trc v kh nng ci t cc chng trnh ng dng ngay trong b nh ROM hoc b nh Flash tch hp sn, cc hng v cc ng dng c th ca h vi x l ny ch yu tp trung vo cc mc ch gia dng v dn dng. Thng k mt s lnh vc ng dng ca cc trung tm vi x l h ny c lit k trong bng sau. CPU 8051 v cc lnh vc ng dng: iu khin trong cng nghip (System Supervision) iu khin ng c Hng khng My y t Truyn thng, truyn d liu Mng: - V mng - Thit b khng dy, - in thoi di ng, - B lp li (repeater), - Chuyn mch (switch) Video game, chi (toy) 81

Thit b: - Thit b cm tay, thit b di ng - Thit b u cui truy nhp d liu - H thng n hiu ng st - Trm v tinh mt t, - H thng gim st khng dy. - in thoi My tnh H thng an ton - My in Laze, my in mu, my nhn tin Trong gia nh: - in gia dng Thit b m thoi in thoi H thng an ton M ng ca Tr li t ng My FAX, - My tnh gia nh TV Truyn hnh cp VCR Camera iu khin t xa Tr chi in t - Nhc c in t, iu khin nh sng
2.4.3 Vi mch H thng kh trnh trong mt Chip (Programmable System-on-a-chipPsoC) v Vi iu khin (Programmable Intelligent Computer-PIC) L mt cng ngh pht tin rt mnh hin nay, m nn tng c s l : hp nht tt c cc thnh phn mt my vi tnh, cc vi mch in t chuyn dng nh ADC/DAC, DSP vo mt vi mch duy nht vi kh nng lp trnh ng dng ngay trn vi mch . Lnh vc ng dng l to ra cc HTN vi ph cu hnh t n gin ti phc tp. nc ta y l xu hng pht trin rt mnh bi d thc hin v c bit gi thnh rt hp l. PIC: PIC bt ngun l ch vit tt ca "Programmable Intelligent Computer" (My tnh kh trnh thng minh) l mt sn phm ca hng General Instruments t cho dng sn phm u tin ca h l PIC1650. Lc ny, PIC1650 c dng giao tip vi cc thit b ngoi vi cho my ch 16bit CP1600, v vy, ngi ta cng gi PIC vi ci tn "Peripheral Interface Controller" (B iu khin giao tip ngoi vi). CP1600 l mt CPU tt, nhng li km v cc hot ng xut nhp, v v vy PIC 8-bit c pht trin vo khong nm 1975 h tr hot ng xut nhp cho CP1600. PIC s dng microcode n gin t trong ROM, v mc d, cm t RISC cha c s dng thi by gi, nhng PIC thc s l mt vi iu khin vi kin trc RISC, chy mt lnh mt chu k my (4 chu k ca b dao ng). Nm 1985 General Instruments bn b phn vi in t ca h, v ch s hu mi hy b hu ht cc d n - lc qu li thi. Tuy nhin PIC c b sung EEPROM to thnh 1 b iu khin vo ra kh trnh. Ngy nay rt nhiu dng PIC c xut xng vi hng lot cc module ngoi vi tch hp sn (nh USART, PWM, ADC...), vi b nh chng trnh t 512 word n 32K word (1word=16 bt). 82
V cu trc ca PsoC/PIC: s tch hp nhiu thnh phn trong mt vi mch C mt hay vi vi iu khin (microcontroller), hay vi x l (microprocessor) v b x l tn hiu s ( Digital Signal Processor-DSP ). Cc khi b nh ty chn ROM, RAM, EEPROM v Flash. Ngun ng h chun gm b giao ng thch anh v mch phn hi d cht pha (phaselocked loops). Ngoi vi gm b m nh thi (counter-timers), m thi gian thc (real-time timers) v mch t ng khi ng li h thng (power-on reset). Ghp ni ngi theo chun cng nghip USB, FireWire, Ethernet, USART, SPI(Serial Peripheral Interface). Ghp ni vi tn hiu tng t ADC v DAC 8, 10, 12 bit. B ngun chun, c chnh xc cao. V d cc thnh phn hp thnh ca mt vi iu khin hon chnh:
Hnh 2.34
M hnh mt vi iu khin kiu PSoC hay PIC
Mt s vi mch PSoC l sm phm ca CYPRESS 83

V d CY8C29466: B x l kiu Harvard rt mnh * Tc ti 24 MHz * Hai b nhn 8x8, Thanh ghi tch ly ACC 32-bit * Tiu th ngun thp ngay c tc x l cao * Ngun nui : 3.0V to 5.25V * Mi trng nhit : -40C to +85C * Hi ng in t v T ng ha (AEC) chng nhn sn phm H thng cc thit b ngoi vi tin tin (PSoC Blocks) * 12 Khi lin kt thit b tng t cung cp: Cc ADC ti 14 bit Cc DACs ti 9 bit Cc b khuych i kh trnh Cc b lc v b so snh kh trnh * 16 khi k thut s cung cp: cc b m v nh thi 8 ti 32 bit, v b iu ch theo rng ca xung (PWM) cc module CRC v PRS C 4 UART chy song cng a bus SPI Masters or Slaves * Bng cch t hp cc khi tao ra thit b ngoi vi phc hp ng h kh trnh, chnh xc cao * ng h trong 24 ti 48 MHz , 5.0% * C thm ng h thch anh tn s 32.768 kHz * Ty chn ng h ngoi ti 24 MHz * Giao ng ni cho Watchdog v Sleep B nh linh hot trn chip * 32K Bytes Flash cho chng trnh * 2K Bytes SRAM cho D liu * Lp trnh trc tip qua lin kt ni tip (In-System Serial Programming -ISSP) * Nng cp Flash tng phn * C ch bo v linh hot (Protection Modes) Cc chn ni kh trnh chc nng * Dng u ra 25 mA Sink, 10 mA Drive trn tt c cc chn (GPIO) ca chip * y ko, in tr treo, tr khng cao, h mch u ra tt c cc chn ca chip. * C ti 12 u vo tng t (Analog Inputs on GPIO) * 4 u ra tng t cung caaso ti 40 mA (Analog Outputs on GPIO) * Cc ngt kh cu hnh trn tt c cc chn ngt ca chip Cc ngun ti nguyn h thng khc: * Kt ni gia cc IC kiu ch/t vi tc 400 kHz (I2C Slave, Master, and Multi-Master to 400 kHz) * Watchdog and Sleep Timers * Kh cu hnh pht hin ngun nui thp * Hp nht mch gim st (Integrated Supervisory Circuit) * C ngun in p chun chnh xc trong chip Cng c pht trin y * Phn mm pht trin t do (Free Development Software (PSoC Designer)) * u cng c m phng hiajt ng kiu ICE (Full-Featured, In-Circuit Emulator and Programmer) 84

* M phng chy vi tn s ti a (Full Speed Emulation) * Cc cu trc tm li hon ho (Complex Breakpoint Structure) * 128K Bytes nh cho lu du vt hot ng (Trace Memory) * Ghi nhn s kin y * C Compilers, Assembler, and Linker
Hnh 2.35 Vi iu khin PSoC CY8C29466 Vi mch PIC ca hng Microchip Technology
http://www.best-microcontroller-projects.com/pic-microcontroller.html
85

Mt PIC ging nh mt thit b mnh c thit k v tch hp nhiu thnh phn kiu module nh sau:

EEPROM. Timers (cc b nh thi). Analogue comparators (cc b so snh tng t). UART ( b thu pht d b vn nng). Cc cng kt ni ngoi vi, m rng b nh
Vi cc module nh vy, c th trin khai cc d n ng dng nh: * Frequency counter m tn s, s dng cc b nh thi bn trong, kt qu thng bo ra ngoi bng cch truyn thng i xa UART (RS232), hay ra LCD ti ch. * Capacitance meter - in dung k, bng cc b giao ng so snh tng t. * Event timer nh thi s kin vi cc b nh thi bn trong. * Event data logger Thu thp d liu theo nh thi v s ha bng DAC bn trong, lu d liu trong EEPROM hay lu trong b nh ngoi qua tuyn truyn d liu tc cao I2C. * Servo controller ng dng t ng ha kiu iu khin servo s dng b iu ch rng xung PWM vi phn mm iu khin servo, kt hp truyn thng qua UART n thit b u cui. V d PIC 12F675: 8 chn (Dual In Line) c cc ngoi vi tch hp nh sau:
86
PIC12F629/675 BLOCK DIAGRAM
c trng:

Two timers. One 10 bit ADC with 4 selectable inputs. An internal oscillator (or you can use an external crystal). An analogue comparator. 1024 words of program memory. 64 Bytes of RAM. 87

128 Bytes of EEPROM memory. External interrupt (as well as interrupts from internal peripherals). External crystal can go up to 20MHz. ICSP : PIC standard programming interface.
Cc PIC hng trung bnh c khng gian a ch t 1 KB n 8 KB (v d h 18FXYZ). B nh xem ra khng nhiu, nhng vi tp lnh hiu qu c th xy dng cc ng dng rt hu ch. (Xem v d PH LC : LM35 temperature sensing project). Lp trnh: S dng giao din ni tip ICSP lp trnh, c th lp trnh bng hp ng, hay C. Vo/Ra - I/O: PIC c cc cng kt ni s dng cho nhiu mc ch, v d cho iu khin motor bc, ng ct cc rele, c cc nt n ng/m, hin th ra LCD/7-segment/LED, o tn s, s dng ADC vi nhiu mc ch khc nhau Ngoi vi (Peripherals): Cc thit b tch hp bn trong rt nhiu v hu hiu cho cc d n ng dng, ty vo yu cu c th chn dng PIC vi cc c trung khc nhau. Cc c trng tng qut gm c: PIC PIC microcontroller microcontroller feature description Feature Flash memory RAM EEPROM Re-programmable program storage. Memory storage for variables. Long term stable memory : Electrically Erasable Programmable Read Only Memory. High current Input/Output ports (with pin direction change).
I/O ports
Timers/Counters Typically 3. USART CCP SSP Built in RS232 protocol (only needs level translator chip). Capture/Compare/PWM module. I2C and SPI Interfaces. 88
Comparator ADC PSP LCD
An analogue comparator and internal voltage reference. Analogue to digital converter. Parallel Slave Port (for 8 bit microprocessor systems). LCD interface.
Special features ICSP,WDT,BOR,POR,PWRT,OST,SLEEP ICSP Simple programming using In Circuit Serial Programming.
Flash memory: B nh cho chng trnh. ICSP (In Circuit Serial Programming): Cng giao din vi h pht trin, lp trnh
trc tip cho PIC nm trn bo mch thit k. Qa trnh lp trnh/th nghim c n gin ha theo kiu in the circuit cho ti khi hon thin phn mm.
Cng I/O: S dng ghp ni vi cc thit b ngoi.

Cc chn ni: Hu ht cc chn ni c th l IN hay OUT n l hay nhm qua lp trnh. 1 chn ni c th lm nhiu chc nng theo tng thi im khc nhau, v d chn RA0 ca cng PORTA: out-a d liu cho 7-segment LED, sau l cng in-c d liu vo. Cng sut cc cng ra c th cho ti 25 mA.
nh thi (Timer / Counters): Thng c 3 b m dng lm nh thi, dung

nh b m hay nh thi. Timer 0: 8 bit, c kh nng t trc mt gi tr vi tn hiu u vo c t bn trong (Fosc/4) hay t bn ngoi. Khi m trn gi tr s to ra mt ngt, c dng nh mt watch dog. Timer 1 : 16 bit, vi kh nng t trc gi tr. m trn s to ra mt ngt. Timer 2 : 8 bit, vi kh nng t trc gi tr. S dng t gi tr gc thii gian cho module PWM.
89

USART: Cng ni tip RS 232 dng kt hp vi mch to ra V24, v d vi mch
MAX232, hay SP202ECP. Baud Rates: t tc cho UART, c th hot ng ti 38.4kbaud.
CCP (Capture/Compare/PWM) iu ch PWM vi 3 ch :

Capture ghi nhn s kin Compare So snh khi Timer 1 t gi tr t trc. PWM - Pulse Width Modulation.
Capture : Ly d liu ca Timer 2 khi chn CCP xung ln cao hay xung thp do lp trnh. Compare: So snh khi Timer 1 t gi tr, v a vo CCPR1. Dng khi ng ADC. PWM: iu ch PWM vi phn gii 10 bit.
SSP (Synchronous Serial Port): kt ni vi thit b theo giao thc SPI SPI (Serial
Peripheral Interface) hay I2C(Inter IC communication). (project I2C here, more info I2C here).
Comparator and comparator voltage reference: Module so snh c 2 b so snh

tn hiu tng t, c th lp 1 trong 8 cch lm vic khc nhau: u vo c th l tng t hay s, so snh vi cc mc in p chun. in p chun c to ra bn trong chip, ni vo 1 u vo ca c 2 b so snh, vi cch dn knh c th ng dng cho 4 tn hiu vo/b so snh. u ra ca b so snh c th gi ra ngoi qua mt chn ca vi mch. Mc tn hiu vo nm trong gii hn Vdd v Vss.
ADC : Phn gii cp 10 bit, 10 u vo tng t dn knh. PSP: Cng song song 8 bit, c/ghi, ch slave, cho php mt h thng khc giao tip
trc tip vo CPU t ngoi vi tn hiu chn chip (CS-chip select). H bn ngoi nhn CPU nh thit b kiu nh x b nh (memory mapped I/O), nh vy PIC CPU l mt h con (slave) ca h kia, v c th lp trnh cho PIC thc hin cc tc v theo yu cu.
LCD: Giao din vi LCD, v d vi LCD module HD44780.

90

Cc c t c bit:
ICSP WDT In Circuit Serial Programming Watch dog timer click here (jumps to ICSP section). This is a software error protector. This detects if the power supply dips slightly and resets the device if so. This starts microcontroller initialization. A time delay to let Vdd rise.
BOR
Brown Out reset
POR
Power on reset
PWRT PoWeR up Time OST
Oscillator start up Wait for 1024 cycles after timer PWRT. Enter low power mode.
PIC SLEEP microcontroller sleep mode
WDT ( Watch dog timer): s dng khi phn mm chy c vn , s RESET cng CPU v trng thi ban u. cm reset cng CPU, khi phn mm lm vic bnh thng, cn pht sinh lnh CLRWDT ci trong chu trnh, v np li gi tr nh thi cho WDT. WDT chy theo ng h ring. POR (Power On Reset): Khi ng PIC microcontroller khi c sn ln ca tn hiu MCLR. PWRT: nu cho php PIC microcontroller s khi ng sau 72 ms. OST (Oscillator Startup Timer): tr cn 1024 chu k c tn s n nh. SLEEP (Sleep mode -or low power consumption mode) hot ng khi thc hin lnh 'SLEEP'. PIC s thc dy bi cc s kin nh: RESET ngoi, Watch Dog Timer, INT - peripheral interrupt. Mt s PIC vi cc dng khjasc nhau: 12F, 16F:
91
PIC PIC PIC microcontroller microcontroller microcontroller Device No. Pins Flash memory WORDS 12F675 16F88 16F877A 8 18 40 1k 4k 8k
Dung lng b nh Flash ca PIC Microcontroller

B nh ca PIC thng khng ln, nhng vi tp lnh RICS vn c th chy nhiu ng dng, tuy nhin nu cn b nh ln hn, hy chn PIC 16F vi 4 - 8Kword (hay 8-16KB) hay m rroojng qua lin kt I2C.
Dung lng b nh RAM v EEPROM ca PIC microcontroller

RAM cha bin v cc d liu tc th, hay tm thi, lu khi ng dng vi di d liu khng qu ln. Khng nn dng du phy ng, nn dng s nguyn di du phy c nh PIC microcontroller EEROM : cho d liu, hng s. PIC hin nay rt ph bin nc ta trong ging dy v thc hnh ng dng. C th tham kho ti: http://www.picvietnam.com/forum/showthread.php?t=10 Di y l v d loi PIC 16F888/887, ang s dng kh rng ri Vit nam:
92
93
Hnh 2.36
Vi iu khin PIC 16F882/883/886/887 - Hai tc khi ng chn khi khi ng - Pht hin s c thch anh cho cc ng dng ti hn - Kh chuyn ng h ngay khi ang hot ng tit kim nng lng C ch ng tit kim nng lng Thang ngun nui rng :2.0V-5.5V Chi ng mi trng nhit cng nghip cao Khi ng khi bt ngun (Power-on Reset (POR)) nh thi bt ngun (Power-up Timer (PWRT)) v khi ng giao ng ( Oscillator Start-up Timer (OST)) Khi ng vi phn mm Bo v m kh trnh Flash/EEPROM Cell bn vng lu di vi: - 100,000 ln ghi voFlash 94
CPU RISC hiu nng cao: Ch cn 35 lnh my : - Tt c cc lnh u thc hin ch trong 1 chu k lnh, tr cc lnh nhy Tc hot ng: - DC 20 MHz tn s u vo (clock input) - DC 200 ns cho mt chu k lnh Ngt 8-Level Deep Hardware Stack Csac ch a ch: Direct, Indirect v Relative Cc c im c bit ca vi iu khin: Giao ng ni chnh xc lp bi nh my 1% - Kh trnh lp tn s t 8 MHz xung n 31 kHz - Tinh chnh bng phn mm

- 1,000,000 ln ghi vo EEPROM - Flash/Data EEPROM sng ti hn 40 years G ri trong chip (In-Circuit Debugger (on board)) Tiu th nng lng thp: Dng ch ngh (Standby Current): - 50 nA @ 2.0V Dng lm vic (Operating Current): - 11A @ 32 kHz, 2.0V, - 220A @ 4 MHz, 2.0V Dng vi Watchdog Timer: - 1A @ 2.0V, typical Cc ngoi vi: 24/35 chn vo/ra (I/O) kh nng kim sot hng : - Dng ti trc toeesp cho n LED - Thay i chc nng ngt chn chip - Kh trnh tng chn chip Module vi cc b so snh: - 2 b so snh tng t - Kh trnh in p chun (CVREF) module (% of VDD) - in p chun c nh (0.6V) - C mch lt kiu SR lm thanh cht - C cng cho b m ngoi ni vo cho php m B bin i ADC: - phn gii 10-bit vi 11/14 knh Timer0: B m 8-bit (Timer/Counter) kh trnh gi tr t l chia t trc (Programmable Prescaler) Timer1 tin tin: - 16-bit timer/counter kh trnh gi tr t l chia t trc - C cng cht ni tn hiu t bn ngoi - B giao ng tinh xo 32 kHz Timer2: 8-bit Timer/Counter with 8-bit Period Register, Prescaler and Postscaler Enhanced Capture, Compare, PWM+ Module: - 16-bit Capture, max. resolution 12.5 ns - Compare, max. resolution 200 ns - 10-bit PWM with 1, 2 or 4 output channels, programmable dead time, max. frequency 20 kHz - u ra ca iu ch PWM cho iu khin li Module nhn, so snh, iu ch PWM: - 16-bit Capture, max. resolution 12.5 ns - 16-bit Compare, max. resolution 200 ns - 10-bit PWM, max. frequency 20 kHz Module USART: - H tr kt ni RS-485, RS-232, v LIN 2.0 - T ng pht hin tc truyn thng - T ng tr li hot ng khi pht hin bit START Lp trnh truyn thng ni tip qua 2 chn ca chip (In-Circuit Serial ProgrammingTM (ICSPTM)) Module truyn thng ng b ch (Master Synchronous Serial Port (MSSP) Module) h tr kt ni 3 dy SPI (vi c 4 ch lm vic) v kt ni I2C c Ch/t vi mt n a ch ( Master and Slave Modes with I2C Address Mask)
95
Chng 3: Cc thnh phn phn mm ca h thng nhng

Do hun h gio trnh, cc h ng d n hai thc v thit vi cc d ng chip ny hng a vo ti liu Khi trin hai tm c ti liu v lm theo h ng d n c a nh cung c p Thng th ng t nh cung c p c cc thit m u v cng c pht trin (Cch lp trnh, cng c n p ch ng trnh vo chip) h tr nghin cu v trin hai ng dng. 2.5 B NH V THIT K B NH B nh l phng tin lu tr thng tin bao gm chng trnh v s liu trong h thng my tnh. Phn gii thiu chung ny cp tng quan v nhng khi nin c bn nht v b nh. Bng sau y cho mt s thng tin c bn v b nh trong my tnh:
2.5.1 Mt s thng s chnh ca mch nh di ca nh: di ca nh cho bit s bit cha trong nh, c th tnh bng bit, byte (8 bit), t (16 bit), t p (32 bit) hay t kp (64 bit). Dung lng (capacity) ca mch nh xc nh s bit hay byte hay t cc i m mch nh c th cha. Gi s mch nh c n bit a ch u vo v mi a ch (hay nh) di l m bit, nh vy mch nh c dung lng 2n x m (bit). n v o dung lng b nh thng thng nht l: Byte(B), KiloByte (1KB=210B), MegaByte (1MB=220B), GigaByte (1GB=230B), TetraByte (1TB=240B)... Thi gian thm nhp (Acces Time) l thi gian t thi im p a ch ti BUS a ch ti khi khi ni dung ca nh c a ra BUS s liu, k hiu l tA , thi gian ny ph thuc vo cng ngh ch to v cu trc mch nh. Chu k c (Read Cycle) l thi gian k t khi p a ch c nh cho n khi c th p a c nh tip theo, k hiu l tRC. l thi gian ngn nht gia hai ln c mt nh. Chu k ghi (Write Cycle) l thi gian k t khi p a ch ghi nh cho n khi c th p a ghi nh tip theo, k hiu l tWC. l thi gian ngn nht gia hai ln ghi mch nh. 96

Trng thi i tW (wait state) l s CPU Clock chen vo chu k c/ghi thch ng vi mch nh do tA ca mch qu di. Ni cch khc nu dng mt module nh chm cho my tnh nhanh, cn ng b vi hot ng ca CPU m bo my chy n nh th cn thm mt vi tW, mi tW = 1 T clock ca CPU., Trn mi chip DRAM u c ghi cc thng s k thut cn cho thit k, v du: DRAM Hitachi HM51W17400BS t chc nh sau: 4M x 4 bits, 2K refresh, Extended Data Out (EDO), Speed (tA )= 60ns, Supply = 3.3 Volt. C th xem v iu chnh thng s ny trong BIOS ca cc PC. Tn s ca mch nh l lng thng tin ln nht c th c hay ghi vo mch nh trong thi gian 1 giy. f = 1/tM Trong tM = Max (tRC, tWC ) Phn t nh Phn t nh thng thng l mt mch in c th ghi li v lu gi mt trong hai gi tr ca mt bin nh phn, hoc 0 hoc 1, c gi l bit. Trn mch in di y, trn dy D1 s khng c in p (do cng tc m), trong khi dy D2 c in p (v cng tc ng, hay thng qua diode mc theo chiu thun), gn bng gi tr ngun nui Vcc, tng ng vi bit D1 = 0 v bit D2 = 1.
Mch lt (flip-flop) RS (cn gi l triger RS) ng b l mt mch c kh nng lu gi cc gi tr 0 hoc 1 li ra. C th dng RS Flip-Flop lm mt mch lu gi tn hiu vo R bng cch cht d liu li ti u ra Q. Cc hng ch to thc hin mch ny bng cng ngh cao, nn kch thc v cng nh, c th c hng nhiu triu phn t nh trn mt din tch 1mm2. Cc vi mch nh thng thng c ch to vi di t nh v s lng t nh c nh. Hnh m t: - Dng Flip/flop RS, hay D nh 1 bit, thch hp d ch to b nh tnh tnh (Static). - Cc u vo/ra cn thit ca mt nh, hay mt chip nh, hay mt module nh (ROM hay RAM): a ch (tp cc a ch p vo), cc tn hiu ghi (WR/)/c(RD/), chn chip/module CS (Chip Select) v u ra/vo d liu.
97
Hnh 2.37 M hnh u vo/ra ca phn t nh n v nh n v nh l cc gi tr qui c trong k thut my tnh, c th c cc loi nh sau: - Nh 1 bit, - Nh vi bit : 4 bit hay 8 bit (cn gi l 1 byte); - Mt t (word) 16 bit - Mt t p (double word) 32 bit - Mt t di 64 bit to c mt t nh ca b nh, tc l t nh c di (s bit trong mt t) chun (theo chun IBM l 8 bits), trong mt s trng hp nht nh cn phi tin hnh ghp cc chip nh li vi nhau. cho ta khi nim v kh nng to mt t nh c bn (byte) khi t nh ca chip nh l 1bit, 2bits v 4 bits. Trong trng hp di t nh ca chip nh l 8 bits, vic lin kt l khng cn thit.
Thng thng di mt n v nh ph thuc vo loi CPU c kh nng x l, v d CPU 8 bit nh Intel 8085, Motorola 6800 x l ti a 8 bit song song. Ngy nay cc CPU a nng trong PC x l 32 bit v 64 bit. 98
2.5.2 Phn loi b nh Ni chung, b nh c phn loi theo mt vi thuc tnh. Sau y l mt s cch phn loi b nh: Theo chc nng b nh c chia thnh hai lai: - B nh trong ( b nh chnh) - B nh ngoi. ( b nh ph) Da trn thi gian ghi v cch ghi b nh trong c th chia thnh: - B nh c nh - B nh bn c nh - B nh c/ ghi
Hnh 2.38 Phn loi b nh a. B nh c nh ROM (Read Only Memory): B nh c ni dung ghi sn mt ln khi ch to c gi l b nh c nh v c k hiu l ROM. Vic ghi c thc hin bng mt n. Mt phn t nh trong ROM thng n gin hn nhiu so vi mt mch lt trong b nh c /ghi, v trng thi ca n c nh. Chng trnh iu khin ca hu ht cc h vi tnh c gi trong ROM. b. B nh bn c nh EPROM (Erasable Programmable Read Only Memory) y l b nh xa c bng tia cc tm v ghi li c. S ln xa v ghi li khng hn ch. Chng c thi gian ghi ln hn rt nhiu so vi b nh oc/ghi. Di tc dng ca tia cc tm tt c cc nh b xa cng mt lc, tr v gi tr =1, khi xa mch nh phi c a ra khi h vi tnh xa. iu thun tin b nh bn c nh cng nh ROM, l b nh tuy bt bin khi 99

dng nhng vn c th ghi li c. Mt b nh bt bin l b nh c ni dung khng b mt khi ngun in b ngt. EEPROM (Electrical Erasable Programmable Read Only Memory EEPROM cng tng t EPROM, c th ghi c nhiu ln, c ngha l ghi li v s dng li, nhng EEPROM khng xo bng tia cc tm m bng xung in nn khi xa vn trong mch in. Cc loi b nh ROM:
Hnh 2.39 Cc loi b nh ROM c. B nh c/ ghi RAM (Radom Access Memory) kiu truy nhp ngu nhin, ch cn c a ch p t, v tr no khng quan trng, s truy nhp c ni dung a ch tr ti. B nh c th ghi v c nhiu ln, vi thi gian ghi ngn c vi chc n vi trm nano giy. Trong cc h vi tnh, b nh c/ghi c s dng ct gi chng trnh (h iu hnh, ng dng), kt qu trung gian. Cc loi RAM:
100
Hnh 2.40 Cc loi RAM SRAM (Static RAM) nh tnh SRAM l b nh c/ghi c nguyn l hot ng tnh: ghi vo mt gi tr v tn ti cho ti khi ghi gi tr mi. Khi mt in s mt ni dung. B nh c/ghi tnh c cc nh cu to tng t nh mch lt. SRAM khng cn iu khin phc tp nh DRAM, tc nhanh hn (tA = 10 ns), tin cy hn nhng gi thnh tnh theo bit t hn DRAM, c s dng lm b m cache trong cc b vi x l hay my vi tnh. Bit nh c to bi Flip-Flop. V d cho 1 bit SRAM: Trn hnh bn l s nguyn l mt mt nh ca RAM tnh, mch nh s dng 6 transistor. RAM tnh c ch to theo cng ngh ECL (dng trong CMOS v BiCMOS). Mi bit nh gm c cc cng logic vi 6 transistor MOS.
1 phn t RAM tnh 101

V d t chc mt Chip RAM 32Kx8 bao gm: - Ma trn cc nh, hay byte nh (khi hng x ct); - a ch truy nhp vo nh hay byte nh (address lines); - Bus v khuych i bus d liu c ra hay ghi vo cc /byte nh (I/O lines) - Tn hiu iu khin c/ghi (READ/WRITE) (CS/, WE/, OE/).
Hnh 2.41 1 chip RAM 32K x 8 (32K byte) Lnh vc s dng SRAM: Do gi thnh cao, mt ch to (transistors/1 bit ) cao, tc nhanh, tin cy, d thit k cho ng dng, nn Trong my tnh SRAM thng dng nh RAM cache. Trong cc thit b in t s, c bit trong cc vi iu khin ca HTN , SRAM c s dng ph bin bi cc tnh nng nn trn. Hn na cc HTN khng cn dung lng b nh ln nh my tnh ph thng. DRAM (Dynamic RAM) RAM ng Hnh di l s mt nh RAM ng c to t 1 transistor v 1 t in. RAM ng dng k thut MOS. Mi bit nh gm mt transistor v mt t in k sinh. Vic ghi nh d liu da vo vic duy tr in tch np vo t in v b mt dn theo thi gian. Do vy cn khi phc li d liu, gi l lm ti (refresh). Qui trnh lm ti din ra lin tc, t ng theo chu k (v d khon 2s, hay khc ty dung lng v cng ngh ch to), v th gi l RAM ng. Vic lm ti c thc hin vi tt c cc nh trong b nh. Cng vic ny c thc hin t ng bi 102

mt vi mch lm ti. B nh DRAM chm, d ch to, mt cao/n v din tch, ph hp cho ch to RAM, r tin hn SRAM. i li iu khin phc tp.
Hnh 2.42 Phn t DRAM
103
104
Cc cch ghi/c/lm ti ca DRAM Khi thit k DRAM d vo c t ca CAS/ v RAS thit k logic iu khin Cc loi DRAM s dng trong my vi tnh PC 1. SDRAM (Vit tt t Synchronous Dynamic RAM) c gi l DRAM ng b. SDRAM gm 3 phn loi: SDR, DDR, v DDR2. o SDR SDRAM (Single Data Rate SDRAM), thng c gii chuyn mn gi tt l "SDR". C 168 chn. c dng trong cc my vi tnh c, bus speed chy cng vn tc vi clock speed ca memory chip, nay li thi. o DDR SDRAM (Double Data Rate SDRAM), thng c gii chuyn mn gi tt l "DDR". C 184 chn. DDR SDRAM l ci tin ca b nh SDR vi tc truyn ti gp i SDR nh vo vic truyn ti hai ln trong mt chu k b nh. c thay th bi DDR2. o DDR2 SDRAM (Double Data Rate 2 SDRAM), Thng c gii chuyn mn gi tt l "DDR2". L th h th hai ca DDR vi 240 chn, li th ln nht ca n so vi DDR l c bus speed cao gp i clock speed. 2. RDRAM (Vit tt t Rambus Dynamic RAM), thng c gii chuyn mn gi tt l "Rambus". y l mt loi DRAM c thit k k thut hon ton mi so vi k thut 105

SDRAM. RDRAM hot ng ng b theo mt h thng lp v truyn d liu theo mt hng. Mt knh b nh RDRAM c th h tr n 32 chip DRAM. Mi chip c ghp ni tun t trn mt module gi l RIMM (Rambus Inline Memory Module) nhng vic truyn d liu c thc hin gia cc mch iu khin v tng chip ring bit ch khng truyn gia cc chip vi nhau. Bus b nh RDRAM l ng dn lin tc i qua cc chip v module trn bus, mi module c cc chn vo v ra trn cc u i din. Do , nu cc khe cm khng cha RIMM s phi gn mt module lin tc m bo ng truyn c ni lin. Tc Rambus t t 400800MHz. Rambus tuy khng nhanh hn SDRAM l bao nhng li t hn rt nhiu nn c rt t ngi dng. RDRAM phi cm thnh cp v nhng khe trng phi cm nhng thanh RAM gi (cn gi l C-RIMM) cho . d. B nh ngoi SAM (Sequencial Access Memory) SAM l b nh ngoi thm nhp trnh t. Thi gian thm nhp ph thuc vo v tr ca thng tin trn phng tin mang tin. V d bng t (Tap Cartridges) dng nh thit b lu tr d liu ca my vi tnh. DAM (Direct Access Memory) DAM cho php thm nhp ti bt c vng d liu no cn. Thi gian thm nhp ph thuc vo v tr ca thng tin trn phng tin mang tin. V d thit b a cng, a mm thuc loi thit b ngoi vi kiu DAM. CD-ROM ( Compact Disk Read Only Memory) CD-ROM l loi thit b a da trn nguyn l quang laser. Dung lng ca a CDROM rt ln c kh nng cha ti 650 MByte. WORM ( Write Once Read Many) WORM cho php ngi s dng ghi thng tin mt ln c nhiu ln. Kiu a ny rt thun tin cho vic sao chp phn mm hay d liu khi trin khai cc ng dng tin hc. DVD ( Digital Versail Disk) DVD cho php ghi nhiu lp thng tin trn mt a lm cho dung lng ca a tng ln ng k so vi CD-ROM. Mt a DVD c th lu tr lng thng tin gp 17 ln mt a CDROM. Nhng mch nh bn dn hin nay c sc cha gii hn. Trong mt vi ng dng, mt b nh khng nhng cn c dung lng ln, m cn cn c t chc c s lng t v s lng bit trong mt t nh mong mun. Ni chung, trong b nh c nhiu vi mch nh c ni ghp li c di t v tng s t cn thit. Nhng vi mch nh bn dn c thit k sao cho c y nhng chc nng ca mt b nh nh: - Mt ma trn cc phn t nh, mi phn t cha mt bit - Phn mch logic gii m a ch cho nh 106

- Phn mch lgic cho php c/ghi c ni dung ca nh - B m vo, b kch ra - Phn mch m rng a ch 2.5.3 Phn cp b nh M hnh phn cp b nh:
Phn cp b nh c th hin trn : Quan st h thng nh t CPU ra ngoi ta c cc thnh phn nh sau: 1. Cc thanh ghi a nng cha mt ton hng hay kt qu trung gian, c iu khin bng phn cng 2. B nh m Cache cha mng lnh v s liu c s dng trong thi gian gn nht, c iu khin bng phn cng v chng trnh. B nh cache t gia CPU v b nh chnh. Cache trong CPU (cache L1), cache ngoi CPU (L2): B nh cache cha mt phn bn sao ca b nh chnh. Khi CPU thm nhp vo d liu n a a ch ti b iu khin Cache, sau mt trong hai qu trnh s xy ra. - Trng (cache hit): nu a ch tm thy trong Cache - Trt (cache miss): nu a ch khng c trong Cache Khi trt mt khi nh t b nh chnh s c a vo thay th cho mt ng (khi) ca Cache. ng no s c chn thay da trn hai nguyn l sau: - Cc b theo thi gian: nu CPU thm nhp vo mt nh th c xc sut cao n s thm nhp nh trong tng lai. - Cc b theo khng gian: nu CPU thm nhp vo mt nh th c xc sut cao n s thm nhp cc lnh v d liu t st cc v tr trong tng lai. Trng hp ghi vo Cache d liu s c ghi vo b nh chnh, ta phn bit hai trng hp sau:
107

- Khi ghi vo Cache th ng thi ghi vo b nh chnh, phng php ny gi l ghi xuyn (Write through) - Khi ghi ch ghi vo b nh Cache, d liu t Cache s c chuyn vo b nh chnh ti mt thi im thch hp sau (v d khi chuyn d liu t b nh chnh ra thit b ngoi vi). Vic nh x gia b nh Cache v b nh chnh c th t chc theo phng php khc nhau: - Cache nh x trc tip (Direct mapping cache) - Cache nh x lin kt ton phn (Full associative mapping cache) - Cache nh x lin kt cm (Set associative mapping cache) Ni dung v b nh Cache s c nghin cu k hn trong cu trc my II 3. B nh trong (b nh chnh) cha chng trnh v s liu ang thc hin 4. B nh ngoi lu tr chng trnh v s liu vi khi lng ln. N cng cha phn nh o, khi my tnh chy trong ch a ch o. Nu nh s phn cp theo gi tr tng dn t trong CPU ra ngoi, ta c nhn xt sau: - Thi gian thm nhp ca b nh c mc phn cp cng thp th cng nh tAi < tAi+1 - Gi thnh tnh theo bit ca b nh c mc phn cp cng thp th cng cao ci > ci+1 - Dung lng ca b nh c mc phn cp cng thp th cng nh Si < Si+1
Hnh 2.43 M hnh hot ng ca RAM cache 2.5.4 T chc b nh vt l v thit k b nh
108

T chc b nh cho mt h my vi tnh ph thuc khng ch vo mt h c th, m cn ph thuc vo cch b tr thun li bn trong h thng. Trc ht, hy lm quen vi cc khi nim chip nh v t nh phn tch vn t chc vt l mt b nh, sau m rng khi nim t chc theo quan im ca ngi lp trnh (t chc logic). Cc chip nh c sn xut di nhiu kch c v dung lng nh, t chc t nh khc nhau, ph thuc vo th loi v cng ngh ch to. Chip nh l mt vi mch c th, c b tr cc chn c bn nh v di. Cc chn ca mt chip nh thng thng gm cc li vo ca BUS a ch, li d liu, cc chn iu khin chn chip, ghi/c v cc chn ngun. V d mt RAM tnh 1Kx4 (1024 t, mi t c di 4 bit:
Hnh 2.44 S v ngoi mt vi mch (chip) nh (pin-out) Tu theo tng chip, s lng chn a ch v s lng chn d liu c th khc nhau ph thuc vo di t nh v dung lng ca chip nh. di t nh ca chip nh c th l 1bit, 4 bits hoc 8 bits, trong khi s chn a ch c th t 10 tr ln tu thuc vo dung lng ca chip nh. Trong trng hp di t nh ca chip l 1 bit, ta cn phi ghp song song 8 chip to thnh 1 byte, ghp song song 16 chip to mt t word 2 bytes). Ngy nay, vi cng ngh chip mt cao, thng 1 chip nh c th c dung lng rt ln, v d 256 x 1 Mb/Chip, 512 x 4 Mb/chip, 1 Gb/chip. Nh c th to ra 1 thanh RAM c dung lng ln nh PC hin ang s dng. Vn t chc logic ca b nh l mt chng mc phc tp vt ngoi tm ca gio trnh, nn y ch nu ln mt vi khi nim n gin ph hp cho ngi thit k. Thit k v nh l mt vic rt quan trng v rt cn thit trong vic xy dng mt h vi tnh. Cc v nh c thit k thng thng l EPROM, cc loi v nh RAM, t cc chip nh c sn. Thng thng, cc chp nh c chn l nhng chip thng dng trn th trng, c cc thng s k thut ch yu sau: a. Dung lng nh ca chip nh tnh theo n v Kbyte b. di t nh ca chp nh tnh theo s bits 109

c. Mt s thng s k thut khc nh thi gian truy xut, cng sut tiu tn ca chip v.vNhng thng s ny khng c nh hng ln n qu trnh thit k v xy dng v nh. d. Qui tc tnh ton khi thit k mt v (module) nh: Xc nh s chip nh, hoc s chip lin thng to c dung lng nh theo yu cu. Trong trng hp c th ca ra, cn 4 chip to c dung lng nh 32KB. Tnh theo cng thc: M= Q/D, trong Q l dung lng ca v nh. D l dung lng ca mi chip M l s chip nh hoc s chip lin thng cn thit. Xc nh s dy a ch c s (tc l s dy a ch thp c ni trc tip vo chip nh hoc chip lin thng): S dy a ch m ph thuc vo dung lng nh ca chip nh hoc chip lin thng theo biu thc sau: 2m = D, trong D l dung lng ca chip nh, m l s dy a ch c s T s chip hoc s chip lin thng, xc nh s dy a ch cn thit to cc dy chn chip ring bit. Tnh theo cng thc: 2i = M, trong i l s dy a ch cn gii m xc nh cc tn hiu chn chip (CSi) cho cc chip nh hoc chip lin thng. M l s lng chip hoc s lng chip lin thng. Cc dy a ch cn li c s dng to tn hiu xc nh vng nh ca v nh trong khng gian nh (c gn cho v nh theo a ch u ca v nh theo yu cu). V d: Thit k RAM tnh (Static RAM) Gi s cn xy dng mt b nh kch thc 16Kbyte trn c s cc chp SRAM loi 16Kx1bit. Bng nh SRAM 16Kbyte c xy dng trn c s 8 chip SRAM loi 16K x 1bit, c c nh c di 8 bits (t nh c bn). lm c iu ny ngi ta sp t 8 chip SRAM loi 16K x 1bit sao cho mi chip ti mt v tr xc nh s m nhim lu tr bit d liu c trng s tng ng trong byte d liu. Cc ng tn hiu : A13 - A0 BUS a ch, cho 16K (16383) a ch CS: Tn hiu chn chip. Nu CS = 0 th truy nhp c chip W/R: Tn hiu iu khin ghi/c. W=0 (W/) iu khin ghi, ng thi iu khin cc vi mch 3 trng thi theo cc chiu In/Out Chn bng nh cn thm A14, A14=0 chn bng th nht, (A14=1 chn bng th 2).
110
Hnh 2.45 S khi chc nng bn trong chip 16K x 1 bit
Hnh 2.46 S thit k bng nh SRAM 16K x 8, vi Chip 16Kx1
111
V d thit k RAM ng (DRAM ) DRAM dng phng php dn knh np ln lt (2 ln) a ch hng v a ch ct vo m a ch. S thi gian di y cho thy nhng lu khi thit k vi DRAM.
Hnh 2.47 S khi chc nng ca 1 chip DRAM thng mi 4164Kb Tn hiu iu khin : - RAS/: khi RAS (Row Access Strobe) tch cc th a ch hng c np (cht li). - CAS/: khi CAS (Column Access Strobe) tch cc th a ch ct c np (cht li). 112

- WE/: WE = 0 iu khin ghi chip, WE = 1iu khin c chip. Vic xy dng b nh t cc chip DRAM c thc hin gn tng t nh vi SRAM, tuy nhin phi thit k mt logic iu khin to cc tn hiu RAS/ v CAS/ bn ngoi, sau ni ti cc chn RAS/ v CAS/ ca chip. V d ly DRAM MK 4164 l DRAM 64K bit trong 1 Chip. Gi nh s thit k RAM cho CPU 8085 vi RAM ti a 64 KB, s cn 8 Chip. Khi thit k cn tham kho ti liu c t ca Chip DRAM, nh ni DRAM phc tp hn khi thit k.
Hnh 2.48 Quan h cc tn hiu iu khin DRAM 4164x1 thng mi. DRAM 4164 c dung lng 64 Kbit/chip, c t chc kiu ma trn gm (256 hng x 256 ct). chn mt bit trong ma trn cn c a ch v tr hng v ct c hai b gii m hng v gii m ct xc nh. u vo cho mi b gii m cn 8 bit c 256 u ra, vy ta s phi hp cc dy a ch t CPU 8085, bao gm A7-A0 cho hng v A15-A8 cho ct. CPU pht a ch vo vi mch dn knh SN 74257, u ra ln lc s l A7-A0 cht vo DRAM bng xung RAS/ A15-A8 bng xung CAS/. Khi thit k Mch logic iu khin to RAS/ v CAS/ v WE cn s dng cc tn hiu iu khin ta CPU pht ra. c c 64KB, cn 8 chip ni trn.
113
Hnh 2.49 CPU 8080/8085 Module DRAM 64 KB ton phn d) Thit k ROM/EPROM Trong tt c cc h my vi tnh, thnh phn khng th thiu l ROM/EROM/EPROM, vi chc nng lu cc phn mm khng c mt i khi mt in. Cc phn mm ny ty vo lnh vc ng dng my vi tnh, c th l : Nu l my tnh vn nng, nh PC, s l chng trnh BIOS (Basic Input Output system) c chc nng lu cc device driver, cc thng s khi ng cc vi mch iu khin cc thit b ghp ni vo PC trn bo mch ch hay qua cc slot m rng, cc routine, subroutine, v phn m khi ng H iu hnh t thit b ngoi. Nu l cc thit b in ton, v d nh HTN, th cha phn mm h thng iu khin thit b v ng dng c th m thit b x l. Nh cp cc loi phn mm y rt a dng. V d: Xy dng module ROM c dung lng 32KB, s dng Chip 2764 8K x 8 bit, a ch u l 20000hex. Chng trnh ng dng np vo module ny. Thit k mt ROM, loi 2764 (8Kx8bit), Vi mch 2764 c thi gian truy xut vo khong 250ns ph hp vi cc b vi x l tc cao nh Intel 8MHz 8086-2 trong h thng ny 2764 hot ng khng yu cu trng thi "i" ( Wait state ). Vi mch 2764 hot ng trong ch d 114

phng (standby mode ) cho php gim cng sut tiu tn m khng tng thi gian truy cp . Dng in khi hot ng l 150mA ,khi ch d phng l 35mA gim 75%. Vi mch 2764 c thit k ch to da trn cng ngh HMOS -E tc cao, knh N. Mch t hp logic gii m chn a ch vng c thit k da vo thng s a ch u ca vng nh, l cc bit nh cao nht, c gi tr c th v khng thay i trong ton b qu trnh truy xut n cc v tr nh trong v nh. Mch t hp logic gii m tn hiu chn chip nh c u vo l cc bit a ch tip theo k t cc bit a ch c lp (tc l cc bit a ch c ni trc tip vo cc chn a ch ca chip nh). S lng bit a ch l li vo ca mch ny ph thuc vo s lng chip nh hoc s lng chip lin thng to nn t nh c bn, tun th cng thc 2i = M. truy nhp vo 8 K a ch /chip cn 13 ng da ch, t A12-A0 truy nhp vo mi chip trong 4 chip cn 2 dy a ch: A14-A13 xc nh vng a ch cn 5 ng a ch: A14-A19 ca 1MB u tin CPU x86 s dng 20 dy a ch cho 1 MB u tin:A19 A0:
A19 0 A18 0 A17 1 A16 0 A15 0 A14 X A13 X A12 x A11 x A10 x A9 x A8 x A7 x A6 x A5 x A4 x A3 x A2 x A1 x A0 x
Gi tr =1 l c nh, gi tr =X thay i (0 hay 1)
115

Hnh 2.50 Chip ROM 2764 thng mi a ch khi truy nhp module RAM ny: Chip # C0 C1 C2 C3 a ch u 20000 22000 24000 26000 a ch cui 21FFF 23FFF 25FFF 27FFF Dung lng 8K 8K 8K 8K
Gii m th nht c 5 u vo t A19-A15 v 32 u ra chn vng a ch. Vi gi tr: 00100 , chn vng a ch yu cu (20000-27FFF)hex = 32 K, s c u ra cho php gii m th 2 hot ng. Gii m th hai dng A13-A14 to ra 4 CS/ chn 4 chip, trong khi A12-A0 chn nh trong mi chip: Chn vng A19.A18.A17.A16.A15 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Chn chip A14 A13 0 0 1 1 0 1 0 1 Chip c chn theo A14 v A13 C0(8K byte th 1) C1(8K byte th 2) C2(8K byte th 3) C3(8K byte th 4)
A12A11. A0 0. . .. .
116
Hnh 2.51 S thit k ROM 32KB t 4 Chip 2764 Vi cc tng nh trn c th thit k cc loi b nh cn thit cho mt HTN. iu lu ch l: Loi b nh no (ROM hay RAM) s dng v dng cho mc ch g (BIOS, HH hay D liu,ng dng). Khng gian a ch s dng t u n u trong ton b khng gian a ch m CPU cho php. Cch truy nhp RAM ca loi CPU s dng (tuyn tnh, phn on, phn trang, tr trc tip, tr gin tip qua cc thanh ghi ). V d sau y l phn hoch a ch b nh mega u tin (0000:0000 10000:0000) trong PC chun:
117
Hnh 2.52 V d v cch phn b b nh trong my tnh PC Trong : F000:0000 n F000:FFFF cho BIOS (64K cao nht), a ch sau RESET: CS:IP=FFFF:0000 (tc FFFF0) l lnh u tin thc hin (JMP RESTART F000:E05B. a ch FFFF1 n FFFFF dnh ring 16 byte cao nht cho CPU. Phn Extended (t 10000:0000 tr ln) l ngoi MB u tin vi A20 kch hot !
118
119

2.6 GHP NI VI THIT B NGOI VI Nh cc phn trn cp. Sau khi thit k phn trung tm ca HTN vi CPU, RAM, ROM v vi mch to cc cng giao tip vi thit b ngoi, phn ny cp ti cc nguyn l c bn ca k thu ghp ni v cch to ra cc module ghp ni hp nht trn bo mch chnh hoc ko di qua BUS m rng. 2.6.1 Tng quan Trc khi i vo chi tit, cn bit mt s khi nim c bn ca k thut ghp ni. Cc phng thc a ch ca CPU: Cc CPU thng thng c 2 phng thc s dng a ch, l dng a ch truy nhp vo b nh, thng qua cc lnh my lin quan ti b nh, v mt s rt t lnh c bit truy nhp vo cc thit b (vi mch kh trnh) gi cc m iu khin ti cc thit b . Trong trng hp ny, CPU truy nhp vo thit b theo cng (port). Cng (port) c CPU gn cho mt hay vi a ch. CPU c th nhn cng nh b nh. Trong trng hp ny, ngi thit k phi qui hoch khng gian a ch ca b nh vi mt vng a ch dnh ring cho cc thit b. Trng hp th hai, CPU nhn thit b qua cch gn a ch danhf ring cho cng. Khi tip cn cng, CPU c mt vi lnh c bit truy nhp. a ch dnh cho cng khng nm trong khng gian a ch cho b nh. Cch a ch ha cng: Theo a ch b nh (Memory mapped Imput/Output). Qui hoch b nh s c mt vng a ch dnh cho thit b. Truy nhp cng s dng tt c lnh qui chiu vo b nh. im yu c bn ca phng thc ny l: khng gian b nh bi co li mt phn, iu ny c bit bt li vi cc CPU c s a ch cho b nh gii hn, thi gian truy nhp cng lu hn do cc lnh b nh cn nhiu CPU clock hn. V d vi CPU c 16 dy a ch (CPU 8080/8085), khng gian a ch cho b nh ti a l 65.535, hay 64KB, hy xem phn hoch sau y hnh dung m t ca Memory mapped Imput/Output: Thit b RAM Cho cc cng s dng (I/O ports) Sound controller (I/O ports) Phn b a ch 0000 - 7FFF 8000 - 80FF 9000 - 90FF Kch thc RAM 32 KB 256 bytes 256 bytes 2KB 120
Video controller/text-mapped display A000 - A7FF

RAM ROM
C000 - FFFF
16 KB
Theo a ch cho thit b (Imput/Output mapped Input/Output). Phng thc ny n gin v truy xut nhanh. Cc lnh in hnh c c php nh sau: Cho CPU 8080/8085: IN a_ ch_ port_in ] OUT a ch_ port_out] Khi thc hin lnh, [a ch port] s t trn c AD7-AD0 v A15-A8 v u ging nh nhau (doublicated). 8080/8085 ch cho ti a 256 cng. Vi CPU x86, dng 16 bit cho cng, do s cng s rt ln (65.535 cng). D liu trao i c th 8 bit/ln hay 16 bit /ln. Lnh c vo/ghi ra thng kt hp vi cc i AX v DX (hoc EAX v EDX). Trong src thng l DX cha a ch_ port_in] hay a ch_ port_out] v des thng l AL hay AX cha d liu c vo hay ghi ra t/ti cng ghp ni. Trong ch bo v (protected Mode hay Kernel Mode), ngi dng bnh thng khng s dng c lnh IN/OUT. Lnh thc thi: IN des, src OUT des, src V d cng chun cho bo mch v ngoi vi chun s dng trong PC: I/O address range Device 00 1f First DMA controller 8237 A-5 20 3f First Programmable Interrupt Controller, 8259A, Master 40 5f Programmable Interval Timer (System Timer), 8254 60 6f Keyboard, 8042 70 7f Real Time Clock, NMI mask 80 9f DMA Page Register, 74LS612 87 DMA Channel 0 83 DMA Channel 1 81 DMA Channel 2 82 DMA Channel 3 8b DMA Channel 5 89 DMA Channel 6 8a DMA Channel 7 8f Refresh a0 bf Second Programmable Interrupt Controller, 8259A, Slave c0 df Second DMA controller 8237 A-5 f0 Clear 80287 Busy 121

f1 f8 ff f0 f5 f8 ff 100 10f 110 1ef 140 15f 170 177 1f0 1f7 200 20f 210 217 220 233 278 27f 280 29f 2b0 2df 2e8 2ef 2e1 2f8 2ff 2e2 2e3 300 31f 300 31f 300 31f 320 323 330 331 340 35f 370 377 378 37f 380 38c 388 389 3a0 3a9 3b0 3bb 3bc 3bf 3c0 3cf 3d0 3df 3e8 3ef 3f0 3f7 3f8 3ff Reset 80287 Math coprocessor, 80287 PCjr Disk Controller Reserved for future microprocessor extensions POS Programmable Option Select (PS/2) System I/O channel Secondary SCSI host adapter Secondary Parallel ATA Disk Controller Primary Parallel ATA Hard Disk Controller Game port Expansion Unit Sound Blaster and most other sound cards LPT2 parallel port LCD on Wyse 2108 PC SMC Elite default factory setting Alternate Enhanced Graphics Adapter (EGA) display control COM4 serial port GPIB/IEEE-488 Adapter 0 COM2 serial port Data acquisition Prototype Card Novell NE1000 compatible Ethernet network interfaces AMD Am7990 Ethernet network interface, irq=5. ST-506 and compatible hard disk drive interface MPU-401 UART on most sound cards Primary SCSI host adapter Secondary floppy disk drive controller LPT1 parallel port Secondary Binary Synchronous Data Link Control (SDLC) adapter AdLib Music Synthesizer Card Primary Binary Synchronous Data Link Control (SDLC) adapter Monochrome Display Adapter (MDA) display control MDA LPT parallel port Enhanced Graphics Adapter (EGA) display control Color Graphics Adapter (CGA) COM3 serial port Primary floppy disk drive controller. Primary IDE controller (slave drive) (3F63F7h) COM1 serial port 122

cf8 cfc PCI configuration space
Ghi nhn trng thi Ghp ni l k thut thch ng v ng b hot ng trao i thng tin gia CPU v thit b ngoi vi, bao gm thch hp dng tn hiu (bin i, qui i mc nng lng) theo chun TTL ca my tnh. Qu trnh ny thun ty l thit k in t (s-s, analog-sanalog, s-analog). ng b hot ng c th thc hin theo cch din gii trnh t s xut hin ca cc tn hiu iu khin theo thi gian, hay thc hin kt hp vi phn mm iu khin. Vic kho st thng tin v trng thi hot ng ca thit b l rt quan trng. Thit b c th sn sng hoc khng/cha sn sng trao i d liu. ghi nhn ta gi l thng tin trng thi thit b , c th hin bi mt loi tn hiu mang thng tin trng thi. Qui trnh kho st trng thi trc khi thc hin trao i d liu gi l bt tay (hand shaking) v c th hin trong chng trnh iu khin thit b (device driver). M hnh ghp ni vo/ra M hnh ghp ni bao gm cc thnh phn sau y: Ghp ni thc hin qua BUS h thng hay BUS m rng, gi chung l BUS S dng cc vi mch thch ng ghp ni gia BUS v thit b ngoi (latch SN74773, SN 74244/245, Flip/Flop Type D SN 7474, gii m SN 74138, gate SN 7400, 3-state SN 74125, open collector SN 7403 . . Cc vi mch ny to thnh cng d liu trao i gia CPU v thit b i qua li. CPU truy nhp vo cc cng thc hin ng b qui trnh trao i d liu. Cc thit b ngoi, ghp vo bo mch my tnh, cung cp cc tn hiu cn thit thc hin ghp ni k thut.
H thng ng dy a ch (ADDRES BUS ) B vi x l trung tm (CENTRAL PROCESSING UNIT) H thng ng dy iu khin (CONTROL BUS) H thng ng dy d liu (DATA BUS)
Status
Ghp ni vo/ra (I/O)
STROBE
Thit bi ngoi
DATA in/out
Hnh 2.53 M hnh k thut ghp ni 123
Hnh 2.54 Cc kiu ghp ni 2.6.2 Ghp ni CPU ch ng Vo/ra do CPU ch ng cn gi l vo/ra iu khin bng chng trnh c chia thnh hai nhm: Vo/ra s liu bng chng trnh khng iu kin Vo/ra s liu bng chng trnh c iu kin (handshaking-i thoi) a) Vo/ra s liu hng iu in, iu hin bng ch ng trnh Vo/ra s liu khng iu kin c cc c im nh: - CPU chuyn s liu thng qua chng trnh - CPU gi thit TB vo/ra lun sn sng chuyn s liu - D liu c vo CPU qua cng sau lu li o b nh cho cc x l tip theo. - Vic chuyn s liu c thc hin gia cc thanh ghi ca CPU (ACC) v thanh ghi (cng ghp ni) ca TB vo/ra, sau lu li o b nh cho cc x l tip theo. B nh [CPU_ACC] [ Cng ] [Thit b] c vo:
124
Hnh 2.55 c d liu vo: D liu_t thit b vo ACC sau vo RAM V d ng dng: Khi kim sot nhit , thit b nhit lun c s liu o v x l. Trong trng hp ny ghp ni vi thit b nhit tr nn n gin. Tng t cho m hnh a d liu ra thit b. Lnh thc hin: IN [port_in] hoc IN , a ch_ port_in] Cc bc thc hin: - CPU a ra BUS a ch a ch cng port_in cho gii m, to CS/ m port_in. - CPU a ra BUS /k tn hiu IORD - S liu t vi mch 3-state chuyn vo BUS d liu v di tc ng ca tn hiu IORD/ v c a vo ACC ca CPU qua port_in 3 trng thi. - Thc hin chuyn ACC vo RAM. a ra: Lnh thc hin: OUT [ port_out] hay OUT [ port_out], AL
125
Hnh 2.56 a d liu t RAM vo ACC sau ACC ra thit b Cc bc thc hin: - CPU a ra BUS a ch a ch cng port_out cho gii m, to CS/ m port_out. - CPU a d liu cn ghi ra BUS d liu - CPU a tn hiu IOWR/ cht d liu, di tc ng ca tn hiu IOWR/ s liu c ghi vo thanh ghi cht, t thit b nhn d liu vi tn hiu RD/ ca thit b. Ghi nhn cn bn y l CPU v tr trung gian ca qui trnh nhn hay gi d liu. Chi ph mt cng cho mi cu hnh. Mi ln trao i 1 byte. C ch ny c hn ch v CPU ra lnh c (IORD) hay ghi (IOWR) m khng kim tra xem thit b vo/ra c sn sng gi hay nhn s liu hay cha do khi ng dng cn phn tch hot ng ca thit b c gii php ghp ni ng mc ch. b) Vo/ra s liu c iu in, iu hin bng ch ng trnh Khi ghp ni vi cc thit b m thit b cn c thi gian hon thnh mt x l (tc v), trong qa trnh ghp ni, CPU cn c ghi nhn trng thi sn sng ca thit b nh gi v ra quyt nh tip theo.Qu trnh kim tra trng thi i khi phi thc hin mt vi ln trc khi quyt nh tip tc hay t b trao i d liu vi thit b. Ti sao ? Nu thit b lm vic tt, mi chuyn tri chy, nhng nu thit b hng hc, chng trnh iu khin khng th c ch thit b sn sng mi c, chu trnh phi kt thc. Qui tc ny gi l i thoi, hay mc ni c iu kin l vy. V mt thc hin, y cn t nht 2 cng: 1 cng c trng thi thit b, cng kia trao i d liu vo hay ra. Trng thi thng thng mc d n gin ch cn 1 bit th hin, v d STATUS=1, thit b sn sng , v ngc li. Tuy nhin c nhiu trng hp trng thi c th l tp hp ca vi bit. V d khi ghp vi cng truyn thng d b (UART), c n 5 bit phn nh trng thi ca UART. Cc bit trng thi c ni vo BUS d liu qua cc mch 3-trng thi v c iu khin bng lnh. 126

c vo c i thoi:
Hnh 2.57 Trao i d liu c vo c iu kin Cn CS0/ c trng thi READY ca thit b qua port_status, gi nh ni vo D0 ca BUS d liu. Cn CS1/ c d liu qua port_in, hp thnh t Flip/flop, cng 3-state, ni vado bit D0 ca BUS d liu. Cc bc thc hin: - CPU a a ch port_status ra BUS a ch, vo gii m, to CS0, c STATUS, gi tr bit READY ti D0. (IN port_status) - CPU kim tra gi tr ca READY. - Nu READY=0, quay li c STATUS NuREADY=1, CPU c d liu vo ACC (IN port_in) - Thc hin lnh ct d liu vo RAM Lu iu khin:
127
START routine: C2=n2
C = n1
C=0 ?
c STATUS Port_status
C = C-1
READY ? D0=1
c d liu_ Port_in, Chuyn d liu vo RAM
C...s m ln kim tra trng thi t/b C2...s byte trao i vi t/b
C2=C2-1
C2=0 ?
Kt Thc
Hnh 2.58 Lu iu khin c d liu v c iu kin BI TP: 1.a ra c i thoi: Thit k mch ghp nia d liu ra; Vit chng trnh iu khin qu trnh a d liu ra.
c) Quay vng (polling) Trong phng php vo/ra c i thoi, nu thit b vo/ra cha sn sng nhn hay gi s liu th CPU phi ch cho thit b sn sng. Ni cc khc phng php ny gy lng ph thi gian ca CPU. Khi h thng c nhiu thit b ghp vo, cn c chin thut gin ti a thi gian ch trn mt thit b. Cch n gin l dng phng php quay vng hi trng thi cc thit b vo/ra. V nguyn tc ch hi 1 thit b mt ln, nu thnh cng, thc hin trao i d liu, cn khng 128

chuyn sang thit b khc. Chng trnh s t chc vi nhng qui t ti u no , v d nh bt u vi thit b c nc u tin cao nht v gim dn.
Thc hin lnh CALL: START Polling routine:
Thit b #1 READY ?
Call Service routine thit b #1
Thit b #2 READY ?
Call Service routine thit b #2
Thit b #n READY ?
Call Service routine thit b #n
Kt Thc polling thc hin lnh RETURN()
Hnh 2.59 Lu iu khin c d liu kiu quay vng 2.6.3 Ghp ni I/O ch ng
a)
Ngt (Interrupts)
Nhng hn ch ca phng php vo/ra bng chng trnh c khc phc bng phng php vo/ra bng ngt. Trong phng php ny thit b vo/ra ch ng khi ng qu trnh vo/ra s liu. Khi s dng vi c ch ngt, phi qun trit tng v ngt khi gn cho thit b, l thit b s c nhu cu trao i d liu, tuy nhin thi im nhu cu xut hin th khng th bit trc c. chnh l u im vt tri m ngt mang li: Thit b ch ng vo bt c lc no, CPU khng b rng buc vi thit b, do chi ph thi gian nh phng php CPU ch ng gim i rt nhiu. Ngt cn mang mt ngha khc l tnh tc thi nu coi ngt l biu hin ca mt s kin. Trong cc HNT nhng vi x l theo thi gian thc, y chnh l im ch 129

yu. C hai hnh thc ngt, thng thng vi thit b, ta ni n ngt cng, tc l ngt t mt tn hiu pht sinh t thit b. Ngoi ra cn c khi nim ngt mm, s dng mt nguyn l m h iu hnh h tr thng qua lnh my tnh, gip to ra s chuyn x l (chng trnh) tm thi n mt x l t xut. Xt v x l thun ty, ngt cng hay ngt mm u c tc dng nh nhau. Ngt cng hay quay vng ? Li th ca ngt cng l thi gian s dng CPU rt hiu qu, CPU phn ng tc th khi c ngt, trong khi dng hi p quay vng (polling) chi phi ngiu thi gian ca CPU. Ngt cho nhiu gii php phn ng ca CPU vi cc s kin bn ngoi. Tuy nhin, to v x l ngt phc tp hn v, trong khi vit trnh cho polling n gin hn. Mt trong cc ng dng quan trng ca HTN l ch standby v nh thc bng wake-from-sleep interrupt.Another benefit of using interrupts is that in some processors you can use a wake-from-sleep interrupt, c bit khi h nui bng pin. Cc khi nim vi ngt: ISR Interrupt vector Interrupt mask NMI Asynchronous event Context switching Interrupt Service Routine- Dch v ngt: m x l cho ngt. a ch ca ISR trong b nh h thng. Mt n kim sot cho php hay cm mt ngt hot ng Ngt khng th kim sot c, lun hot ng. S kin c th xy ra bt k thi iimm no, c tnh ngu nhin. Qui trnh bo v / khi phc ni dung cc thanh ghi ca CPU, hay d liu trc / sau khi x l ngt. on code ny nng trong code ca ISR.
Mt h ngt c bn:
130
Ngun pht sinh ngt (Input sources) L cc tn hiu ngt t cc thit b trong hay ngoi bo mch, v d t ADC/DAC, t UART , t cc cng ghp ni, DMAC cc tn hiu c th kch hot dng mc (level) hay sn ln hay xung ca tn hiu ngt (edge). CPU phn ng vi tn hiu qua lp trnh. C trng thi ngt (Interrupt flags) Mi ngt kt hp vi c, ch cn 1 bit, bo trng thi cuiar ngt . Cc bit thng tp hp trong 1 thanh ghi c ngt (interrupt register hay interrupt flag) c/ghi c. CPU c bit ngt xut hin, v ghi (xa) sau khi x l cho ngt . Mt n ngt (Interrupt mask) Mi ngt kt hp vi 1 bit ca thanh ghi mt n. Lp trnh cc bit ca thanhg ghi s cho php hay cm ngt tng ng kch hot. Phn loi kiu ngt:
131
Hnh 2.60 Cc kiu ngt Ngt mm
Ngt mm thc cht thc hin mt li gi hm c bit c kch hot bi cc ngun ngt l cc s kin xut hin t bn trong chng trnh v ngoi vi tch hp trn Chip. V d nh ngt thi gian, ngt t thit b nh ADC/DAC, C ch ngt ny cn c hiu l loi thc hin ng b vi chng trnh v n c kch hot v thc thi ti cc thi im xc nh trong chng trnh. Hm c gi s thc thi chc nng tng ng vi yu cu ngt. Cc hm thng c tr bi mt vector ngt m c nh ngha v gn c nh bi nh sn xut Chip. V d nh h iu hnh ca PC s dng ngt s 21hex gn cho ngt truy nhp c d liu t a cng v xut d liu ra my in. Ngt cng
Ngt cng c th c xem nh l mt li gi hm c bit trong ngun kch hot l mt s kin n t bn ngoi chng trnh thng qua mt cu trc phn cng (thng c kt ni vi th gii bn ngoi qua cc chn ngt). Ngt cng thng c hiu hot ng theo c ch d b v cc s kin ngt kch hot t cc tn hiu ngoi vi bn ngoi v tng i c lp vi CPU, thng l khng xc nh c thi im kch hot. Khi cc ngt cng c kch hot CPU s nhn dng v thc hin li gi hm thc thi chc nng phc v s kin ngt tng ng. Trong cc c ch ngt khong thi gian t khi xut hin s kin ngt (c yu cu phc v ngt) ti khi dch v ngt c thc thi l xc nh v tu thuc vo cng ngh phn cng x l ca Chip. T chc to ngt c th n gin nu CPU h tr nhiu u vo ngt v h thng khng cn nhiu ngt cng. V d nh trong CPU 8080/8085 c 4 ngt (RST7.5, RST6.5, RST5.5 v TRAP) v 8 ngt mm (RST0 n RST7). Tuy nhin s thit b nhiu, s tn hiu ngt cng tng 132

ln, do c mt c ch qun l ngt hieehu qu hn, l c ch vector. Trong c ch ny CPU ch cn 1 u vo (INTR) v mt u ra (INTA) e nhn v tr li chp nhn ngt. Phn cng do cn thm mt vi mch h tr cho CPU, gi l vi mch iu khin ngt lp trnh c(Programmable Interrupt Controller), v d vi mch Intel 8259 vi 8 u vo ngt v 1 u ra. Mi mt ngt (mi thit b) cn c mt chng trnh x l ring, gi tn chung l chng phc v ngt (Interrupt Service Routine ISR). a ch ca mi ISR t trong mt vng b nh qui c, v d vi Intel CPU, l vng a ch t 00000-003FF (1024 byte), vng b nh ny gi l bng vector ngt, c 4 byte cho mt ngt (CS:IP), nn c 256 ngt. Bng vector ngt thuc vng RAM h thng. (Th ngh xem ti sao RAM, m khng ROM ?).
Hnh 2.61 Thit kt vi ngt cng che c INTR ca CPU Hy xem xt tin trnh ngt nh sau chy trnh: Khi cn trao i thng tin, thit b ngoi vi gi tn hiu yu cu ngt (Interrupt Request-IRQ) ti u vo INTR ca CPU. CPU s thc hin nt lnh hin ti v tr li bng tn hiu nhn bit yu cu ngt (INTA). Chng trnh chnh lc ny b tm dng (ngt) v CPU chuyn sang thc hin chng trnh con phc v ngt (thc thi ISR ca ngt ), tc l chng trnh con trao i thng tin vi thit b ngoi vi yu cu ngt. Sau khi xong cng vic phc v ngt, CPU quay v thc hin tip chng trnh chnh k t lnh tip theo sau khi b ngt.
133
Hnh 2.62 Vector ngt v chuyn x l ti ISR Cc tn hiu yu cu phc v ngt t mt thit b ngoi vi bt k c gi ti chn nhn yu cu ngt ca CPU c th thng qua mt khi iu khin ngt. Tu theo ngi lp trnh m yu cu ngt c c chuyn ti CPU hay khng (thng qua chin thut nhn v x l ngt vi cc lnh cho php ngt (EI) hay cm ngt (DI). Trong trng hp yu cu ngt c gi ti CPU, x l ca CPU gm cc bc sau: Qu trnh thc hin ngt: - CPU hot ng bnh thng - Khi thit b vo/ra sn sng chuyn s liu s gi yu ngt ti CPU bng tn hiu IRQ ti du vo INTR (Interrupt Request) ca CPU - CPU thc hin nt lnh ang thc hin trc khi tr li chp nhn ngt - CPU nhn v tm cch xc nh ngt v tr li thit b vo/ra bng tn hiu INTA (Interrupt Acknowledgement) - y PSW (Program State Word) v PC (Program Counter) vo ngn xp - Xo cc c IF (Interrupt Flag) v c TF (Trap Flag) 134

- TB vo/ra thng qua b iu khin ngt cho bit a ch ca chng trnh con phc v ngt ISR ca ngt . CPU np a ch ny vo PC. - CPU nhy n chng trnh con ISR v thc hin x l - Chng trnh ISR s y cc thanh s b thay i trong chng trnh con vo ngn xp. - Chng trnh ISR s thc hin vic chuyn s liu gia thit b vo/ra v b nh qua ACC ca CPU. - Sau khi chuyn s liu xong, CPU khi phc cc thanh ghi - Khi phc PC v PSW t ngn xp, tr v chng trnh chnh thc hin tip nhim v trc khi c ngt.
Hnh 2.63 T chc ngt vi iu khin ngt Nhng iu lu khi vit chng trnh ISR: nhng lnh u tin ca ISR thc hin l: y cc thanh ghi ca CPU vo STACK, Thc hin vic cm ngt trnh qui ngt nu cn, hoc cm cc ngt khc M x l ca ISR Khi phc cc thanh ghi ca CPU Khi phc li kh nng chp nhn ngt cho cc ngt tm cm Quay v (RETURN) chng trnh b gin on trc . Lp trnh ngt v ci t vector ngt l vic lm cn thn trng. Cc ngt t chc theo vector ng thi cng l theo mc u tin, nn khi thit k cn c tng r rng. V mc u tin v s dng mc u tin: NMI (Non Maskable Interrupt) l yu cu ngt tc thi, khng th cm hay cho php bng chng trnh. Ngt theo Vector Ngt mm dng lnh (INT) gi cc chng trnh phc v ngt ca h thng. 135

V d cc ngt h thng: ng h thi gian thc, bo li phn cng, bo mt ngun nui, bo li trong truyn tin Thng thng ta hay quan tm nhiu n p ng ca CPU vi s kin ngt v thi gian thc hin tc v ngt. y thi gian p ng ph thuc v quyt nh bi tc v kh nng x l ca phn cng cn thi gian thc hin tc v ngt ch yu quyt nh bi tc v ngt di hay ngn v do chng trnh quyt nh. V d: Thit k vi 8259, h tr 16 ngt cng:
Hnh 2.64 M rng s ngt vi 2 vi mch 8259 s dng 8259, cn nghin cu c t v phng php lp trnh cho vi mch ny. S cha c Chip select (CS/), cn ty vo thit k c th. b) Truy nhp trc tip vo b nh (Direct Memory Access-DMA) Trong cc phng php vo/ra trnh by trn c cc nhc im sau: 1) S dng phng php vo/ra iu khin bng chng trnh ta thy: - c d liu vo bng chng trnh phi chuyn s liu gia thit b vo/ra v b nh thng qua ACC: B nh [CPU_ACC] [ Cng ] [Thit b] Trong c hai bc cn thc hin: 1. [DATA_ghp ni_t thit b] ACC 2. [ACC] MEM 136

- Tng t khi ghi d liu ra thit b phi a ni dung ca nh ti TB vo/ra, cng phi qua 2 bc: 1. [MEM] ACC 2. [ACC] [DATA_ghp ni_ra thit b] Nh vy vic chuyn s liu gia thit b ngoi vi v b nh cn hai bc, tc chm. y ch tnh thm bc kim tra trng thi READY ca thit b. 2) Phng php vo/ra bng ngt bo m thit b vo/ra c phc v gn nh tc thi (trong thi gian ngn). Nhng trong chng trnh con phc v ngt, qu trnh chuyn s liu c thc hin bng lnh chng trnh nn tc trao i cng khng th cao c v khu ny cng khng khc g 1). Tuy nhin trong my tnh, vic phi trao i mt khi lng ln d liu gia b nh RAM v thit b ngoi khng th s dng 2 cch ni trn c. V d khi ghi/c a cng, cp nht cho video RAM to nh trn mn hnh l cc loi ng dng kiu nh vy. K thut vo/ra thm nhp b nh trc tip s khc phc cc nhc im trn. Bn cht ca k thut ny nh sau: khi cn trao i khi d liu gia RAM v thit b, th tc v ny phi xy ra nhanh nht c th v ch ph thuc vo kh nng ca thit b v phi thc hin hon ton bng c ch in t, khng s dng ti cc lnh my qua chng trnh. Ni vy c mu thun ? Hay ni cch khc lm c, Hy loi b tm thi CPU v nm ly quyn khng ch BUS h thng trong thi gian trao i d liu !. Qu trnh thit k ca gii php ny nh sau: Cn c mt vi mch kh trnh, c kh nng thay th CPU, to ra cc tn hiu ging nh CPU to (BUS a ch, BUS d liu, BUS iu khin) v kim sot BUS h thng trong sut thi gian thc hin DMA. C cc tn hiu i thai vi CPU (HRQ, HLDA), cc tn hiu i thoi vi thit b ngoi (DREQx, DACKx, ..). Vi mch nh vy gi l DMA Controller, hay DMAC, vi mch ph bin c tn Intel 8237A. S nguyn l nh sau:
Hnh 2.65 Nguyn l DMA Qu trnh thc hin DMA: 137

1) CPU lm vic bnh thng 2) Khi thit b ngoi vi mun chuyn s liu trc tip vi b nh th gi yu cu ti DMAC qua tn hiu DRQx ( DMA Reqest th x, mi DMAC c kh nng nhn 4 DRQ). 3) B iu khin DMAC chuyn yu cu ny ti CPU qua tn hiu HRQ: Yu cu CPU tch ra khi BUS h thng. 4) CPU thc hin nt chu k my ang thc hin, treo BUS v tr li DMAC bng tn hiu HLDA: Chp nhn v treo BUS. 5) DMAC tr li thit b vo/ra bng tn hiu DACKx, DMAC qun l BUS h thng v pht sinh cc tn hiu a ch ln BUS a ch, hng ti b nh, 6) Pht cc tn hiu iu khin: MEMRD/, MEMWR/, IORD/, IOWR/, thc hin DMA vo: c thit b/ghi b nh hay DMA ra: dc b nh/ghi ra thit b. 7) iu khin chuyn s liu gia b nh v thit b vo/ra, chy ng b theo BUS-clock. S liu chuyn gia b nh v thit b vo/ra thng l c mt khi, c di ty qua lp trnh. 8) Khi chuyn xong s liu DMAC a tn hiu TC hay EOP (Terminal Count, End of Operation-EOP) thnh tch cc bo mt qu trnh DMA kt thc (tn hiu TC ng vai tr mt ngt khi s dng thng bo cho CPU). DMAC treo BUS, DMAC hy HRQ. CPU hy HLDA, CPU tr li qun l BUS h thng. Chu k DMA hon tt. Qui trnh chy DMA xy ra rt nhanh, ch ph thuc vo kh nng trao i ca thit b. C mt vi th thut DMA xy ra trong my tnh, tham kho thm ti liu, v d Intel 8237 DMAC, hiu thm. DMA kt hp vi ngt bng tn hiu TC, hay EOP khi kt thc chu k DMA. V d ng dng: ghi c d liu RAM a cng, RAM NIC.
Hnh 2.66 DMA v hot ng ca CPU l c lp V du: Thit k vi DMAC: S dng Intel DMAC 8237 138

C hai phng php thc hin DMA: Cch nh m t, CPU trao quyn s dng BUD h thng cho DMAC; Cch th hai gi l DMAC ly ln chu k: DMAC tn dng nhng khon thi gian trong mt chu k BUS m khi CPU khng c truy nhp b nh, v d cc chu k CPU pht a ch cho cc chu k c hay ghi b nh). Mt khi DMA hot ng, c mt s cch trao i d liu sau y: Ch trao i n, Ch theo yu cu, Ch m rng cc vi mch DMAC theo a mc (cascade). Khi thit k vi DMAC xem chi tit hng dn cch ghp v lp trnh cho DMAC.
Hnh 2.67- Ghp ni DMAC-CPU 8085 139

2. CPU 8080/8085 3. DMAC 8237A 4. Latch 74LS373 cht a ch A15-A8 do DMAC pht ra a ln BUS h thng
140
Lu thi gian ca qui trnh DMA
141
Hnh 2.67 Lu DMA ghi d liu t RAM ra thit b ngoi
142

2.6.4 Cng vo/ra Khi ni v ghp ni ta hay cp ti khi nim cng. Thc ra cng y bao gn hai phn: l s dng cc mch in t lm thch ng cc tn hiu mang thng tin trong thit b k thut s ni chung v phn mm iu khin hot ng ca cng. gc hp nht trong thit k, cng phi do CPU qun l bi v cng c to thnh da vo kin trc ca CPU v thc hin bng lnh my tnh. Nh trnh by, CPU nhn cng theo hai cch: cng nh l mt nh (Memory mapped I/O), nh vy cng s chim mt phn trong khng gian a ch ca CPU. Hay CPU nhn cng theo kiu cng thun ty (I/O mapped I/O) v cng c khng gian a ch ring m CPU dnh cho cc hot ng vo/ra. Trng hp ny nu phn ghp ni khi thit k cc k thut ghp ni vo/ra. Cc cng nh vy gi l cng logic v dng iu khin cng vt l m n nh x ti. Cc cng vt l phi c m t k thut rt chi tit v n dng ghp ni cc tn hiu vt l (in, quang, t trng) vo my tnh. Cc cng ny thng thng trong cng nghip u c chun ha m bo tnh tng thch cho mi h thng, m mc ch l h tr cho vic truyn d liu gia cc thit b k thut s. Cng song song. Cng song song cho php trao i thng tin gia hai thit b s (PC, HTN) ng thi nhiu bit mt ln. V d, ng thi t 2 bit tr ln. Vic truyn thng c th n gin, nhng cng c th rt phc tp. V d, n gin ch cn thng qua mt s tn hiu i thoi ng b pht/nhn d liu. Mt trong cc cng song song ph bin trong PC l cng ni vi my in. Di y l cng song song ni ra my in trn PC (Standard Parallel Port (SPP)), tn u ni ra l DB25 vi ng ngha ngha cc chn ca cng.
Chn 1 2 3 4 5
Tn gi STROBE D0 D1 D2 D3
Hng d liu Li vo/ra, o Li ra (Output) Li ra Li ra Li ra
M t Byte c in ng d liu D0 ng d liu D1 ng d liu D2 ng d liu D3 143

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 D4 D5 D6 D7 ACK BUSY PE SLCT AF ERROR INIT SLCTIN GND GND GND GND GND GND GND GND Li ra Li ra Li ra Li ra Li vo (Input) Li vo, o Li vo Li vo Li vo/ra, o Li vo Li vo/ra Li vo/ra, o ng d liu D4 ng d liu D5 ng d liu D6 ng d liu D7 Acknowledge (Xc nhn) 1: My in bn 0: My in khng bn Bo ht giy SELECT (La chn) Auto Feed (T np) Error (Li) 0 : Reset li trng thi my in Select in Ni t Ni t Ni t Ni t Ni t Ni t Ni t Ni t
Hnh 2.68 Cng song song trn PC v gii ngha cc chn cng
Lu d thi gian m t nguyn tc ghp ni vi my in, trong (Ra) c ngha tn hiu ra t cng v(Vo) l tn hiu t my in.
Hnh 2.69 Lu cc tn hiu cng song song 144
a ch truy nhp cng: Address 3BCh - 3BFh Notes: a ch ny trc ay hay kt hp trn bo mach video. Khng h tr ch ECP addresses (Extended Capabilities Mode) Cho cng LPT 1 Cho cng LPT 2
378h - 37Fh 278h - 27Fh
Khi s dng cng song song a d liu vo, c th d dng cc tn hiu trng thi nh ACK, PE, BUSY, SELECT, cc cng c dng ty bin theo s kho lo ca ngi thit k. Hn ch ay l ch c th c vo 4 bit mt ln. cc PC hin i cng ny vn nng hn gi l cng hai chiu:
Hnh 2.70 Cng song song hai chiu Xem thm: http://www.beyondlogic.org/spp/parallel.htm#6 Cng ni tip. Trong khi cng song song c u im v s bit truyn v c th t tc rt cao, th im yu ca cng l khon cch kt ni. gii quyt vn ny phi s dng ti cng ni tip. Bn cht ni tip l phi trao i gia hai my vi nhau tng bit mt v lnh vc ng dng ca truyn thng ni tip li rt ph bin. Tuy nhin truyn ni 145

tip la rt phc tp, i hi thit k v c bit l qui trnh pht/thu, gi chung l giao thc truyn thng. Do y khng i vo chi tit c th ca truyn thng ni tip, c th thao tham kho thm cc ti liu khc: http://www.beyondlogic.org/serial/serial.htm#2 v http://www.lammertbies.nl/comm/cable/RS-232.html#pins. Trn PC c t nht 2 cng vi tn gi COM1 v COM2 vi chun RS-232. Chn cng ni tip (Serial) D25 v DB9
Hnh 2.71 u ni RS 232 cc loi DB9, DB 25 v DEC MMJ D-Type-25 Pin No. Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 D-Type-9 Pin No. Abbreviation Pin 3 Pin 2 Pin 7 Pin 8 Pin 6 Pin 5 Pin 1 TxD (Ra) RxD (Vo) RTS (Ra) CTS (Vo) DSR (Vo) SG (V my) DCD (Vo) Full Name (Transmit Data Serial). C liu pht ra t DTE (v duh PC, HTN) (Receive Data Serial). Nhn d liu t DCE v DTE (Request To Send). DTE sn sng pht d liu ra. (Clear To Send). DCE sn sng nhn d liu do DTE pht ra. (Data Set Ready). DTE sn sng nhn d liu t DCE. Signal Ground (Carrier Detect). kt ni vi DCE 146

t xa qua PSTN. Pin 20 Pin 22 Pin 4 Pin 9 DTR (Ra) RI (Vo) Data Terminal Ready. DCE mun pht d liu (Ring Indicator ). DCE bo c chung n t PSTN.
Mt s cng ni tip khc: RS-422 (H thng tc cao tng t RS-232 nhng dng tn hiu vi sai ) RS-423 (H thng tc cao tng t RS-422 nhng dng tn hiu kiu khng cn bng) MIL-STD-188 (chun qun s, ging RS-232 nhng cht lng t hn (tr khng, sn ln dc hn) EIA-530 (tc cao s dng chun cc thuc tnh v in cua EIA 423, chn ni ca RS422 hay RS-423,) EIA/TIA-561 Kt ni 8 v tr, khng ng b gia thit b d liu u cui (Data Terminal Equipment) v thit b mch d liu kt thc (Data Circuit Terminating Equipment ) dng trao i d liu nh phn ni tip. EIA/TIA-562 (Chun qui nh cho giao din kt ni s khng cn bng (Electrical Characteristics for an Unbalanced Digital Interface (low-voltage version of EIA/TIA-232) TIA-574 (standardizes the 9-pin D-subminiature connector pinout for use with EIA-232 electrical signalling, as originated on the IBM PC/AT)). Mt s cng hin i khc: USB (Universal Serial Bus) l cng ph bin dng trong cc thit b nhng, v d b nh flash ngoi dng vi PC. Cc thit b nhng trong mt t hp thit b ni vi nhau qua HUB trao i d liu Cng 1394 (cn gi l FireWire) cc nhanh t ti 800Mbps, cho php kt hp ti 63 thit b cng lc, cm l chy v cm/rt nng. Cc thit b nh camcorder truyn video vi PC t tc rt cao. Cng SI-P (Serial Interrface port - Programmer): y l mt cng rt c bit pht trin kt ni gia mt bo mch HNT ang pht trin vi PC qua cng COM, trong PC l mi trng lp trnh phn mm cho HTN. Xem http://www.lancos.com/siprogsch.html#baseboard
147
Hinh 2.72 PC lm h pht trin phn mm cho HTN, ph hp tn hiu gia RS-232 cua PC v cng SI-P ca HTN ang pht trin
Hnh 2.73 Cng SI-P n gin, dng ngun t RS 232 ca PC 2.6.5 Ghp ni vi tn hiu tng t (analog signal) Cc thit b m HTN phi kim sot, iu khin s dng cc tn hiu lin lc vi HTN thng qua cc ghp ni. Cc tn hiu c th dng ri rc (discrete), hay bin thin lin tc theo thi gian, gi l tn hiu tng t (analog). Cc tn hiu trong t nhin phn ln dng tng t, biu din s bin thin lin tc theo thi gian ca mt i lng vt l no . Trong khi dng my tnh x l cc tn hiu , cn mt cng on nht nh chuyn ha tn hiu tng t thnh tn hiu ri rc, gi l s ha (digitalization). Lm s ha i khi ging nh m ha tn hiu analog vy, bi v c nhiu cch s ha v u ra ca s ha li c th biu din bi cc tp 148

hp nh phn khc nhau. Vi mch in t thc hin chc nng s ha gi l b s ha (analog-todigital converter-ADC). Ngc li, sau khi x l, tnh ton tn hiu tng t s ha, HTN s a ra cc gi tr v chuyn ti cc thit b. Nu cc thit b ch nhn tn hiu tng t, cn mt qu trnh chuyn i gi tr s thnh gi tr tng t. Vi mch thc hin gi l b chuyn i s ra tng t (Digial Analog Converter ADC). 2.6.5.1 Mt s khi nim lin quan ti s ha Sai s lng t: Qu trnh s ha lun lm mt i tnh chnh xc ca thng tin cha ng trong tn hiu gc. Tuy nhin vi sai s nht nh th kt qu vn c chp nhn. Bng di y cho thy sai s ca mu c s ha biu din theo s bit th hin gi tr gc: V d ly mu audio: u vo tng t c gi trin t 0 n 1, Tn s ly mu fsample = 44,1 KHz. Resolution = f(s bit biu din). Dung lng b nh cn lu d liu sau thi gian s ha 1s, 60 s v 300 s
Tc ly mu, trung thc s ha: ph thuc vo TCONVENSION ca l thi gian bin i xong mt mu ca ADC, t kt hp vi nh lut NyquistShannon tnh tn s ly mu:
Biu din Fourier transform ca x(t) nh trn, v nu X(f) = 0 cho mi | f | > B, th x(t) b gii hn b bng thng B. T tn s ly mu ti to tn hiu gc l :
fsample > 2B
149

n gin ha th tn s ly mu s ha vi ADC:
fsample = 1/ TCONVENSION , f sample min > 2 fanalog l t nht.

Mu phi ly v bin i lin tc m bo tnh trung thc ca tn hiu. f cng ln v s bit s dng cng cao tnh trung thc cng tt, tuy nhin b nh d liu li l vn . C mt s cch m ha u ra c th b tr gi 2 yu cu: chnh xc v trung thc. V d cc thit b trang m hi-fi c thang tn s t 20 n 20KHz, th tn s ly mu ti thiu l 40 kHz. M ha (codecs): - Nh phn, - Pulse code modulation (PCM), - Pulse width modulation (PWM). - Differential pulse coded modulation (DPCM), - Adaptive differential pulse code modulation (ADPCM) L cc biu din s u ra ca cc ADC. 2.6.5.2 Bin i tng t thnh s (s ha) M hnh u vo ca ADC v ghp ni vi h thng B chn knh u vo: khi s dng mt ADC c tnh nng cao, thi gian bin i mt mu nhanh, c th dng AD cho nhiu tn hiu u vo. Mch trch mu: dng ly mt gi tr tng t, nh tr s trong thi gian ADC chuyn thnh gi tr s. Thi gian cn thit xong mt bin i l TCONVENSION . ADC Cng ghp ni vi h thng tnh ton (HTN)
SW
Ly mu
ADC
Cm bin Cc knh vo
HTN
Hnh 2.74 ADC v ghp vo HTN 2.6.5.3 Bin i s thnh tng t (DAC) Trong trng hp thit b nhn gi tr tng t t HTN, cn c b bin i s-tng t: 150
HTN
DAC
Lc thp tn
I->U
Hnh 2.75 HTN v DAC ADC v DAC l mt ch rt phc tp, c th tham kho t cc bi hc khc. Khi s dng tham kho ti liu chn loi ph hp vi ng dng s thit k. Tuy nhin mt s thng s sau y c nu ra khi chn ADC/DAC: phn gii ca ADC: 8 bit, 10 bit, 12 bit; Thi gian chi ph cho mt bin i (hay tc bin i); nhy u vo tng t (hay thang o), gii (bin ), cc tnh tn hiu u vo; Ngun nui (n cc hay hai cc:+/-), bin V; Cn hay khng cn mch ly mu u vo (Sample-hold circuit); Ghp ni vi vi tnh (CPU), c tn hiu i thoi, ngt; . 2.7 KT CHNG
Chng ny cp n nhng k thut lin qua n phn cng, t hot ng ca CPU, ca BUS ( BUS ca CPU v BUS h thng). Vic nm bt v hiu cc nguyn tc lm vic ca CPU gip cho cc phn tip theo, l nhng k nng h tr cho vic thit k cc h thng vi tnh hay HTN, bi v nguyn tc khng c g khc bit. to ra mt h thng vi tnh, cn phi thit k b nh v m rng ghp ni vi cc thit b ngoi. Ghp thit b ngoi vo HTN l khu khng th thiu, bi HTN lin quan chnh ti cc thit b, l i tng HTN qun l v iu khin hot ng ca chng. Cc phng php ghp ni l chun k thut, do hiu c nguyn l v p dng cho tng ng dng s lm cho HTN hot ng hiu qu. 2.8 CU HI V BI TP
2.8.1 Cu hi cui chng 1. BUS hp thnh t cc tn hiu no ca CPU, chc nng, chiu trao i d liu mi BUS c khc nhau ? 151

2. Th no l mt vi mch c 3 trng thi v 3 trng thi l nhng trng thi no ? Khi no phi s dng vi mch 3 trang thi ? 3. Th no l cng (port), cng dng l g ? 4. L th no truy nhp vo cng ? 5. Th no l memory mapped I/O ? 6. Th no l I/O mapped I/O ? 7. CPU thng thng c mt tp cc tn hiu pht ra u ra theo kiu dn knh, v d cc ng AD7-AD0 ca CPU 8080/8085. Lm th no tch cc ng dy A7-A0 v cc ng dy D7-D0 ? Th thit k bi tp ny ? 8. BUS ca CPU v BUS h thng c khc nhau ? Ti sao ? 9. BUS m rng v BUS h thng c khc nhau ? To sao ? 10. Khi thit k HNT, c cn ti BUS m rng v cc ch hot ng ca BUS m rng ? To sao ? 11. M t mc ch ca bng vector ngt. 12. Th no l ghp ni vo/ra khng iu kin v c iu kin ? 13. Khi no thi chn gii php ghp ni khng iu kin ? 14. Khi no thi chn gii php ghp ni c iu kin ? 15. C nhng phng php ghp ni no ? M t nguyn tc hot ng ca tng phng php. 16. Ti sao truyn c liu bng DMA li nhanh hn kiu iu khin bng chng trnh ? 17. u v nhc im ca ca hai phng php vo/ra iu khin bng chng trnh v DMA ? 18. Ngt l g ? Khi no th dng ngt ? 19. C nhng kiu ngt no, phm tr s dng ca cc kiu ngt ? 20. Cho v d v cc thit b m khi ghp ni s dng ngt l hp l hn cc kiu ghp ni khc. 2.8.2 Bi tp cui chng 1. Thit k bo mch vi CPU 8085 vi 4KB EPROM cha nhn HTN, 8KB RAM cho d liu, mi vi mch RAM c dung lng 8KB x 4 bit. a ch u cho EPROM=0000Hex, a ch u cho RAM=8000Hex. a ch u vo cho vi mch gii m l cc a ch l ? (Bi gii PH LC). 2. Di y l s thit k ghp ni mt module vi ADC vo PC qua cng my in. Tm hiu xem cch ghp ni nh vy c chy khng ? Th vit chng trnh iu khin c d liu tuwd ADC vo my tnh. 152

Cc vi mch s dng: Ngun chun LM 358 To dao ng 74LS14, R=1K, C=0,001 F cho f=700KHz (theo tnh ton ca ADC 0809) Dn knh 74LS157
Hnh 2.76 Bi tp thit k ghp ni ADC, cng LPT vo my tnh PC 3 ) Ghp ni vi cng kh trnh 8255. S dng ISA BUS trn PC. Mc ch bi tp: s dng vi mch a nng 8255, ghp ni vi BUS h thng m rng ISA: -S dng a ch IO cho Prototype 300Hex- thc hin ghp ni vi mch 8255 vi PC qua BUS ISA. Cng 301 c trng thi ca 8255, Cng 303 gi lnh cho 8255, mode 0. -S dng cng ca 8255 ni ti hin th l LED 7 thanh - Vit chng trnh thc hin ghp ni, a ra cc s lm cho n sng. 153

CHNG 3 CC THNH PHN PHN MM CA H THNG NHNG
Chng 2 cp ti phn cng ca cc h thng my tnh ni chung m HTN cng l mt trong cc h thng . S khc bit phn cng ca HTN l ph hp vi nhng yu cu t ra trn mt HTN cng c cp. Chng 3 s xem xt n phn mm c trin khai trn HTN. Nh trong m hnh kin trc tru tng ni chng 1, hnh di y s cho thy hai lp (con) mi s a thm vo m hnh . Khi cp ti phn mm, tng qut, ta c th chia ra lm hai lp: phn mm h thng v phn mm ng dng. Phn mm ng dng l cc phn mm ng dng nhng, cc phn mm ny nh ngha chc nng cng nh mc ch hnh thnh mt HTN c th. Phn mm h thng l phn mm c chc nng qun l hot ng ca phn cng, cung cp ngun ti nguyn phn cng v phn mm trung gian khc cho phn mm ng dng, thc thi m phn mm ng dng sao cho hiu qu v n nh. Ty thuc vo yu cu vn hnh ca mt HTN, phn mm h thng c th n gin nhng cng c th rt tinh xo. V d rt ph bin l phn mm h tr a nhim, v nu chu s rng buc v thi gian x l, th phi c tnh thi gian thc, v phn mm h thng s l mt h iu hnh thi gian thc (RTOS). Cn c nhng phn mm khc to ra lin kt gia cc lp phn mm, v d phn mm h thng khai thc phn cng, cn c mt phn mm sn gi l BIOS (Basic Input Output System), m thc t l tp hp cc module phn mm iu khin cc phn cng. Cc module ny cn c tn l cc module chng trnh iu khin thit b (device driver). C th miu t vai tr ny nh sau: phn mm ng dng c nhu cu trao i d liu vi thit b bng cch thc hin gi chc nng vo/ra ca phn mm h thng. Phn mm h thng chun b cc thng s vo/ra v gi cho cc device driver. Cc device driver nhn cc thng s u vo, v u ra s l cc lnh iu khin thit b c th. D liu ca qu trnh ny l kt qu m thit b thi hnh v trao i cho phn mm h thng qua cc phng thc ghp ni trnh by chng 2, cc vng nh b m d liu ca phn mm h thng. Sau phn mm h thng s chuyn d liu cho phn mm ng dng. Gia phn mm h thng v phn mm ng dng cn c mt c ch lin lc gi l gi h thng (systen call), m thc cht l phng thc m phn mm h thng h tr phn mm ng dng khai thc cc chc nng ca phn mm h thng. cng l ch m chng 3 s cp. 3.1 TRNH IU KHIN THIT B ( vit tt: TKTB) 3.1.1 Tng quan C th nu nh ngha v trnh iu khin thit b (TKTB) nh sau: l mt phn mm khi ng phn cng v phn mm lp cao hn s dng qun tr truy nhp vo phn cng ghp ni vo my tnh. Phn mm ny tng tc trc tip v iu khin phn cng v c t chc dng cc th vin phn mm. Khi my tnh c h iu hnh th TKTB l cu ni gia 154

phn cng v h iu hnh. Thng thng c nhiu thit b chun ghp ni vo my tnh, v d: a cng, a mm, CD, DVD bn phm, mn hnh, v mng V l cc thit b chun, nn khi thit k h iu hnh (HH) thng mi (WINDOWS, UNIX, Linux. Mac OS, ), cc TKTB c nhng trong h iu hnh nh cc th vin. Tuy nhin khi a thm mt thit b mi vo my tnh, m HH khng h tr, th phi vit m cho TKTB, lc ta ni l vit trnh iu khin thit b, cng vic s lm l chuyn i cc lnh vo ra tng qut ca HH thnh cc ch th dng thng ip sao cho cc thit b c th hiu c v thc hin cc ch th . HH thng khng qun l trc tip cc thit b, m thng qua mt trnh iu khin thit b o ha (virtual device drivers), v HH hnh nhn cc thit b nh l mt lp phn cng tru tng (hardware abstract layer HAL), cn cc thit b th c o ha (virtual device driver) nh vy HH s c lp (tng i) vi cc phn cng. Cc TKTB o s x l cc ngt mm t HH thay v x l cc ngt cng t cc thit b cng, v TKTB o s duy tr trng thi ca phn cng v cc thit c ca thit b li c th thay i c (programmable settings). Chng ta cp ti ngt cng v ngt mm v t chc ca vector ngt ca CPU. HH tn dng c ch ny ca CPU quan l thit b qua TKTB o. C th chng nghim iu ny khi ci HH WINDOWS ca Microsoft vo thi im np HAL pht hin cc thit b ghp ni vo my tnh. M hnh chung kin trc cc phn mm my tnh nh hnh 3.1
Hnh 3.1 M hnh tng qut cc phn mm trn my tnh Trong phn mm h thng t gia phn mm ng dng v phn cng. Hy xut pht t mt ng dng: khi ng dng mun s dng phn cng ca my tnh (truy nhp ROM, RAM, thit b ngoi nh a cng, mng ), ng dng s chuyn yu cu theo mt phng thc qui c gi h thng (system calls-GHT). GHT l mt giao din lp trnh m ng dng s dng khai thc cc dch v ca phn mm h thng. n lt mnh, phn mm h thng s gi lnh ti 155

cho mt nhm cc phn mm iu khin cc thit b, l BIOS. BIOS sau ra lnh thit b thc hin cc vo/ra d liu. Khi trin khai m hnh trn, ty thuc vo kin trc tng th cc phn mm trn c trin khai theo mt s cu hnh nh sau:
a.
b.
c. Hnh 3.2 M hnh tng qut cc kiu sp xp phn mm trn my tnh Hnh 3.2 a. l cu hnh dng n gin nht. Cc thit b nhng vi nhng chc nng iu khin kiu ON/OFF c th s dng. Hnh 3.2 b. l cu hnh nng cao vi phn mm trung gian thc hin cc x l phc tp hn, theo cc u tin, a x l hn ch. Trong khi hnh 3.2 c. L cc h thng tinh xo hn, vic qun l ng dng v qun l phn cng cn c h iu hnh, c phn mm trung gian. H c th m rng bng cc bo mch c TKTB nhng trn bo v kt hp vi h iu hnh qua c ch HAL. Cc TKTB trong HTN thng xp vo hai lp: Lp xc nh theo kin trc (architecture-specific) ca HTN, cc TKTB lp ny qun tr phn cng hp nht vi CPU. Cc kin trc kiu microcontroller, hay kin trc Havard 156

vi b nh trn chip, cng, vi mch qun tr b nh (memory management Unit-MMU), cc phn cng du phy ng, cc ADC/DAC hp nht trn bo mch, thuc lp ny. Lp TKTB tng qut (generic) iu khin cc thit b nm trn bo mch chnh nhng khng hp nht vo chip vi CPU. Tuy nhin m thc thi s c mt phn ca lp architecture-specific v khi truy nhp bt k thit b no u phi chy qua CPU. Tuy nhin TKTB lp ny cn dng iu khin cc thit b khng nht thit xc nh cho CPU c th. Ni cch khc TKTB c th lm cu hnh hot ng vi cc loi kin trc khc nhau m li c cc phn cng m TKTB vit iu khin cc phn cng . V d cc TKTB khi ng v truy nhp vo cc thnh phn ca bo mch nh: BUS Inter-Integrated Circiut (I2C), PCI, PCMCIA, cache L2, Flash B qua kiu TKTB, b qua kiu thit b, ta a ra y cc chc nng c bn ca TKTB: 1) Khi ng phn cng (Hardware Startup): Khi ng cc phn cng sau khi bt ngun hay sau khi RESET my. Phn ln cc phn cng l cc vi mch ghp ni hay iu khin cc thit b v l kh trnh. Cho nn bc ny l lp trnh cho cc vi mch chc nng ca bo mch, a cc vi mch vo trng thi u tin: trng thi sn sng thc hin cc lnh tip theo. 2) Tt my (Hardware Shutdown): Ngc li vi khi ng, iu khin tt my s cm tun t cc vi mch, kt thc kt ni vi cc thit b sao cho d liu khng b xo trn hay b hng. Cui cng l ct ngun in nui my. 3) Cm phn cng hot ng (Hardware Disable): Cho php phn mm khc c th tm thi v hiu ha mt phn cng khc. 4) Cho php hot ng (Hardware Enable): Cho php phn mm khc kch hot phn cng . 5) Dnh ly phn cng (Hardware Acquire): Cho php phn mm khc chim ly phn cng bng cch kho phn cng i vi cc phn mm khc. V d sau khi HH gii quyt tranh chp phn cng, gn phn cng cho mt tin trnh tm thi c quyn s dng, cc tin trnh khc phi ch. 6) Gii phng phn cng (Hardware Release):Cho php phn mm khc gii kha phn cng. 7) c/ghi d liu (Hardware Read/write ): Cho php phn mm khc thc hin trao i d liu vi phn cng. 8) Ci v tho d phn cng (Hardware Install/Uninstall): Cho php phn mm khc ci mi hay tho d phn cng. TKTB cn c th cc chc nng khc hay c th khng nht thit phi c tt c cc chc nng ny. Cc phn cng khi kch hot u c t nht ba trng thi m TKTB phi gim st: Khng hot ng (inactive, idle), ang hot ng (in active-busy), kt thc hot ng (finish). 157

Vy mt TKTB chy trong mt h thng nh th no ? Mi TKTB u nhm vo mt thit b c th, nhng c hp nht vi phn mm h thng. Phn mm ng dng tip cn TKTB qua giao din lp trnh GHT nh nu. Cch khai thc TKTB c khc nhau theo cch m mt h thng c xy dng v c hay khng c h iu hnh, h hnh l n nhim hay a nhim. V d vi MS DOS cc phn mm ng dng truy nhp TKTB d dng v trc tip. Tuy nhin vi h iu hnh a nhim th khc. cc h iu hnh ny c hai ch thc thi: supervisor hay user. Cc ch ny khc nhau ch cc thnh phn phn cng no ca h thng, mt phn mm c th truy nhp vo c. Ch supervisor cho php phn mm truy nhp khng hn ch phn cng, tc ti nguyn h thng, trong khi ch user th khng. Cc TKTB thng chy trong ch supervisor. L do: a nhim l tranh chp ti nguyn, gii quyt tranh chp cn gii php phn mm h thng. 3.1.2 Cc loi TKTB Cc thit b ghp ni vo my tnh ni chung hay HTN ni ring c th rt a dng, tuy nhin c th xp la nh sau: Thit b cung cp khi d liu (block device drivers), do khi thc hin vo/ra vi loi ny TKTB cn c b nh m (buffer) cho mi ln thc hin. Kch thc ca khi c th ln hay nh ph thuc vo kh nng ca thit b. Nh chng 2 cp ghp ni vi thit b loi ny s dng phng thc DMA. TKTB s bao gm lp trnh xin cp buffer trong RAM, gi cc thng s iu khin ti DMAC, cho php DMAC nhn yu cu DMA. Vi HNT, cc thit b loi ny, v d my MP3, Camcorder, TV, d liu t cc cm bin radar v.v. Thit b x l k t (character device drivers): khng cn s dng buffer ln, thng thao tc 1 k t 1 ln. Mt k t thng c di 8 bit. Khi trao i d liu c th khng gii hn s byte cho mi ln trao i vo ra. Chng 2 cp ti cc cch ghp ni v nhng nt chnh vit TKTB: c/khng c iu kin, c kim tra trng thi hay khng kim tra trng thi thit b, cch thot ra khi chng trnh trnh b qun khi thit b khng lm vic do s c Thit b loi ny c s dng ph bin trong HTN, v d cc cm bin qua ADC/DAC gi d liu vo RAM qua cc cng. i khi cng s dng cng truyn ni tip nhn hay gi d liu ti cc thit b xa bo mch, cng lp trnh v debug li SPI. Thit b mng (Network device drivers): Thit b mng nhn t ng truyn tng bit, chuyn thnh byte buffer v mng sau chuyn vo RAM bng ngt v DMA. TKTB mng nm lp 2 ca m hnh mng OSI. 3.1.3 Hot ng ca TKTB Khi TKTB c kch hot, mt lot cc thao tc s c thc hin. Nhn gc khi TKTB thuc qun l ca h iu hnh, cc thao tc nh sau: 158

T cu hnh (Autoconfiguration): Vo thi im nhn HH gi THTB xc nh thit b kt ni vi cng (probe interface), lp cc thng s ph hp v khi ng thit b. Thao tc vo/ra (I/O operations): TKTB s kim sot qu trnh vao/ra d liu gia RAM v thit b, Cc thao tc bao gm: m cng vi thit b, thc hin ghi/c d liu v ng thit b. X l ngt (Interrupt handling): Khi c ngt c chp nhn, CPU xc nh s hiu ca vector ngt, gi ISR tng ng. Cc bc chi tit trnh by chng 2. Nhng yu cu c bit (Special requests): C nhng trng hp cn ti cc x l t bit, th cc TKTB cng l dng c bit, v d cc ngt khng trong t chc vector m l cc ngt khng th che vi nhng mc u tin cao, x l cc s kin c bit xy ra trong h thng. Ti khi ng (Reinitialization): C nhng thnh phn theo chu k phi ti khi ng a thit b v trng thi ban au. V d watchdog timer, hay nu thit b c vn sau thi gian th truy nhp (time-out), cn ti khi ng thit b a thit b v trng thi ban u. Thc hin thao tc ny c th t ng bi phn mm h thng, cng c th cho php thc hin bng tay.
3.1.4 Pht trin TKTB Cc cng vic cn lm thit k TKTB: Thu thp thng tin: Cc thng tin v my tnh (host) s ci TKTB ln : loi CPU, loi HH, kin trc BUS; Cc qui nh c dng vit TKTB: Cch t tn cho thit b, m t thiiest b, ti liu. Xc nh cc thuc tnh ca thit b: thit b l kiu khi (block device) hay kiu k t (character device), thit b c h tr cu trc h thng tp (a cng, USB, ), h tr chui (byte stream), c kh nng phn ng vi ngt (cm ngt qui khi ang trao i khi lng ln d liu, khi ko di chu k ngt khng cm ngt tip theo, thao tc hng i d liu c th b ngt hay ngt) , khi ng li (reset) nh th no. M t v thit b: kiu thit b, c bao nhiu thit b cng kiu c th ci t trn h thng, mc ch ca thit b. Thit k TKTB Kiu thit b: k t (Character ), Khi (Block ), C hai: khi v k t, Mng (Network ). 159

u vo tip cn thit b: l giao din ghp ni thit b: a ch cng s dng, cch nhn bit thit b c trn h thng (thm d-probe, qut-scan) ghi nhn. Hiu cu trc d liu h thng v kiu a ch gn cho thit b Kiu d liu thao tc: Ph thuc vo kiu thit b, cch ghp vo BUS h thng, d liu song song, song song my bit, ni tip, biu din kiu nh phn, hexa , a ch o khng nh x: l a ch o trong khng gian HH a nhim. Khi dng vi HH a nhim s c loi a ch ny, nhn HH dung c ch ny dng k nh x a ch vi ch o. a ch vt l ca nhn HH: l ch thc trong khng gian a ch ca nhn HH, dng khi HH l a nhimKernel physical address . a ch vt l ca BUS: C mt s Bus ni vi thit b c th a ch ha ( Xem chng 2 v BUS), BUS ny thit b s dng chuyn d liu ti thit b khc. v d SCSI BUS v ID ca thit b ni vo BUS, max=8 hay 16 thit b, hay IDE BUS c IDE#1 cho 2 thit b, ID#2 cho 2 thit b. a ch RAM ni s thc hin trao i vo/ra d liu. a ch thit b hay a ch I/O: L a ch cng ghp ni ti thit b. Xc nh phng php ng k ngt ca thit b vi module qun l ngt (interrupt handler): thc hin qua mt gi h thng ti trnh qun l ngt hay nhy trc tip vo bng vector ngt. Trnh qun l ngt c hai u vo vi cu trc: ihandler_t v handler_intr_info. Cch sp t cu trc d liu ca TKTB: Khi khi ng h thng cc cu tr d liu v thit b s c ci vo v tr no, con tr tr ti ISR u (qua interrupt handler hay bng vector ngt). To mi trng pht trin TKTB: Khi i vo pht trin thng s dng cc b kit cho mi trng HH trin khai trn HTN. Cng c s yu cu ci t vi t chc th mc bin dch, to m thc thi v sau l hp nht vo HH, v np xung HTN ang pht trin. V d ca hng KIEL Software c cng c chip Chip 8051/80251. Tt c cc hng sn xut Chip CPU cho HTN u c DDK (Device Driver Development Kit) i cng.
3.1.5 Mt s v d v TKTB TKTB iu khin ngt: Ngt l c ch ph bin c s dng. Chng 2 c m t v cch thc ngt xut hin v cc bc x l ngt. Di y s nu ra mt s nt chnh khi thit k TDDKTB cho ngt. u chng ta lit k tm chc nng ca TKTB, trong c t nht 4 chc nng kt hp vi m t khi xy dng TKTB ngt:
160

1) Khi ng (start) phn cng qun l ngt : gi cc lnh iu khin ti iu khin ngt (v d vi mch 8259), ci t bng vector ngt, kch hot (cho php nhn ngt) sau khi bt my (POST). 2) Tt (shutdown) iu khin ngt: chuyn iu khin ngt v trng thi khng lm vic (idle). 3) Cho php phn mm khc tm thi v hiu cc ngt: a iu khin ngt vo ch v hiu (disable). 4) Cho php phn mm khc khi phc li hot ng ca iu khin ngt (enable). 5) Kch hot ISR: CPU xc nh s vector ngt, tm ti a ch ca ISR ca ngt v kch hot x l ngt . Khi vit m thc thi ca ISR rt thn trng, da vo phn tch cch qun l cc s kin m h thng hoi vng: s xut hin, mc u tin, cho/cm ngt qui. M ny thuc lo ti hn, phi rt ti u, chy hiu qu. Tt c cc chc nng trn khi chuyn thnh m u d vo qui tc sau: 1) Kiu, s hiu, mc u tin ca ngt: xc nh trn CPU, vi mch qun l ngt trn bo mch. 2) Ngt cng: Tn hiu ngt xut hin nh th no: bng sn ca tn hiu ( nhy cao) hay bng mc ca tn hiu ( nhy thp hn). 3) Chin lc t chc ngt: danh sch cc s kin m h thng s x l v c phn loi h thng c p ng ph hp. TKTB iu khin BUS Mi BUS h thng trn cc h phc tp u c mt qui c hot ng, goi l giao thc (BUS protocol), nh cp trong chng2. Protocol cho bit: thit b s c kh nng truy nhp vo BUS nh th no (qua trng ti BUS), cc qui nh thc hin bt tay khi cc thit b trao i d liu, cc tn hiu iu khin s dng trn mi BUS s c s dng th no cho qui trnh bt tay v trao i d liu. Cc chc nng sau y phi c ci vo TKTB khi thit b s dng BUS: 1) Khi ng BUS khi bt ngun. 2) Tt BUS khi tt ngun. 3) Treo BUS (disable): cho php phn mm khc treo BUS. 4) Kch hot BUS tr li (enable): cho php phn mm khc dnh li BUS v a BUS vo hot ng. 5) Kha BUS: cho php phn mm khc tm thi c quyn BUS bng ch kha (lock) BUS. 6) Gii kha BUS: cho php phn mm khc gii kha (unlock) BUS. 7) c/ghi: cho php phn mm khc c d liu trm BUS, hay a d liu ra BUS. 8) Ci t hay tho ci t BUS: cho php phn mm khc ci/tho mt thit b mi nhm m rng BUS. 161
TKTB li bo mch cm vo khe I/O h thng Khi m rng chc nng h thng thng cn ti bo mch thit k cho chc nng mi. Thng thng cm bo mch vo BUS h thng s hnh thnh mt c ch kiu ch (master) v th cp (slave). Giao tip bo cm thm s c kim sot bi vi mch ghp ni-iu khin trn bo (slave). Trong vi mch s c cc thanh ghi iu khin, thanh ghi trng thi sao cho master c th truy nhp v kim tra hot ng ca bo mch cm thm. TKTB cho bo mch s c cc chc nng sau : 1) Khi ng I/O: Khi ng bo cm thm sau khi bt ngun t h thng. 2) Tt I/O: tt hot ng I/O tren bo mch cm thm khi tt ngun. 3) V hiu I/O bo mch cm thm: cho php phn mm khc v hiu I/O. 4) Kch hot bo mch : cho php phn mm khc kch hot I/O tr li. 5) Kha/gii kha: cho php mt phn mm khc kha bo mch, hay cho php phn mm khc kch hot bo mch tr li. 6) c/ghi bo: cho php phn mm khc thc hin c/ghi d liu vi bo mch.
Trong chng 2 c v d v TKTB vi lu iu khin ghp ni c iu kin, cng l mt li vit TKTB. C th tham kho vi MS OS ti : How to Write a Windows Driver. http://msdn.microsoft.com/en-us/library/ms809956.aspx 1.Ci DDK 2. http://www.adp-gmbh.ch/win/misc/writing_devicedriver.html 3.2 H THNG NHNG THI GIAN THC Trc khi i vo m t v HTN thi gian thc, cn tr li mt s khi nim lin quan ti h iu hnh cho my tnh. Mt h thng tnh ton hay mt thit b k thut s lun cn c phn mm h thng. Phn mm h thng m nhim chc nng qun l ti nguyn nh phn cng my tnh (ROM, RAM, thit b lu tr thng tin, cc thit b ngoi vi ), tp thc hin giao tip ngi my, khi ng, cung cp ti nguyn v iu phi cc chng trnh ng dng, v.v. Mc phc tp ca phn mm h thng c th khc nhau t n gin n tinh xo. Cc HTN cng khng phi l ngoi l, c HTN n gin c HTN phc tp, i vi cc HTN phc tp khi phi thc hin nhiu ng dng ng thi, th cn c h iiu hnh a nhim h tr. 3.2.1 H iu hnh a nhim (multitasking) Phn ln HTN c s dng trong mi trng iu khin cng ngh, ti ty vo v tr trong ton b dy chuyn, HTN c th l cc loi vi qui m kin trc khc nhau. Tuy nhin phn 162

mm h thng i hi tng i kht khe v loi HH s dng ph bin l h iu hnh thi gian thc (Real Time Operating System RTOS), a tc v. Khi tho lun v RTOS l mt ti ln v phc tp, cho nn chng ch s trch nhng im cn thit cn quan tm khi pht trin RTOS trn HTN. Khi cp ti HH kiu a tc v, cn nhc li mt s khi nim sau y: , Nhn HH, Tin trnh, ch hot ng, chc nng, ngt, tc v, ngt, ngoi l Nhn HH (kernel): Nhn HH thc hin chc nng chnh ca HH, gm: Qun l cc tin trnh: to ra cc tin trnh, cung cp ngun ti nguyn cn thit tin trnh hot ng, gim st thc thi tin trnh trong mi trng a nhim. Qun l ti nguyn: Cc ti nguyn my tnh bao gm: CPU, RAM, thit b I/O, h thng tp (File system) . Cung cp cc ti nguyn khi to tin trnh v khi tin trnh i hi, gii quyt cc tranh chp ti nguyn, thu hi ti nguyn khi tin trnh kt thc thc thi. Cung cp th vin cc hm chc nng ca nhn cho ng dng qua API gi h thng (GHT). t bo v, nhn chy trong mt ch ring (supervisor/protected). Ch ny c h tr th kin trc ca CPU. Nhn t HH th gi l ch nhn (kernel mode). Tin trnh (Process): Trn mt h a nhim, khng ch mt chng trnh chy trn my v phng thc ph bin nhiu chng trnh c th chy ng thi l k thut phn chia thi gian s dng CPU cho mi chng trnh (time sharing). Nh vy mi chng trnh khng chy lin tc m c nhng thi im chng trnh dng. Chng trnh dng v khung thi gian s dng CPU cho n ht, hay khi ti nguyn n yu cu cha c p ng, hay b mt x l khc c xu hng chen ngang s dng CPU, lch din s vn ng nh vy, cn c mt khi nim, gi l tin trnh. V ng ngha l ni n qu trnh tin trin (thc hin) chng trnh theo thi gian trong khi chng trnh ri vo nhng hon cnh khc nhau, trong mi hon cnh nh vy gi l trng thi ca tin trnh. Vy tin trnh (TT) l thi im thc hin ca mt chng trnh (instance of execution) v vic thc hin ch xy ra trong mt khon thi gian nht nh (slice time). Nhn kha cnh qun l ca HH, th tin trnh do HH to ra thu gi tt c cc thng tin lin qua ti vic thc hin chng trnh. Nh vy thc hin c chng trnh, TT s s dng CPU chy cc lnh ca n, v b nh ni c m lnh (code hay text), d liu (data), v ngn xp (stack) ca chng trnh. Mt TT khi thc hin phi lm theo mt trnh t cc lnh trong vng code ca TT. TT ch c th c/ghi truy nhp data v stack ca n, nhng khng th trn data v stack ca TT khc. TT lin lc vi cc TT khc v phn cn li ca h thng bng cc Go H Thng (GHT, system call) v c ch lin lc gia cc tin trnh (IPC). M hnh v qu trnh tin trin chy chng trnh gi l m hnh trng thi. 163

V c bn c th a ra ba trng thi chnh: 1. TT trnh chy (run): l khi cc lnh ca chng trnh c thc hin 2. TT dng (suspended, wait): do ht thi lng c phn phi, do ti nguyn cha p ng, do b chen ngang bi cc x l khc, ch s kin. 3. TT sn sng (ready): ti nguyn c, n lt chy li TT chuyn vo hng i ch kch hot bi h lp lch. Khi pht trin h iu hnh s trng thi c th nhiu hn v chi tit hn.
Chy trong ch ngi dng
Yu cu Ti nguyn
Ch ngi dng
X l ngt
fork():
to TT mi, chen ngang
Ch nhn
Chy trong nhn HH
Lp lch
Dng, treo, i
s kin
Sn sng trong hng i
Hnh 3.3 Trng thi ca tin trnh Tin trnh ch y trong ch ngi dng: ngi dng kch hot chng trnh ng dng. Tin trnh ch y trong nhn HH, tc nhn: khi chng trnh i hi ti nguyn, nhn HH thay mt ngi dng truy nhp ti nguyn (RAM, I/O) bng cc chc nng ca nhn, cc chc nng ny c kch hot t ng dng qua GHT hay ngt mm. Tin trnh dng, i, tc nhn: khung thi gian cho tin trnh ht, hay tin trnh b gin on v cc l do khc (dng x l ngt, i c ti nguyn). Tin trnh chuyn vo hng i (wake up) sn sng chy li, tc nhn: khi nhu cu ti nguyn tha mn, n lt chy li. H lp lch s thc hin qu trnh ny: Dng Hnh i Chy trong nhn Chy trong ch ngi dng kt thc. 164

fork(): to ra tin trnh mi. Cc trng thi s bin chuyn theo m hnh cho ti khi chng trnh kt thc. (Xem thm l thuyt HH a trnh, a nhim). Ch ngi dng v ch nhn HH Trong cc HH a nhim c mt ranh gii gia hai khng giangi l khng gian (a ch) ngi dng v khng gian (a ch) nhn HH dnh ring cho HH v c bo v bi CPU v m nhn HH. Ni nhn HH thay mt ngi dng truy nhp ti nguyn (RAM, I/O), c ngha l ti nguyn do nhn HH qun l, cung cp cho chng trnh ng dng (ngi dng) ti nguyn khi c nhu cu, c nh vy mi trnh c tranh chp ti nguyn h thng. hnh dung qu trnh chuyn trng thi t khng gian ngi dng v khng gian nhn nh sau: M HH chy trong khng gian a ch nhn HH, gi l ch nhn (kernel mode hay supervisor mode). Ch ny c h tr bi kin trc ca CPU ( bi cc lnh my c bit) v n ngn ngi dng truy nhp vo phn cng (qun l phn cng chun xc cho nhiu ngi dng ng thi, cn gi l ch c bo v (protected mode)). M cc trnh ng dng chy trong khng gian a ch ngi dng, gi l ch ngi dng (user mode). Vic kt ni gia hai ch chy trnh c thc hin bi gi h thng (system call). Thut ng nhn (kernel) cp n phn m ct yu nht ca cc chng trnh h thng, n kim sot ti nguyn my tnh nh cc tp, cc thit b in t, khi ng v cho chy cc chng trnh ng dng ng thi, cp b nh cng nh cc ti nguyn khc cho cc chng trnh ca ngi dng. Bn thn kernel khng lm g nhiu nhng cung cp cc cng c nguyn thu (primitive functions) m cc tin ch khc, cc dch v khc ca HH. Do cc chng trnh h thng, cc trnh ng dng s dng cc dch v ca HH, v chy trong user mode. Tuy nhin c s khc bit l cc trnh ng dng th tn dng nhng tin ch h thng cho, cn cc trnh h thng l s cn thit my tnh chy c. Gi h thng (hay gi cc dch v ca h thng, GHT), l mt giao din lp trnh gia HH v ng dng. N c thc hin bng cch t cc thng s vo nhng ch c nh ngha r rng (vo cc thanh ghi ca CPU hay t vo stack) v sau thc hin mt lnh by t bit (trap intruction) ca CPU. Lnh ny chuyn ch chy my t user mode vo kernel mode v t iu khin chuyn cho HH (1). Tip theo HH kim tra s hiu v cc thng s ca GHT xc nh GHT no s thc hin (2). T trong bng vi ch s (s hiu ca GHT), HH ly ra con tr tr n qui trnh (procedure) thc hin GHT (3). Khi thc hin xong GHT, iu khin chuyn tr li cho chng trnh ca ngi dng.
165
Hnh 3.4 Trin khai API qua GHT T y c th thy cu trc c bn ca GHT nh sau: 1. Mt chng trnh chnh kch hot dch v h thng bng mt GHT. 2. By (TRAP) chuyn GHT vo nhn HH, nhn xc nh s hiu ca dch v. 3. Thc hin dch v. 4. Kt thc dch v v tr v ni pht sinh GHT. Hnh sau cho cc bc theo trnh t t lp trnh n thc thi GHT read():
Hnh 3.4 Nguyn l a trnh v quan h gia ch ngi dng v ch nhn HH 166

Tc v (Task) : l mt ng dng chy trong thi gian thc v b gim st bng h thng lp lch ca HH. Trong cc h thng iu khin, khi nim tc v cng hay c s dng bn cnh qu trnh tnh ton. Tc v c th thc hin theo c ch tun hon (periodic task) hoc theo s kin (event task). Cc dng tc v qui nh trong chun IEC 61131-3 (Programmable Controllers Part3: Programming Languages) c minh ha trn hnh 3.5. V d, mt tc v thc hin nhim v iu khin cho mt hoc nhiu mch vng kn c chu k trch mu ging nhau. Hoc, mt tc v c th thc hin nhim v iu khin logic, iu khin trnh t theo cc s kin xy ra. Tc v c th thc hin di dng mt qu trnh tnh ton duy nht, hoc mt dy cc qu trnh tnh ton khc nhau.
Ch ti chu k
Ch s kin
M thc thi
Thi gian
S kin
M thc thi
M thc thi
Tc v mc nh V d: - iu khin logic - Kim tra li
Tc v tun hon V du: - iu chnh vng kn (loop control) -X l truyn thng
Tc v s kin V du: -iu khin trnh t -X l s c
Hnh 3.3 Cc kiu tc v So snh gia chc nng (function), dch v ngt v tc v: Chc nng (function) - Tp hp cc lnh thc hin mt hnh ng. - c kch hot bi th tc Proc/Task/ISR. - Mi chc nng c bi cnh thc thi ring. dch v ngt (ISR) - ISR l c lp. - Kiscg hot bi ngt cng hay mm. - ISR c gn mc u tin. - Mi ISR c bi cnh ring. tc v (Task) - Tc v l c lp. - c ng b thc thi bi RTOS. - Lp lch chn mt tc v chy trong mt khung thi gian.
Lung (Threads): L nhng phn chia nh ca mt tin trnh, chy trn cc h c a CPU, v c kim sot bi h thng kim sot tin trnh. 167

Ngt v ngoi l (exception): Bt k s kin no lm gin on thc thi ca CPU v y CPU vo thc thi nhng lnh c bit trng thi c quyn ca CPU. Cc ngoi l phn loi vo 2 hng: ngoi l ng b vad ngoi l khng ng b. Ngoi l ng b: pht sinh bi cc s kin bn trong, v d khi thc hin cc lnh ca CPU : C mt s CPU truy nhp b nh bt bu a ch chn, nu ngc l s bo li, hay khia thiwjc hin php chia m mu s bng 0, ,,, Ngoi l khng ng b: l cc s kin pht sinh t bn ngoi khng lin quan ti thc hin lnh ca CPU. Cc s kin ny gn li vi cc tn hiu ngt, t cc thit b. V du: n nt RESET trn HTN (system reset exeption), cc thit b truyn thng ca HTN to ra cc ngt khi nhn c d liu. Ngt ngoi cng c qui chiu vo loi ny. S khc bit ca hai loi ngoi l ch l ngun pht sinh ca s kin. iu phi chy chng trnh bng lp lch (schedule) Lp lch l mt php thc hin phn b v gn quy trnh thc thi cc tc v cho b x l sao cho mi tc v c thc hin hon ton. Nh vy cng vic ca lp lch l tm kim mt gin phn b thi gian thc thi theo kiu a nhim hp l vi cc iu kin rng buc cho trc. Hay ni cch khc l lp lch phi x l thng tin iu kin quyt nh v iu phi thc hin tin trnh/tc v. Qun l tc v thng qua lp biu:
Ngt ngoi
iu phi ngt
ISR
Ngt nh thi
Cc dch v thi gian v s kin Cc dch v (to tin trnh, lung, chuyn trng thi, nhn, pht d liu )
Lp biu v iu phi tc v
Thc thi tc v
Gi h thng, by
Nhn RTOS
Hu ht cc loi tc v xuyn qua lp biu. Hn cht (deadline): thi iim cui cng phi cho ra mt p ng trong cc h rng buc v thi gian. Trong hnh di y di l hn cht. Thi gian xut hin ai (arrival time): Khi s kin xy ra v tc v tng ng c kch hot. 168

Thi im bt u thc thi ri (release time): Thi im sm nht khi vic x l sn sng v c th bt u. Thi im bt u thc hin si (starting time): L thi im m ti tc v bt u vic thc hin ca mnh. Thi gian tnh ton/thc thi ci (Computation time): L khong thi gian cn thit b x l thc hin xong nhim v ca mnh m khng b ngt. Thi im hon thnh fi (finishing time): L thi im m ti tc v hon thnh vic thc hin ca mnh. Thi gian ri ro/ xu nht wi (worst case time): khong thi gian thc hin lu nht c th xy ra, dung sai mm = wi-di. Thi im kt thc di (due time-deadline): Thi im m tc v phi hon thnh.
ci
t ai ri si fi di wi
Hnh 3.4 Biu thc hin mt tc v Lp lch (scheduling) : k hoch ha vic thc hin cc tc v theo thi gian. a) Phn loi lp lch, cc TT c phn ra lm hai lp theo nhu cu thi gian, l : 1. hng I/O (I/O bound) c ngha TT s dng nhiu ti I/O v s dng nhiu thi gian i kt qu I/O; 2. hng CPU (CPU-bound), l lp TT yu cu nhiu thi gian CPU. cc HH a nng, cng c cch phn bit khc theo lp ng dng nh: - Lp TT tng tc (interactive), tng tc thng xuyn vi user, do chi ph nhiu thi gian cho nhn bn phm, hay chut. Khi c u vo TT phI thc dy tht nhanh, thi gian tr trung bnh l 50 n 150 ms, nu qu chn, user co h c vn ; Cc ng dng nh son vn bn, shell, ho (tI to hnh nh) thuc lp ny; - Lp TT x l l (batch), khng cn c s can thip ca user, v thng chy nn (background). Do khng cn phi c p ng nhanh, nn thng khng c xp u tin cao, V d loi ny l cc trnh dch (compiler) hay c cu tm d liu (database search engine), cc tnh ton khoa hc; - TT thi gian thc (real time), c yu cu rt khc khe, khng bao gi b cn tr bi cc TT mc u tin thp, cn p ng thi gian tht nhanh, v quan trng hn c l thi gian p 169

ng ch c thay i mc ti thiu. Cc ng dng nh video, m thanh, iu khin robot, thu nht s liu vt l thuc lp ny. b) Cc gii thut lp lch c nhiu v theo nhiu tiu chun. M hnh di y trnh by mmojt s gii thut lp lch h thi gian thc:
Lp lch thi gian thc
Hn cht cng
Hn cht mm
Chu k
Khng chu k
Chen ngang
Khng chen ngang
Chen ngang
Khng chen ngang
tnh
ng
tnh
ng
tnh
ng
tnh
ng
Hnh 3.5 Phn loi cc gii thut lp lch thc hin tc v Lp lch hn cht mm thng c thc hin thng qua m rng mt s chc nng ca h iu hnh. V d nh cung cp cc mc u tin cho vic kch hot cc tc v hay gi h thng. Hn ch mm t thn n khng cha ng nhiu yu t c tnh quyt nh, thi gian xc nh c th x dch vi dung sai (c th ng k) hay tnh nhy cm thi gian khng quan trojnh lm (less time-sensitive). Lp lch hn cht cng li rt nhy cm vi thi gian (more time-sensitive). ng hn phi thc hin/hay kt thc khng th ko di, sai hn nh s dn ti hu qu (nghim trng). Chen ngang (preemptive): gii thut c s dng nu c tc v no c thi gian thc thi qu lu, n c th b tc v khc ngt hay nu mt s kin bn ngoi cn thi gian p ng ngn, s kin s ngt s kin khc. Khng chen ngang (non-preemptive): gii thut gi nh rng cc tc v s thc hin cho ti khi hon tt. Nh vy nu c mt tc v thc thi qu lu, th p ng cho cc s kin ngoi s lu. 170

Quay vng kt hp mc u tin (Co-operative Round robin Scheduling): S dng qui tc quay vng theo mc u tin gim dn. Trong mi mc u tin c th c vi tc v ng mc. V quay vng t hiu qu trong RTOS, nn khi dng cn kt hp vi c ch chen ngang th mi t hiu qu: T1 quay vng v b T4 mi chen ngang:
Cao
u tin
Chen ngang
T4
T4 hon tt
Thp
Task 1
Task 2
Task 3
T1
T1
T2
Hnh 3.6 Quay vng kt hp u tin v chen ngang Vic tnh mc u tin ca mi tin trnh c thc hin theo mt trong s cc thut ton sau: - Rate monotonic: tc v no cng din ra thng xuyn cng c u tin. - Deadline monotonic: tc v no cng gp, c thi hn cui cng sm cng c u tin. - Least laxity: tc v no c t l thi gian tnh ton/thi hn cht (deadline) cng ln cng c u tin. Lp lch tun hon / khng tun hon (periodic and aperiodic): Tc v s thc hin c sau
mt n v thi gian, gi l tc v tun hon. Ngc l l tc v khng tun hon v c c im l s thc hin vo cc thi im khng d on trc c.
Lp lch tnh (offline): Vic lp lch c thc hin da trn cc hiu bit hoc d bo v cc s kin tc v thc hin trong h thng (thi im xut hin, thi gian thc hin, hn cht c tnh (deadline) v c quyt nh ti thi im thit k v c p dng c nh trong sut qu trnh hot ng ca h thng. Cc tc v c khi ng cc thi im lp trong mt bng trc , module phn phi (dispacher) khi ng tc v theo ch dn trong bng. Module phn phi c kim sot bi cc b nh thi (timer), a module vo thc hin phn tch bng lch kch hot tc v ng thi im. Mt h thng b gim st bi timer gi l time trigged (TT system). Vic lp lch trc c mt s cc u im sau: - Tc v tip theo c th c la chn thc thi trong khong thi gian l hng s - Kh nng p ng yu cu thi gian thc c th c bit trc v c m bo Nhc im: - Khng th thay i lch trnh thc hin ca h thng trong qu trnh thc hin 171

- i hi phi c thng tin thi gian chnh xc v cc tc v tnh ton lp lch. Mt thut ton lp lch tnh c gi l ti u nu n lun lun c th tm c mt lch iu phi tho mn cc rng buc cho trong khi mt thut ton tnh khc cng tm c mt li gii. Lp lch ng (online): B x l thc hin vic lp lch trong qu trnh thc thi (run time) da trn c s cc thng tin hot ng hin hnh ca h thng. S lp lch l khng xc nh trc v thay i ng theo qu trnh thc hin. Lp lch ng linh hot nhng tn thi gian tnh ton ra quyt nh v cng khng c nhn thc ti bi cnh tng th nh cc yu cu ti nguyn, s ph thuc gia cc tc v. cc HTN cc bi cnh tng th thi c nh hnh lc thit k. V d l lp lch kiu Earliest deadline first scheduling and Least slack time scheduling. Lp lch tp trung hoc phn tn (centralized / distributed): l cc gii thut lp lch chy trn mt hay vi CPU ca mt my.
Lp lch Mono hay Multi-processor: Gii thut lp lch trn cc CPU n l hay trn
nhiu CPU. Loi gii thut ny trin khai trn cc h thng lin kt, cc h thng c th l ng nht (cng loi CPU) hay khng ng nht (nhiu my, cc my c loi CPU khc nhau) ng dng thao tc nhng ch xc nh (target specific) c thi gian rng buc. S dng p dng trn cc h thng hn hp hardware/software, trn mt s tc v chuyn
cho phn cng thc hin.
Cc nhn HH c iu khin theo c ch ngt thng thc thi c ch lp lch khng chen ngang (dymnamic nonpreemtive) ng , trong khi loi ht nhn HH vn hnh theo qu trnh li thc thi theo c ch chen ngang ng (dynamic preemptive). Trn c s b lp lch s phi thc hin bi ton ti u v: Thi gian p ng (response time) Hiu sut thc hin (s lng cng vic thc hin xong trong mt n v thi gian S cng bng v thi gian ch i (cc tc v khng phi ch i qu lu)
V d bi ton lp lch:
Scheduling Function
A real-time system had to execute four tasks J1, J2, J3, J4 with arrival times and deadlines shown in the following table. The scheduling function _(t) observed is shown in Figure 6.
172
Figure 6: Scheduling Function Determine a) the maximum lateness, b) the tasks laxities, and c) the processor utilization for this schedule. Is the schedule feasible? If not, try to modify the scheduling function so that the schedule becomes feasible. Solution - Task 4 The lateness of a task is the delay of the task completion with respect to its deadline (note that if the task finishes before its deadline, its lateness is negative). The maximum lateness is of the task J2 = fi di = 12 10 = 2 (task J2 is the only task that violates the given constraints). The laxity (or slack time) is the maximum time that a task can be delayed on its activation to complete within its deadline. The laxities of the tasks J1, . . . , J4 are as follows (in the table below are the individual tasks computation times):
173

1. X1 = d1 a1 C1 = 9 0 4 = 5 2. X2 = 10 4 2 = 4 3. X3 = 17 2 4 = 11 4. X4 = 13 4 3 = 6
The CPU_Utilization is 13/14 = 0.93. A schedule is said to be feasible (kh thi) if all tasks can be completed according to a set of specified constraints. The scheduling function suggested in the exercise, _(t) is thus not feasible (the task J2 does not meet its deadline). Figure 7: Violation in the old scheduling function
The schedule can be modified in order to complete the execution of all tasks before their respective deadline. One (of several) feasible scheduling functions is depicted in the figure. Figure 8: New scheduling function
174

B gim st nh thi (watchdog timer): l ng h thi gian cng (dng cc b m in t ) vi cc ng dng sau y: - Lm ng h thi gian thc (real time clock-RTC) cho h thng; - Khi ng/ khi ng li mt s kin sau mt thi gian t trc; - To khung ca s thi gian cho mt s kin; - Phn gii khon thi gian gia 2 s kin; - Ch canh chng. hay h thi gian mm (lp cc gi tr m cho mt bin chng trnh), cc thao tc tng/gim gi tr m thc hin bng lnh my, do ph thuc vo CPU clock (mi loi CPU c clock khc nhau).
RESET
nh thi (watchdog-WD)
CPU
RESET-in CPU RST-out
RESTART WD CLOCK
M hnh nguyn l cho WD Ch canh chng s thc hin mt ti khi ng (reset) h thng hay mt hnh ng (x l), hay kch hot mt x l hiu chnh nu chng trnh chnh b li, khng tin trin c do mt iu kin no khng th t c trong khung thi gian d tnh (chng trnh b treo). Trong cc h thi gian thc, trong c HTN, ch canh chng rt quan trng, c s dng t ng khi ng li mt ng dng nhng hay thm ch c h thng v trng thi ban u m khng c s can thip ca con ngi. Trong cc CPU nhng ta thy c vi b m thi gian (specialized timers) cng, t cc gi tr khc nhau cho cc ng dng quan trng, m trong khung thi gian ng dng phi kt thc hay phi a ra c p ng, nu khng (kh nng c s bt thng) ng dng s c ch canh chng khi ng li t u. Cc h c ci trnh gi ri s ghi li vo b lu tr c bit h tr khc phc s c. C th timer mm cho cc ng dng t ti hn (critical) hn. V d watchdog timer l mt b m (counter) cng/mm vi x bit, vi u vo c tn s m f , thi gian t vo b m l T, sau T n v thi gian, b m t gi tr t (hay t gi tr t kuif v 0). Nu sau thi gian m b m khng c ti khi ng, h thng s b khi ng li. V d : gi nh mt phn mm, c c vng lp chy trong 25 micro giy, hay vi dung sai ti a l 35 micro giy thc hin x l. Dng mt mt watchdog timer c u ra ni vo mt ngt khng che (NMI), hay vo chn RESET ca CPU. watchdog timer c np mt 175

gi tr 50 micro giy, nu sau thi gian phn mm vng lp khng kt thc, u ra ca watchdog timer s kch hot RESET, khi ng li h thng. Nu vng lp kt thc vi trng hi bnh thng, watchdog timer s c np li gi tr cho mt chu k mi. HTN l loi h thng con ngi khng th gim st hot ng thng xuyn, do vy ch canh chng l gii php nu h thng b treo (l do .). C nhng trng hp nu phn mm c li nghim trng, ch canh chng c th s loi (disable) phn mm khng cho chy na. Gii thut vi watchdog timer: Mi tc v khc bit thc thi bi mt main loop, nu kt thc hon ho, t c trng thi ln (Flagi set = TRUE). Tt c cc main loop thc hin ti a trong 35 micro giy. Sau vng cui cng l on m kim tra : Nu tt c cc Flags u l TRUE, khi ng chu k watchdog mi (50 micro giy), nu Flags = FALSE, ghi nhn s c v t tt c Flags = FALSE, watchdog khng c khi ng li (kick the dog) trong thi gian 50 micro giy, u ra ca b m watchdog s kch hot RESET h thng.
Main loop code: main() { Call(Set Twd); Task1() { . . .
FLAG=(TRUE/FALSE);
} Task2() { . . .
FLAG=(TRUE/FALSE);
Ttask
} Taskn() {. .
FLAG=(TRUE/FALSE);
If (AllFLAGs=OK) { Call(reset Twd); Jmp mainLoop } else { Log error; reset System; WD reset CPU }
} }
Hnh 3.7 Gii thut vi gim st nh thi (ch canh chng) 176

on m if (all flag are OK) { Call(Reset Twd); Jmp mainloop; } else { Log eror; Reset System; } V d to mt watchdog timer: Bi ton: Phi reset timer c sau x n v thi gian, nu khng timer s pht sinh tn hiu overflow (dng khi ng li h thng cng-RESET hay qua ngt). S dng: Pht hin li h thng thi gian thc sau x n v thi gian; hay t RESET h thng c sau x n v thi gian. - V d vi my ATM rt tin t ng: timer 16 bit, thi gian rt tin ti a l 2 pht, - Vi 16 bit, m nh phn t 0 65.535 trong 2 pht ta c: Tclk =2*60*1000(ms)/65.535 = 0,54 ms fclk =1/0,54 ms= 1,85 KHz //Record failure //WD reset CPU //nu thc hin on code ny c ngha //counter s vt 50 giy n nh xung u ra s RESET CPU.
//H hot ng bnh thng, //t mi gi tr 50 micro giy co watchdog //Tr v chu k mi;
T b dao ng
clk
prescale scalereg
overflow Timereg
overflow
Ni vo chn RESET ca CPU, hay s dng nh mt ngt
checkreg
Gii thut: /*main.c*/ Main() { Wait until card inserted; Call watchdog_reset_routine; while(transaction in progress) { 177

If(button pressed) { Perform correspondding actions; Call watchdog_reset_routine; } } /* Nu sau 2 pht Call watchdog_reset_routine khng kch hot sau t < 2 pht,*/ /* th interrupt_service_routine s kch hot.*/ } watchdog_reset_routine() { /* Kim tra nu checkreg = 1, np gi tr vo timereg: Np 0 vo scalereg, v gi tr*/ /*65.535 vo timereg*/ checkreg =1; scalereg = 0; timereg = 65.535; } Void interrupt_service_routine() { eject card; reset screen; } C rt nhiu k xo s dng vi watchdog timer khi thc hin mt h thng c th. Truyn thng gia cc tin trnh (Inter Process communication IPC) ng b chy cc chng trnh h iu hnh thc hin mt s c ch ng b thc hin cc tin trnh, bao gm: 1) pipe (ng ng): khng tn, FIFO: c tn; 2) thng ip (message): cho php cc TT gi cc khun d liu c khun dng ti bt k TT no; 3) vng nh chia s (shared memory): cc TT chia s mt phn khng gian a ch o ca mnh; 4) nh tn hiu (semaphore): cc TT dng ng b vic thc hin.
178
Ghi ch: Phn ny lin quan ti H iu hnh, nn khi hc nn xem li L thuyt H iu hnh a nhim, c bit RTOS
3.2.2 H thng thi gian thc Khi nim h thi gian thc khng ng ngha vi khi nim h x l tc cao, x l nhanh. Nu ta cho rng, phi l cc ng dng iu khin c yu cu thi gian tnh ton rt nhanh mi gi l iu khin thi gian thc, th mt cu hi s c t ra l: nh th no mi c gi l nhanh? Ta c th thng nht l, c mt vi micro-giy l rt nhanh, tuy nhin nu mt vi chc micro-giy th sao, mt trm micro-giy th sao? Nu mt trm micro-giy mi gi l nhanh, th 101, 102, ... c nhanh khng? Cc h iu khin vi chu k trch mu 5ms, 6 ms, 7ms c c gi l h thi gian thc hay khng? Tc khng phn nh thi gian thc nhng c c tnh thi gian thc th ph thuc rt nhiu vo tc . Tc cng cao th sai s cng nh v cng d thc hin cc tc v thi gian thc. C th ni n gin hn, tnh thi gian thc l kh nng p kp thi v chnh xc. c im ca h thi gian thc Tnh b ng: H thng phi phn ng vi cc s kin xut hin vo cc thi im thng khng bit trc. V d, s vt ngng ca mt gi tr o, s thay i trng thi ca mt thit b qu trnh phi dn n cc phn ng trong b iu khin. Tnh chun xc chc nng v chnh xc v thi gian: Cc chc nng phi c thc hin chun xc. Cc tnh ton, x l phi cho ra kt qu trong mt chu k thi gian xc nh trc. Chnh xc v thi gian s cho php h a ra p ng mt cch kp thi. Tuy tnh chnh xc thi gian l mt c im tiu lch, nhng mt h thng c tnh nng thi gian thc khng nht thit phi c p ng tht nhanh m quan trng hn l phi c phn ng kp thi i vi cc yu cu, tc ng bn ngoi. Hy kho st cc v d sau y lm r yu t thi gian trong h thng thi gian thc: ts l thi im mt s kin xy ra t thit b v tc ng ti h thng; T l khon thi gian thc hin cc tnh ton, x l t ts ti tp c p ng u ra. tp l thi im ra p ng. Ta s c cc trng hp sau y: a) p ng ng theo yu cu ti tp: p ng chnh xc. b) p ng xy ra trong khon <tpq, tp2>. c) p ng xy ra trong khon <ts, tp>. d) p ng xy ra t tp cho ti
179
Hnh 3.8 S kin v p ng C th cn c cc phn tch khc cp ti thi im phi a ra p ng cho tc ng ca s kin, qua y ta thy r hn yu cu v tnh thi gian thc ca h thng thi gian thc: chnh xc (a), chnh xc tng i (b, c) v tng i lng lo. Nh vy khi p dng, ta c cc thit b ghp ni m c th k thut chc chn s ri vo cc trng hp trn, gip hnh thnh chin thut x l. m hnh trn khung thi gian T l yu t quan trng, v l khung thi gian khng th nh hn c khi xem xt trn mt HTN thi gian thc, tuy nhin T khc nhau cho cc h thng khc nhau. Gii php cho T ph thuc vo la chn thit k phn cng (c bit l tc ca CPU) v k nng vit phn mm h thng v phn mm ng dng. Tnh ng thi: H thng phi c kh nng phn ng v x l ng thi nhiu s kin din ra. V d, cng mt lc mt h thng trong vai tr l mt b iu khin PID, c yu cu thc hin nhiu vng iu chnh, gim st ngng gi tr nhiu u vo, cnh gii trng thi lm vic ca mt s thit b khc Tnh tin nh: D on trc c thi gian phn ng tiu lch, thi gian phn ng chm nht cng nh trnh t a ra cc p ng. V d, nu mt b iu khin phi x l ng thi nhiu nhim v, ta phi tham gia quyt nh c v trnh t thc hin cc cng vic v nh gi c thi gian x l mi cng vic. Nh vy ngi s dng mi c c s nh gi v kh nng p ng tnh thi gian thc ca h thng. X l thi gian thc X l thi gian thc l hnh thc x l thng tin trong mt h thng m bo tnh nng thi gian thc ca n. Nh vy, x l thi gian thc cng c cc c im tiu lch nu trn nh tnh 180

b ng, tnh chun xc, thi gian chnh xc, tnh ng thi v tnh tin nh. c th phn ng vi nhiu s kin din ra cng mt lc, mt h thng x l thi gian thc s dng cc qu trnh tnh ton ng thi. Qu trnh tnh ton l mt tin trnh thc hin mt hoc mt phn chng trnh theo tun t do h iu hnh qun l trn mt my tnh, c th tn ti ng thi vi cc qu trnh khc k c trong thi gian thc hin lnh v thi gian xp hng ch i thc hin. Cc hnh thc t chc cc qu trnh tnh ton ng thi: X l cnh tranh: Nhiu qu trnh tnh ton chia s thi gian s dng ca mt b x l. X l song song: Cc qu trnh tnh ton c phn chia thc hin song song trn nhiu b x l ca mt my tnh.
X l phn tn: Mi qu trnh tnh ton c thc hin ring trn mt my tnh.
Trong cc hnh thc trn y th hnh thc x l cnh tranh c vai tr ch cht. Mc d h thng iu khin c th c nhiu trm, v mi trm c th l mt h a vi x l, s lng cc qu trnh tnh ton cn thc hin thng bao gi cng ln hn s lng vi x l. Trong khi mt vi x l khng th thc hin song song nhiu lnh, n phi phn chia thi gian thc hin xen k nhiu nhim v khc nhau theo th t ty theo mc u tin v phng php lp lch.
Phn loi h thi gian thc

Nh trnh by trn th h thi gian thc c tnh rng buc thi gian v mi x l u c thi hn cht (deadline). Vy thi gian y qui chiu theo cch no ? Ging nh trn my tnh ni chung ta c h thi gian thc mm (soft real time system) v h thi gian thc cng (hard real time system). Hai loi h thi gian thc ny khc nhau ch no, cch nh gi s dung sai ca thi hn cht, tnh hu ch ca cc kt qu tnh ton sau thi hn cht, v s nh gi ngt ngho khi ri vo thi hn cht. Vi h thi gian thc cng, mc dung sai ca thi hn cht l rt nh c th bng khng, cc kt qu tnh ton sau hn cht khng c gi tr, do nhng pht sinh sau hn cht c coi l thm ha. Trong khi dung sai h thi gian thc mm l con s khc khng, cc kt qu tnh ton sau hn cht li c tnh cht khu hao, cho nn gi tr ca kt qu vo lc i qua hn cht vn c ch. h thi gian thc cng: l h m dung sai ti hn cht xp x bng khng. Ni cch khc phi ng thi im nu khng s l thm ha. Cc tiu ch h thng nh sau: - Phi m bo khng bt k mt s kin ti hn (critical event) no b s c trong bt k hon cnh no ca h thng; - tr p ng cho s kin rt nh (xt theo tng lp ng dng); - Cc s kin c tnh chu k phi c m bo thc hin ng chu k. Khi thit k h ny cn tnh kt qu tnh ton c c trc hn cht trc khi h pht ra p ng. 181

h thi gian thc mm: l h phi hp thi gian nhng hn cht c tnh mm do. Nh vy hn cht c th c nhiu mc, hn cht vi thi gian T c tnh vi tr trung bnh, xc xut p ng a ra nm trong cc mc khc nhau vi tr trung bnh v chp nhn c. Tuy khng gy ra thm ha h thng nhng phi tr gi khi tr h thng tng t l thun ty thuc vo ng dng. Cn c c ch b tr loi tr tr ny.
[
real time computing: the objective is to meet the individual timing requirement of each task correct behavior depends on both (1) correct computation and (2) time at which results are produced system that must react within precise timing constraints to events in the environment characterized by a deadline should be predictable (when the timing constraints cannot be met, this must be notified in advance, so that an alternative (scheduling) plan may be planned, and possibly avoid the catastrophe) real time applications the most important features timeliness, design for peak load, predictability, fault tolerance, maintainability. Difference between Hard and Soft Real-Time Systems Hard Real-time systems A real-time task is said to be hard, if missing its deadline may cause catastrophic consequences on the environment under control. Examples are sensory data acquisition, detection of critical conditions, actuator servoing. Soft Real-time systems A real-time task is called soft, if meeting its deadline is desirable for performance reasons, but missing its deadline does not cause serious damage to the environment and does not jeopardize correct system behavior. Examples are command interpreter of the user interface, displaying messages on the screen A hard real-time system guarantees that critical tasks complete on time. This goal requires that all delays in the system be bounded from the retrieval of the stored data to the time that it takes the operating system to finish any request made of it. A soft real time system where a critical real-time task gets priority over other tasks and retains that priority until it completes. As in hard real time systems kernel delays need to be bounded
182

H thi gian thc gn lin vi tng lai ca cc h thng nhng. Cc HTN trc y n gin, nh cc thit b hot ng c lp (automous device), c chu k sng di. Tuy nhin ngy nay, cng nghip nhng tri nghim mt s chuyn i mnh m vi cc s liu nh sau (bo co ca Gartner Group): Chu k pht trin trn th trng nhanh chng, ch trong vng 6 n chn thng; Ton cu ha dn n xc nh li thi trng v khng gian ng dng; Kiu kt ni cc h thng c dy v khng dy, tr thnh khng th thiu cc thit b nhng; Cc thit b in t ngy cng tinh vi; Kt ni cc HTN l lnh vc ng dng mi v ph thuc vo h tng mng (LAN, Internet, Extranet, ); Tc x l ngy cng nhanh theo t l transitor trn chip theo nh lut More: tng s transistors/vi mch tng gp i c sau 18 thng. Tt c nhng iu vi h thi gian thc s lm cho HTN c c tnh x s chnh xc theo thi gian thc. 3.2.3 H iu hnh thi gian thc (RTOS) H iu hnh thi gian thc (Real-Time Operating Systems RTOS), l loi h iu hnh h tr xy dng cc h thng thi gian thc. c bit RTOS c dng trong nhng ng dng in ton nhng c ti nguyn b nh hn ch v yu cu ngt ngho v thi gian p ng tc thi, tnh sn sng cao v kh nng t kim sot mt cch chnh xc. RTOS xut hin hai dng: cng v mm. Nu tnh nng x l ng vi mt s kin no khng xy ra hay xy ra khng nhanh, RTOS cng s chm dt hot ng ny v gi khng gy nh hng n tin cy v tnh sn sng ca phn cn li ca h thng. V RTOS v HTN tr nn ph bin trong cc ng dng quan trng, cc nh pht trin thng mi ang to nn nhng RTOS mi vi tnh sn sng cao. Nhng sn phm ny c mt thnh phn phn mm chuyn dng lm chc nng cnh bo, chy cc chng trnh chn on h thng gip xc nh chnh xc vn trc trc hay t ng chuyn i sang h thng d phng. Hin thi RTOS sn sng cao h tr bus Compact PCI ca t chc PCI Industrial Computer Manufacturers Group, bus ny dng cho phn cng c th trao i nng. RTOS c rt nhiu dng. Sn phm thng mi nh VxWorks v VxWorks AE, u ca Wind River Systems Inc; VxWorks AE c thit k vi tnh sn sng cao, h tr kh nng gi thng ip phn tn v c th chu li. RTOS cho php lp trnh vin tch bit th vin dng chung, d liu v phn mm h thng cng nh ng dng.
183

LynxOS l loi RTOS cng, lm vic vi Unix v Java. QNX chy trn b x l Intel x86 vi nhn ch c 10 KB. RTOS ca gii nghin cu gm c Chimera ca i hc Carnegie Mellon. y l h thng a nhim, a b x l thi gian thc, c thit k to s d dng cho cc nh lp trnh trong vic ti cu hnh v ti s dng m. Chimera nhm vo cc h thng r b v t ng. RTOS ca i hc Maryland, c tn l Maruti, h tr cho c ng dng thi gian thc cng v mm. Trong nhiu nm, ng dng da trn RTOS ch yu l trong cc h thng nhng cng nghip v mi gn y th chng c mt khp ni, t thit b y t c iu khin bng camera nh cho n my pha c ph, nhng ng dng tnh ton phn tn, c bit trong cc thit b truyn thng, ang thc y cc nh pht trin h iu hnh thc hin nghin cu v pht trin cc chun. Nh ni, RTOS to iu kin xy dng cc h thi gian thc, tuy nhin n khng m bo chc chn rng kt qu cui cng s l thi gian thc; iu phi c ci tin trong phn mm ng dng. RTOS khng nht thit cn phi c tnh xuyn sut cao, m RTOS cho cc tin ch, nu s dng chnh xc, th c th m bo tha mn c yu t hn cht (deadline) bi c tnh thi gian thc mm hay thi gian thc cng. RTOS s dng gii thut lp lch c bit, cung cp cng c cho ngi pht trin h thng kim nghim cc tp tnh ca h thng ch. RTOS c nh gi v kh nng cho p ng nhanh mc no, kh nng tin liu phn ng vi cc s kin ring bit, ch khng phi l s lng cc tc v x l c trong mt khung thi gian. Yu t then cht trong RTOS l thi gian ch x l ngt ti thiu, v thi gian chuyn i thc thi (context switching) gia cc tc v l ti thiu. Yu t th hai ngy nay t c vi h tr ca cc CPU i mi tc nhanh, kin trc hin i, cn t CPU Clock hn chuyn i gia cc tc v, v d nh kiu ng ng (pipeline), hay a lung. Cc yu cu c bn trn mt RTOS Cc thao tc rng buc vi thi gian phi d tnh c. Mi dch v ca HH ngng trn ca thi gian thc hin phi c m bo. Trong thc t c nhiu ngng d tnh, ty vo loi s kin h thooang chp nhn.
RTOS phi qun l chi ph thi gian chy tc v v lp lch chy cc tc v. RTOS chu trch nhim v cc hn cht ca cc tc v, trn c s s dng gii thut, k thut lp lch ph hp, v d c th lp lch kiu ofline, khi ng tc v theo thi im hay theo mc u tin, hoc theo cc gii thut online. Cung cp cc dch v thi gian phi c chnh xc cao, v d cc h thng in ng b thi gian gia cc nh my in cc vng cch xa nhau tnh theo mi gi, sai s ln l rt nguy him. RTOS c tc x l nhanh. Bn cnh kh nng d on, RTOS phi nhanh, c kh nng h tr cc ng dng c thi gian hn cht ch l vi phn ca giy ng h. Nhn ca RTOS cn gi l nhn thi gian thc, qun l ti nguyn h thng (b nh, CPU, cc b nh thi). Cc c ch bo
184

v nhn khng cn c. Tuy nhin mc h thng ng dng v l do nh an ninh, tnh c lp c th c c ch bo v. V d, cc thit b mng l cc HTN, c RTOS phi x l mt khi lc rt ln thng lng, c bo v bi cc phn mm mng ring bit nh lad ng dng lp trn HH. C hai kiu RTOS:
ng dng
Phn mm trung gian
TKTB
ng dng
Phn mm trung gian Phn mm trung gian
Phn mm trung gian
TKTB
H iu hnh
TKTB TKTB TKTB TKTB
nhn Thi gian thc
Hnh 3.9 RTOS nhn thi gian thc v RTOS a nng

HH RTOS a nng: cc TKTB c th l nm trong nhn, Cc phn mm trung gian, ng dng lp trn v kt ni vo nhn qua giao din lp trnh API -GHT, ngt mm. RTOS vi nhn thi gian thc: cc TKTB khng phi l thnh phn nhng trong nhn, c t trn nhn v ch c cc TKTB cn th a vo h thng. Cc phn mm trung gian v ng dng t ngay trn cc TKTB, ch khng thng qua API nh HH a nng. iu ny l r rng v hp l, v cc thit b ni trc tip vo h thng nhn iu khin trc tip thit b, m bo chi ph thi gian l t nht. y c s khc bit khi ci t TKTB, cc tc v s thao tc cc thit b, ch khng phi cc thit b hp nht trong nhn h uu hnh, do vy s:
Ci thin tnh tin nh, d on (predictability), v mi x l u i qua b lp lch; Cc TKTB c thit k cho tng h thi gian thc, hhieju chnh cho lp ng dng h thc hin. (Device drivers handled by tasks instead of integrated drivers: Improve predictability; everything goes through scheduler; Effectively no device that needs to be supported by all versions of the OS, except maybe the system timer.) (Def.: A real-time operating system is an operating system that supports the construction of real-time systems.) 185

Three key requirements: (C3-Peter-Marwedel (LH Viet) Embedded-systemdesign .pdf) 1. The timing behavior of the OS must be predictable. The services of the OS: Upper bound on the execution time! RTOSs must be deterministic: unlike standard Java, upper bound on times during which interrupts are disabled, almost all activities are controlled by scheduler:
2. OS must manage the timing and scheduling OS possibly has to be aware of task deadlines; (unless scheduling is done off-line). OS must provide precise time services with high resolution. 3. The OS must be fast Practically important. Chc nng chnh ca nhn RTOS l qun l ti nguyn CPU, b nh, qun l tc v, I/O, thc thi lin lc gia cc tin trnh, lp lch, mc u tin, thi gian, d on tnh hung s kin.
186
Nhn TROS
Lp lch (sche duler)
X l li
Dch v h thng
TKTB Qun l nh thi,

b nh to tr
Khi ng tc v
Chuyn i tc v
ISR
IPC
Tn hiu Semaphore Hng i
Thng ip
ng
Socket mng
Hnh 3.10 Cc chc nng nhn RTOS Trong qa trnh pht trin HTN vi RTOS cn tin hnh g ri m, v th nghim : Cc chc nng thc thi a tc v (C hay C++); ng h nh thi mm (software timers); ng h nh thi cng; Ch canh ca (watchdog); Module lp lch; iu khin chen ngang; Ngt; Ghp ni thit b ngoi v cc module TKTB; Cc chc nng IPC; Cc chc nng x l li; Th nghim phn mm trung gian dng g ri nhng trong h thng. Cc RTOS
Cc RTOS
T to
RTOS t Linux
microC, OS II (Freeware)
PSoS, VxWorks, Nucleus, WinCE, Palm, ...
Hnh 3.11 Cc h iu hnh RTOS 187

HTN thi gian thc
HTN c th c to thnh khi c phn cng nhng v phn mm h thng l RTOS. Mi quan h gia h thi gian thc v HTN nh hnh di y:
H thng nhng
HTN thi gian thc
H thi gian thc
Hnh 3.12 H thng nhng thi gian thc Hnh cho thy rng khng phi tt c HTN u l HTN thi gian thc v ngc li khng phi tt c h thi gian thc l HTN. V phn chung chnh l biu din ca HTN thi gian thc. Cn c cc HTN khng thi gian thc, v HTN thi gian thc c xy dng trn h thng khng thi gian thc. Cc HTN kiu ny tng i ph bin cho cc ng dng nhng khng i hi qu kht khe v c tnh, hay cn p ng nhanh. xy dng cc h nh vy cn c nhng la chn phn cng c tc x l nhanh, RAM ln, p ng cho ng dng. Phn mm h thng khng phc tp nhng hiu qu chy trnh cao. V d cc dng PC 104 nhng trn th trng ph bin chy vi HH DOS 6.4 cng tha mn cho nhiu lp ng dng nhng, hay chy vi Linux nhn 2.2 khng thi gian thc cng l la chn hp l. Mt s H iu hnh thng mi: pSOS+ 248 pSOS+ kernel 248 pSOS+m multiprocessor kernel pREPC+ runtime support pHILE+ file system pNA+ network manager pROBE+ system level debugger XRAY+ source level debugger OS-9 VXWorks VRTX-32 IFX TNX RTL RTscope MPV LynxOS-Posix conformance 188

QNX Windows NT QNX 4 RTOS Windows CE and embedded Linux. Palm OS Windows CE MS-DOS or DOS Clones Linux, including RTLinux and MontaVista Linux and Unison OS 3.3 PHN MM TRUNG GIAN (middleware) Trong gii hn nht nh, phn mm trung gian (gi tt PMTG) l bt k phn mm no khng phi l phi ca nhn HH, TKTB hay phn mm ng dng. Nhng cng c mt s HH hp nht PMTG vo HH (nhng khng vo nhn HN !), nh hnh 3.2 cp. V d vi cc HH my bn, rt nhiu PMTG c sn khi bn HH (cc dch v, mng, Sun embedded Java, Microsoft's .NET Compact Framework, CORBA ca Cty Object Management Group (OMG) v hp nht vi HH, mang li cho ngi dng c ngay cc tin ch khi s dng. Phn mm trung gian khng hp nht vo phn mm ng dng, l chia s s dng cho nhiu ng dng ng thi, hay ti s dng cc mi trng HH khc nhau. Trong HTN, PMTG c coi nh phn mm h thng, m v tr c th theo cc m hnh sau:
Hnh 3.13 V tr cua PMTG HTN Trn hnh ta nhn thy PMTG ging nh cu ni gia cc phn nm khc ca phn mm h thng, cung cp cc dch v cho cc phn mm ng dng, nh: an ninh h thng, kt ni mng, tryn thng cc b gia cc ng dng trong h thng, mang li s linh hot khi trin khai cc ng dng. Vi v tr trung gian, cc PMTG lm gim ng k tnh phc tp ca cc ng, v cc tin ch c sn v chia s ngay trong PMTG. Tuy nhin khi a PMTG vo h thng cng l tng thm mt lp xp chng, c tc ng ng k vo tnh m rng, hiu nng ca cc HTN, v PMTG tc ng vo tt c cc lp phn mm khc. 189

C nhiu kiu PMTG, nh PMTG hng thng ip (message oriented middleware (MOM)), mi gi i tng (object request brokers (ORBs)), th tc gi t xa (remote procedure calls (RPCs)) , Truy nhp c s d li ( database/database access) v cc lp giao thc mng (networking protocols). Tuy nhi khi phn loi c hai tp hp c bn: a nng (general-purpose): c ci t trn nhiu HTN khc nhau, v d giao thc mng, my Java o (JVM). Hai thnh phn ny u c trn cc thit b mng hin i. nh router, Concentrator, Switch, cc thit b dng SOHO, Xc nh (market-specific): dnh cho cc yu cu ring bit cho cc HTN ring bit. V d PMTG trn cc my thu hnh k thut s h tr kt ni mng TCP/IP, c xp trn HH v JVM. Cc PMTG thng l sn phm ca ring cc cng ty, cho cc HTN ca cng ty ch to v c bn quyn s hu tr tu. Cng c mt s l phn mm m ngun m c h tr bi cc t chc cng nghip s dng theo giy php GPL, v d Linux v cc PMTG chy vi Linux. V d cc PMTG trong cc HTN Ty vo phm tr ng dng v qui m xy dng, HTN c th c PMTG cng c th khng. Di y l cc v d cc HTN cn c PMTG, nh cc thit b truyn thng ni mng, th cc module v thit b mng l cn thit:
Hnh 3.14 M hnh cc lp mng theo TCP/IP, OSI v nh x vo HTN Lp 4, 3, 2 ca m hnh OSI c t trong lp phn mm h thng, nhng khng thuc nhn HH nhng. Cc lp 5, 5, 7 thuc phn mm ng dng, lp 1 thuc thnh phn phn cng. 190

Ngy nay hu ht cc ng dng WEB c s h tr ca Java, cho nn cc HTN u c vi Java Virtual Machine: 3.4 PHN MM NG DNG Phn mm ng dng chnh l mc ch chy trn HTN. HTN c ng dng nhiu lnh vc khc nhau, do cc ng dng l rt c th, v c pht trin bi nh ch to ra HTN. V d trong cng nghip ch to cc thit b cho t ng ha, robot, cc HTN c nhng bi ton ring gii quyt, tc l phi pht trin phn mm cho bi ton . V d HTN kn: mt b chuyn mch mng (switch) hot ng c, ngoi mt phn mm nhn iu khin, PMTG mng, cn pht trin cc module nh: - Chuyn gi d liu v/ra mt cng; - Qun l buffer vo/ra ca mi cng; - Truy vn a ch MAC trong gi tm cng u ra; - Chy phn mm chn ng i t cng v ti cng ra; - iu khin ng cc cng tc trong ma trn cng tc in t to ra ng ni t cng vo n cng ra; - Cp nht MAC vo bng c s d liu theo cu trc cc MAC thuc mt cng; - Qun tr thng lng; - Kt ni vi h thng qun tr qua giao thc SNMP vi t cch l Agent; - V d khc HTN m: trong ngi nh thng minh, cc HTN kim sot cc khu vc vi cc tc v c th, sau s ni vo my ch gia nh v my ch gia nh ni Interrnet. Login vo my ch qua mi trng ng dng WEB, ch nh c th kim sot nh mnh (qua video), hay ra lnh thc hin mt cng vic no trn mt HTN no . V ta c m hnh sau y:
Hnh 3.15 Cc ng dng WEB trong HTN, t lp phn mm ng dng. 191

Phn mm ng dng y l cc phn mm lin quan ti Internet: Web server, Navigation, email, Video-On-Demand Pht trin PMTG v phn mm ng dng nhng l ti nm phn khc, y khng cp chi tit. 3.5 KT CHNG Chng 3 cp nhng vn c s ca phn mm h thng bao gm: Trnh iu khin thit b (TKTB). Trong khi chng 2 cp ti cc gii php ghp ni thit b ngoi vo h thng, th phn ny cp ti cch nhn nhn mt s nt c t v cc bc khi vit chng trnh iu khin thit b. TKTB l phn pht trin c lp trn cc phn cng c th, hp nht vi phn mm h thng v phn mm ng dng truy nhp v trao i d liu gia h thng vi cc thit b ngoi.
Phn mm h thng. Phn mm h thng c m t thng qua cc bc: gii thiu cc khi nim c bn khi s dng m t v HH. c bit l HH a trnh, mi trng phn mm h thng c ci t ph bin trong cc HTN. Cc khi nin ny rt cn thit khi vit chng trnh ng dng cho HTN, cc s dng cc hm chc nng ca HH thng qua API kiu li gi hm (GHT). Nhng vn lin quan ti h thi gian thc, nhng c th c bn khi cp ti h thi gian thc cng c m t. Trin khai mt h thi gian thc trn mt h thng nhng yu cu nhng gii hn v vic chuyn ha phn mm h thi gian thc ln h thng nhng to ra mt h thng nhng thi gian thc. Phn mm trung gian v phn mm ng dng. Sau khi c TKTB, phn mm h thng v vit cc phn mm ng dng, HTN c th hot ng. Tuy nhin khi HTN nm trong mt tng th h thng ln hn, th mt lp phn mm khc, c lp, dng chung l cn thit, l cc phn mm trung gian. Cc phn mm trung gian c xu hng tiu chun ha, m, nhm to c s lin kt, kt ni cc HTN li vi nhau, v d nh mng my tnh. C nhiu phn mm trung gian c th tch hp vo HTN, ph thuc vo nhu cu v thc t trin khai. Cc phn mm ng dng l th hin mm cc tng khi thit k mt HTN v chnh l l do pht trin HTN. HTN ng dng cho mc ch g, cn to ra phn mm ng dng cho HTN , chnh v th s lng, chng loi, qui m, mc thng minh ngy nay rt ln, v pht trin rt nhanh.
3.6 CU HI CUI CHNG 1) Nu nh ngha TKTB. 2) a cc m vo m hnh cho thy v tr ca TKTB nm u trong kin trc h thng ( HTN khng c HH, HTN c HH). 3) Nu ra cc chc nng ca TKTB. 192

4) Trong cc CPU h tr nhiu ch hot ng (user mode, supervisor mode), th TKTB chy trong ch no ? Ti sao ? 5) Tng kt cc c t v h thi gian thc 6) Tng kt cc c t v h iu hnh thi gian thc (RTOS). 7) Th no l chen (preemptive) ngang trong h a trnh ? Cho v d ca hin tng chen ngang. 8) Gii thch hot ng ca tin trnh theo mo hinh trng thi ca tin trnh. 9) Th no l hn cht (deadline), k thut gii quyt hn cht nh th no ? 10) Lp lch l g trong cc h a trnh? ng dng lp lch trong h thi gian thc nh th no ? 11) Nu cc quan im thc hin lp lch. 12) Ch canh chng l g ? ng vai tr g trong h thi gian thc ? 13) Thit k mt gii thut cho ch canh chng vi cc iu kin gi nh ty . 14) HTN c cn ch canh chng, cho d HTN c hay khng c h iu hnh ? 15) HTN chy c lp, khng c s gim st ca con ngi. Nu h b qun, lm sao thot ra tnh trng ?
193
Chng 4: Thit k v ci t cc h thng nhng

CHNG 4 THIT K V CI T CC H THNG NHNG
Nhng vn k thut lin quan ti HTN c trnh by cc chng trc, c bit l phn cng v nhng khi nim v phn mm, TKTB, phn mm h thng, cc phn mm h tr nh PMTG, v phn mm ng dng. Chng tip theo a ra mt s tng thit k cc HTN, v phn cui l cch thit k phn cng v ci t phn mm cho mt HTN.
4.1
THIT K H THNG
HTN hp nht cc thnh phn phn cng v phn mm v ngi pht trin HTN phi c k nng c hai ch ny. Cc k nng gm kh nng thch ng v cch tip cn c tnh h thng, a ra mt quyt nh thit k trong khi phi la chn cc phn cng khc nhau cho ng dng nhng xc nh. Cc phn cng ph bin hin nay bao gm h thng xy dng trn CPU v d kiu vi iu khin (MCU-microcontroller) hay CPU x l tn hiu (DSP-digital signal processing) v cc h thng phn cng kh lp trnh (PLD-Programmable Logic Device, CPLDComplex Programmable Logic Device), mng cc phn t cng logic kh trnh (FPGA-Field Programmable Gate Array). Phn tch qui trnh la chn phn cng: Vic quyt nh chn phn cng cho HTN i ra t nhng kinh nghim c c t cc d n v cc hiu bit c tnh chuyn gia ca lnh vc HTN v cn chu nh hng ca nhiu yu t khc. Trc tin, phn cng phi c th thc hin c cc chc nng mong mun t ra bi cc yu cu thit k. Cc thuc tnh phn cng khi xc nh cc yu cu gm phm tr cc chc nng - s lng cc chc nng, kch thc ca cc cu trc d liu, c th thc hin trn phn cng v nu c tnh thi gian thc th l hiu nng - thc hin cc chc nng nhanh n mc no. Cn mt s yu cu khc khng mang tnh chc nng nh: tin cy, bo tr, tiu dng nng lng, kh kim tra h thng v cnh tranh trn th trng. Qui trnh chn phn cng: Kt ni gia cht lng ca h thng vi thuc tnh phn cng. Cc thuc tnh phn cng c trnh by nh hnh di y: H thng thuc tnh phn cng: Phn cng nhng thng thng t c tnh chun, do cc lp ng dng a dng. Tuy nhin c mt s yu cu chung c p dng:
194
Thuc tnh cc chc nng phn cng:
Thuc tnh hiu nng:
195
Thuc tnh kim tra c phn cng:
Thuc tnh th trng ca phn cng:
196

Thuc tnh ti s dng ca phn cng:
Thuc tnh cht lng ca phn cng h thng:
Thuc tnh c lp ca phn cng:
Thuc tnh s i c ca phn cng:
197

Khi thit k mt sn phm in t thng minh ni chung hay HNT ni ring, c th c nhng im xut pht khc nhau v phng php tip cn khc nhau, di y a ra mt trong cc cch tip cn . C th tm tt phng php lun thit k nh sau:
Cc thnh phn phn cng (HW)
Thit k phn cng
To phn cng
Kin thc chung thit k mt ng dng nhng
c t kin trc nhng
Chn phn mm chun (RTOS, phn mm trung gian)
Thc hin thit k: -Qun tr cc tc v cnh tranh, -Phn hoch phn cng/ phn mm, -ng thit k, -Bin dch, lp biu, -G ri, - ...
Thc hin phn cng
Sn phm nhng
Phn mm nhng
...
...
...
...
Ph chun thit k, Kim chng (hiu nng, tiu tn nng lng, tin cy, an ton h thng, )
4.1.1 Cc nn tng c bn khi xy dng kin trc HTN 1) Cn kin thc tt v phn cng (Thit k logic, kin trc my tnh, kin trc CPU, ngoi vi, h iu hnh ). Hiu bit tt v cc thnh phn hp thnh phn cng ca mt h thng nhng, c kh nng hiu v kim sot cc thit b ni vo HTN (hnh 3.17). 2) S tng tc vi th trng vo qu trnh xy dng HTN: Nhu cu ca th trng nh hng ti kin trc ca HTN v khng ch gii hn k thut, cng ngh; Cn nhn ra cc yu cu ca th trng c tc ng vo qui trnh thit k, bao gm: k thut, xu hng thng mi, nh hng ca chnh tr, x hi. im ny gi l chu k kin trc thng mi ca HTN (Architecture Business Cycle). T nhn thc cc yu cu, a ra gii php v phn cng/phn mm thng qua cc bc sau: nh ngha tp cc kch bn m tp phc tho mi mt trong nhng yu cu,
198

a ra chin thut c th p dng cho mi kch bn, c th dng to ra h thng nh mong mun, S dng kch bn phc tho cc chc nng h thng cn c, sau ln danh mc cc thnh phn phn cng, phn mm thc hin cc chc nng .
V d xy dng mt kch bn v hiu nng h thng nhng:

Cc ngun s kin tc ng vo H thng t bn trong Cc ngun s kin tc ng vo H thng t bn ngoi
Ghi nhn li s liu kt qu: thng sut, tr, mt d liu ... phn tch HTN ang pht trin
Mi trng pht trin tiuchun, mng tc cao, nhit , m,...
M phng cc tc ng ln hiu nng ca HTN t cc ngun
p ng ca h thng: s kin c x l theo thi gian thc ...
Hnh 4.1 Kch bn m phng hiu nng khi thit k HTN nh ra cc phn cng, phn mm c th p ng vi yu cu ca th trng. 3) nh ngha mu kin trc (architecrute pattern) v m hnh qui chiu: Mu kin trc h thng hay cn gi l phong cch kin trc h thng thc cht l mt mu m t (profile) ca h thng, cha ng cc c t khc nhau v cc thnh phn phn cng v phn mm, chc nng ca cc thnh phn bn trong h thng, mt s b cc (topo layout) hay cn gi l m hnh qui chiu, cc lin kt gia v giao din ghp ni gia cc cc thnh phn . Cc mu thit k c to da trn phn cng v cc thnh phn dn xut t cc yu cu chc nng hay khng chc nng qua cc thit k ban u (protopype), cc kch bn hay cc chin thut ni trn. Profile sau hp nht cng vi cc m hnh phn cng, m hnh phn mm c c mt thit k c th. 4) nh ngha cc cu trc c tnh kin trc Tip theo bc 3) l to ra kin trc ca HTN. Kin trc HTN s c hnh thnh bng cch phn nh ton b HTN thnh cc thnh phn phn cng, phn mm, sau cc thnh phn li c phn nh n chi tit. S phn nh c biu din bi t hp ca cc cu trc khc nhau v cc mu to ra im 3) ni trn c s dng cho vic xy dng mt cu trc c tnh kin trc ca HTN. Mt s k thut c s dng ph bin 199

trong cng nghip thiwjc hin quiu trnh trn l Rational Unified Process, hay Attribute Driven Design. V d m hnh 4 + 1: M hnh 4+1 ni rng ngi kin trc h thng c th to ra t nht 5 cu trc ng thi, mi cu trc c ci nhn khc nhau v h thng. Trong 4 cu trc thu nhn cc yu cu khc nhau ca h thng, cu trc th 5 l ph chun tnh hp thc ca thit k.
Hnh 4.2 Cc cu trc kiu 4+1 Cu trc logical l cu trc kiu modul c t cc thnh chc nng phn cng, phn mm, mi lin h tng tc chc nng gia chng, m h thng yu cu. Cc thng tin y s lm nn xy dng mt h thng thc t; Cu trc process bao gm cc cu trc thnh phn v cu trc kt ni, phn nh tnh tng tranh v ng b ca cc tin trnh trong h thng c h iu hnh. Cu trc ny m t cc yu cu phi chc nng (nh hiu nng, tnh hp nht h thng, ngun ti nguyn sn c, v.v) thch ng cho h iu hnh. Bng cch nhn t tin trnh, cu trc ny phc tho ra cc tin trnh trong h thng, c ch to cch lp lch, c ch qun tr ti nguyn. Cu trc allocation m t cch nh x phn cng/phn mm vo mi trng pht trin hp nht (integrated development environment-IDE) vi cc cng c: gi ri, bin dch, lin kt, s dng cho ngn ng lp trnh hp ng hay bc cao (C, C+). Cu trc deployment l m t lm th no trin khai phn mm vo phn cng. Phn ny cho bit cc phn cng cn c khi phn mm c xy dng i hi: thc hin code, x l d liu, tc ca CPU phi t mc ti thiu, tc BUS, tc trao i d liu Vi m hnh c nh ngha nh trn, th m hnh c phn mm v h thng c h iu hnh. Kin trc module cho php p dng m khng cn phi bit cc phn mm no c trong h thng hay ngay c khi h khng c phn mm h thng (nh mt s HTN n gin).
200

Thnh phn +1 l vic nh x tp cc kch bn quan trng nht v cc chin thut t 4 cu trc. iu m bo cc thnh phn khc nhau ca 4 cu trc khng c s xung t ln nhau, n n vic ph chun h thng. 5) Phn tch v nh gi kin trc v cc pha thit k Theo hng tip cn kin trc: kin trc c t cc yu cu; Theo hng cht lng thit k (cht lng v s lng): Cc kin trc khc nhau vi yu cu c cng cht lng nh nhau. nh gi xu hng ri ro h thng, hng hc c th; Hiu chnh, tinh chnh kin trc v p dng vo phn cng, phn mm. Cc bc ny c thc hin nh kiu phn hi v lm cho n lc t cc tiu ch trc khi a ra sn xut.
201

Xc nh sn phm
Phn tch cc yu cu
To kin trc h thng
Pha 1 Pht trin phin bn kin trc a ra phin bn kin trc Version 1... Xem li, nh gi Phn hi
Kt hp phn hi
a ra phin bn cui cng
Pha 2 Kt hp phn hi
Pht trin h thng
Th nghim,Xem li, nh gi Phn hi
Pha 3
Sn phm
Pha 4
Hnh 4.3 Cc pha thit k HTN 6) Vit ti liu Ti liu v ton b h thng theo cc chun ti liu. Ti liu v tng cu trc Ti liu tng th v kin trc h thng.
202

4.1.2 Phn hoch thit k phn cng, phn mm Tng quan: Cc HTN t phn ng thi gian thc (reactive real-time), hot ng vi cng cao, l cc h thng hn hp phn cng v phn mm, s dng cc b vi x l, vi iu khin, x l tn hiu (DSP), trong phn mm h tr tnh mm do linh hot, phn cng phi m bo tnh hiu nng cao. T cho thy thit k cc HTN l i mt vi cc thch thc nh: p ng thi gian (cng hay mm) ca h thng vi cc s kin, kch thc, trng lng, tiu th nng lng, tin cy, gi thnh. Cc phng php hin dng bao gm vic c t v thit k phn mm v phn cng tch ri. Mt c t thit k thng l cha hon ho, c vit bi ngn ng no v chuyn cho ccc k s phn cng v phn mm. Vic phn hoch phn cng-phn mm cn c lu tm trc tin v c chp nhn, tn trng, v bt k s thay i no qu trnh ny s dn ti cc thay i khc v lm cho qu trnh thit k s ko di. Cc nh thit k phi n lc rt nhiu mi th c th chuyn vo phn mm, ch chuyn mt phn ca thit k cho phn cng nhm m bo tha mn cc tiu ch v thi gian phn ng ca h thng. Vn y c th l: Cha y cc c t phn cng v phn mm, nn kh kim chng tng th h thng, do dn n s khng tng thch khi tip cn ranh gii gia phn cng v phn mm. Cc pht tho ban u s ko theo cc pht tho (b sung/tu chn) khc bn di. S chn tr cha c mt lu trnh thit k hon ho s gy kh khn cho vic s i v tc ng ti thi im a sn phm ra th trng.
C nhiu cch tip cn gii quyt vn thit k HTN, tuy nhin khng c cch no c th tha mn v t hiu qu nh mong mun. Di y s trnh by mt s tip cn khi thit k mt HTN. Thit k HTN l kt hp gii quyt mt h thng u cui bao gm c phn cng v phn mm. Do cn c nhng quyt nh phn no ca thit k s c gii quyt phn cng v phn no phn mm c c mt h thng vi nhng c im chuyn bit (thin v hiu nng), khc vi cc my tnh thng thng. C nhng x l phn mm li phi cng ha (gi l c silicon ha) m kt qu l hiu nng tnh ton nng cao. V d trc y, CPU 286/386 khi khng c vi chip FPU 387, mi php tnh du phy ng phi chy bng tp lnh mm, do nhiu phn mm cao cp khng hot ng c (AutoCAD chng hn). Cch la chn thit k nh vy gi l s phn hoch thit k. Nu tng qut ha khi nim gii thut thnh cc bc thc thi mt thit k, th gii thut nh mt kt hp ca cc thnh phn mn cng v thnh phn phn mm, v mi phn ca phn hoch cng/mm s thc thi mt gii thut. Tt nhin c th p dng gii thut thun mm (CPU khng c FPU), hay thun cng hoc kt hp c 2 (v d nh v ha my tnh). 203

V d: Gii thut thit k my in laser:
Hnh 4.4
Gii thut thit k my in laser: phn hoch cng/mm
D liu nhn vo t cng LPT, CPU phi chuyn i thnh xu ni tip lm u vo iu ch tia laser, quay cc gng chiu tia, quay trng in, pht tin nh in ln giy, t mc sy kh bn in, Kt qu mt cng sut in 5-7 trang /pht. Tng tc in ? Tng cng thm CPU Gii php nh vy l ti u ? Tuy nhin khi phn tch gii php thit k mt cch su hn, c th biu din thit k nh mt gii thut c nhng tc v c th cng ha, v d cng ha khi chc nng ghi laser ln cc phn t nhy nh sng trn b mt trng in, gii phng CPU khi tc v ny nh trc lm. Tt nhin phn kh s l cn phn cng rt tin cy v bn vng, mt vi mch kiu ASIC (Application-Specific Integrated Circuit- kiu vi mch c thit k dnh cho mt ng dng c th) s xut hin. Tuy nhin ASIC s lm tng s phc hp h thng thit k. Do vy nhm phn mm s phi n lc v hiu chnh phn mm rt t m, sao cho thm phn cng nhng khng qu phc tp v t , lm gi thnh tng thm. S phn hoch thit k cng v mm:
204

c t H thng (Specification) pht trin ban u (concept) Pht trin phn mm pht trin chi tit
Pht trin phn cng
Vit m (coding) thit k chi tit
Chy th (test)
Tng tc HW/SW
Thc hin phn cng
TKTB
firmware
Vit m cho
Th nghim phn cng
Hp nht phn cng phn mm
Th nghim
nh gi, ph chun sn phm
Hnh 4.5
Phn hoch thit k phn cng v phn mm
Cn c s tng tc pha phn hoch cng/mm hai nhm thit k: Tuy hnh thnh cc khi chc nng cng/mm r rng, nhng khi ranh gii vn cha th khng nh khi cc thch thc cha c a vo thit k. Cc cng c thit k phn cng (ICE, Simulation, ) s cho thy c th ci thin phn cng khi kt hp vi phn mm, trong khi phn mm chy th bng m phng trn phn cng nh gi tc x l. Ni cch khc hai nhm thit k cng/mm cn tng tc vi nhau b sung cho thit k cui cng. Bo mch sn phm l bo mch ch tuy nhin vn cha l bo mch thc ch to. Qu trnh tng tc s lp li cho ti khi cc ch tiu sn phm chp nhn c, trc khi tin hnh lm sn phm mu thc. Cc cng ngh thit k ngy nay to iu kin hai 205

nhm thit k lm vic vi nhau cht ch v tit kim nhiu thi gian, hn ch ti a cc ri ro cho ti khi ch to sn phm. Khi no th quyt nh phn hoch cng/mm ? Khi phn tch hu ht (hay tt c) cc gii php trnh by gii thut thit k. T s thy phn no ca gii thut s nm phn cng, phn no phn mm, l ti u. Mt s qui tc c th dng cn nhc: Tng tc x l, c th p ng bng phn cng, nhng tng gi thnh, v i khi phi thit k li chip x l ! Phn mm c th ch ng bng m phng, khng ch i c phn cng honh chnh mi th nghim, vit code tht hp l cng s gim chi ph phn cng. D sao th phn cng cng c nhng li thot, l s la chn cc b x l a vo thit k (hay dng ASIC, ri i n h thng trn chip (System on Chip-SoC). Phn cn li l thit k bo mch tng th, code ha mt s x l phn cng thnh phn mm sn (firmware). Kt hp phn cng/phn mm. Hin nay cc sn phm thng mi c pht trin theo k thut ng thit k phn cng v phn mm-ng kim nghim (Hardware/software codesign and co-verification). Nu theo thit k truyn thng sau khi lm phn hoch cc phn thit k thc hin tng i c lp, thi gian phn hi-hiu chnh c phn cng v phn mm s lu, do vy chi ph nhiu thi gian hn cho sn phm cui cng. Ngy nay mt qui trnh thit k mi pht trin, trong thit k phn cng v phn mm tin hnh song song, cc phn hi-hiu chnh thc hin lin tc, cho ti khi c kt qu tt nht qua ng kim nghim. Trong cng ngh ny phn cng c trnh din bi ngn ng m t phn cng (very-high speed integrated circuit hardware description language - VHDL) v l phn cng o phn mm hot ng. Nh vt qu trnh thit k c th mm ha v s kt hp hi ha l rt r rng.
206
V d k thut thit k ASIC: l cuc cch mng trong thit k cc HTN. Sn phm ASIC c th tm thy, nh cc Chipset trong PC, chip x l m thanh, tng tc ha, chip cho MODEM, Qu trnh thit k c tn l bin dch bn dn (silicon compilation), trong phn cng v phn mm c biu din bi cc tp d liu ca ngn ng thit k cao cp. Nh vy HTN s c c t nh mt c s d liu mm (software database): mt phn m t kin trc phn cng, mt phn m t cch iu khin hot ng ca phn cng. y s phn bit gia phn cng v phn mm c tnh mp m: thit k phn cng li nh l thit k phn mm. 207
-Thit kt gii thut - Vit m C/C++ Co-Design, Co-Cerification pha: -nh ngh kin trc/ chc nng -Phn hoch HW/SW - Thit k gii thut - Vit m HDL
Vit m m phng phn cng
Bin dch thnh *.obj
Hp nht
- vit cc vector th nghim -Chy m phng
Bin dch thnh CSDL linh kin
4.1.3 Xy dng bo mch khi pht trin h thng Trin khai cc yu cu m t phn 4.1.1 khi thit k bo mch s c th nh sau: 1) t vn : Mc ch thit k HTN, mc tiu cn t c, tnh thng mi ; 2) Xc nh HTN: Xy dng mt m hnh chnh tc (formal model) ca h thng vi cc yu cu sau y: Xc nh chc nng: xy dng tp cc mi quan h tng minh hay khng tng minh lin quan ti u vo/u ra, v thng tin trng thi bn trong ca h thng. Xy dng tp cc thuc tnh m thit k s phi tha mn. Kt hp cc thuc tnh v tp cc quan h vo/ra, trng thi h thng, xc nh li cc chc nng h thng. Cc thuc tnh bao gm: Cc thuc tnh c tnh k tha cc h thng tnh ton (my tnh s); Cc thuc tnh c th kim chng trn mt chc nng; Cc thuc tnh phi c kim chng trn cc c t phi c khi cc tiu ch u vo xut hin.
Xy dng tp cc ch s hiu nng nh gi thit k theo cc tiu ch: gi thnh, nng lng. tin cy, tc x l, kch thc Xy dng tp cc khc bit coi nh nhng thch thc ca thit k, ra gii php gii quyt. Thc hin tinh lc thit k c thit k t tng n m hnh:
208
c t
Lnh khng iu kin Qun tr tp (FSManagem ent) Dng d liu S kin ring bit
Sng lc
Phn hoch lp chc nng
Bin dch
Tng hp phn mm
Tng hp hnh vi, phn ng
Tng hp lun l (logic)
M hnh
M hnh CPU M hnh CPU M hnh lun l (logic) M hnh lun l (logic)
Hnh 4.6. Xy dng m hnh hnh thc: Bc sng lc s dng cch tng hp phn cng v phn mm chuyn ha xc nh chc nng vo m hnh phn cng ca thit k. M t h thng phn ng nh th no vi cc u vo, Cng c m hnh ha s vn ng ca h thng, v d phng php li Petri (Petri nets) hay biu trng thi (StateCharts). Yu cu ca sn phm s c: a ra m t sn phm; 3) Thit k phn cng: ln m hnh kin trc ca bo mch chnh, la chn cc thnh phn phn cng;
209
Rx
SIO
Tx
KEY
DISP
-Gi tr t -cng tc, -Trng thi, -tn hiu ...
Digital inputs
CPU, ROM, (FLASH), RAM, PORTS, BUS
Digital outputs
-n hiu (LED), -Motor bc, -cng tc on/off - ... -motor lin tc -van in -my o - .
-nhit -p sut, -mc, v tr, - ...
Analog inputs
Analog outputs
CLK, RTClock
HH, PMTG,ng dng nhng
Timers, watchdogs
Hnh 4.7 Bo mch HTN 4) M hnh t chc ghp ni cc thit b ngoi, s lng, chng loi cc thit b ngoi; 5) Thit k phn mm: phc ha cc phn mm: M hnh cc lp phn mm; C hay khng c cc phn mm trung gian; C hay khng c h iu hnh, loi h iu hnh s pht trin cho phn cng ch; Phn mm iu khin I/O (TKTB); Phng thc lin kt cc phn mm theo nguyn l lp xp chng; Cc phn mm ng dng.
6) Tng tc gia phn mm v phn cng, tinh lc phn cng, phn mm 7) Vit phn mm trn h pht trin; 8) Vit ng dng trn h pht trin; 9) Th nhim chng cc phn mm v hiu chnh phn mm trn h pht trin; 10) Hp nht phn cng v phn mm vo sn phm ch th (prototype): Np phn mm vo h thng ch: 210

Np cc TKTB, th nghim kt hp TKTB vi cc cng ghp ni trn bo mch, hiu chnh m; Np phn mm h thng (h iu hnh, hay monitor, ) v th nhim cc chc nng ca h iu hnh c v khng c TKTB, hiu chnh m; Np phn mm trung gian nu c, th nhim kt hp vi h iu hnh, hiu chnh m. Np th mt ng dng, th nghim, chnh sa m.
11) Hp nht h thng, tng cng th nhim cc chc nng vi cc iu kin phc tp gi nh, thi gian thc, p ng nh gi sc chu ng ca mi trng vn hnh trong thc t 12) Lm h s, ti liu. Tm tt qui trnh thit k HTN Cc qui tc thit k 1) Nn tng kin thc thit k HTN : Khoa hc v my tnh v k thut in t; 2) Thit k vi mch vi ngn ng phn cng Verilog hay VHDL (FPGA, ASIC); 3) Kh nng cng ngh v nhng gii hn cng ngh phn cng. 4) Lnh vc ng dng HTN rt rng, thit k phi hng vo i tng ng dng c th; Vi cc xu hng: - Gia tng kch thc m chng trnh: 16 64 KB ln n 64kB n 512 KB, - Ti s dng cc thnh phn cng (CPUs, micro-controller, DSPs) v mm (device drivers), - C s hp nht cao trong 1 h thng (DSP, mng, RF, CPU 32 bit, IO processors kiu Intelligent Input/Output-I2O). 5) S dng phn mm c sn, phn mm ti s dng, m ngun m. 6) Cng ngh lp trnh (ngn ng lp trnh, h pht trin phn mm); 7) Thit k vi mch (dng VLSI, ASIC), thit k h thng in t (s, analog); 8) H thng x l kiu thi gian thc (thi gian thc cng, thi gian thc mm). Cc bc thit k 1) Xy dng c t HTN, m hnh ha HTN s c thit k, thc nghim vi cc gii thut lin quan; 2) Tp hp v m t phn cng c bn : ghp ni c s, truyn thng, cng ngh tnh ton ng dng vi in t, cng ngh b nh, cc thit b ghp ni vo h thng. 3) H thng phn mm s c: iu khin thit b, phn mm trung gian, h iu hnh, phn mm ng dng 4) Phn hoch, chn lc cc phn ca thit k: phn cng, phn mm. mi phn, phn r thit k thnh cc phn nh hn, xy dng cc mi tng tc gia cc phn ; 211

5) S dng cc cng c m phng thit k chy m phng phn cng, phn mm v kt hp c hai trn m hnh o; 6) Cc phn mm v phn cng ti hn (rng buc thi gian) cn th nghim v iu chnh theo kiu sn ha: phn mm kt hp gia phn cng v phn mm, trong x l khi vi module chia s khai thc chung mt phn cng. Pht trin gii thut lp lch ti u. 7) Th nghim trn bo mch phn cng (prototype) vi CPU chn. 8) G ri v tinh chnh phn cng, phn mm; 9) Hon thin sn phm. 4.2 CI T V TH NGHIM HTN Phn tip theo s cp n vic thc hin xy dng mt HTN. Gi nh rng ta c mt d n pht trin mt ng dng nhng no , v hy bt u vi cng vic thit k HTN . 4.2.1 Chn CPU cho thit k Sau khi phn tch yu cu ca HTN t ra, trn c s cc tc v m HTN s thc hin, s dn n vic xc nh tnh nng ca b x l trung tm (CPU). Nh gii thiu c nhiu loi HTN v mi loi c xy dng trn mt kin trc vi CPU khc nhau, v trn th trng hin ti s cho nhiu la chn ph hp. Nh phn loi cc dng CPU dng cho HTN, mt s cu hi cn t ra khi thit k nh sau: 1) Ch to CPU ring bit kiu ty bin (customize) vi cc cng ngh nh ASIC ? Vn s l chi ph cho la chn ny ? R rng hng pht trin ny mang li nhiu u im nh: hc thut ch to chip, ch ng sng to v.v Tuy nhin cn c kin thc v ch to mch, c bit l mch c mt tch hp ln v rt ln, kin thc v kinh nghim thit k logic theo khi chc nng, v tng kin trc v chc nng ca mt CPU phi rt r rng. Hn na trang thit b s rt t. Ni chung la chn ny i hi mt i ng rt mnh, chuyn nghip v khi lng kin thc chuyn ngnh rt su. 2) Tm hiu th trng CPU cho ng dng nhng: bo mch controller vi microprocessor truyn thng, bo MCU (micro-controller) vi cng ngh mi PIC (Programmable Interface Controller ca Microchip Technology), PSoC (Programmable System-on-Chip ca Cypress Semiconductor.), kt hp vi PFGA (Field Programmable Gate Aray ca Xilink) hay cc sn phm khc. 3) Mt s tng la chn CPU cho HTN: La chn CPU c th trn c s xc nh c th sn phm hay nhu cu m th trng ch i. Tuy nhin tt hn c l ngi thit k HTN phi cn nhc c CPU tha mn ng dng nhng mnh ang xy dng. Di y l mt s tiu ch h tr khi thc hin chn CPU cho thit k: 212

HTN s kt ni vi cc loi ngoi vi (sensors) no ? c tnh k thut ca cc ngoi vi ? Danh sch ny s cho bit s cng vo/ra (I/O) cn c m CPU h tr. C bao nhiu chng trnh, cn bao nhiu khng gian d liu (bao gm c cc ngn xp, khng gian b nh cp pht ng cho chng trnh (heap)) cn cho h thng ? C bao nhiu ngt h thng cn ? V chc chn l nh vy ? S lng cc cng vo/ra m thit k s s dng ? Loi x l no rng buc nht v thi gian ti hn (critcal-time) m CPU phi thc hin ? Loi cng c pht trin no (cho c phn cng v phn mm) c sn cho CPU chn ? (m ngun m, phn mm trung gian ngn ng bc cao khng ph thuc CPU nh Java ngn ng lp trnh, cng c bin dch hng ch ) . Trong trng hp CPU trn bo mch (CPU on board), cng cc thnh phn hp nht, ngun nui, cng c th, th gi thnh thc s l bao nhiu ? C cc loi thit b sn c no ghp c vo h thng hin ti v h tr thit b mi ? Phn mm s lm vic vi phn cng nh th no v ngc li ? (Pht tin ng dng s tng thch ?). Loi cng c pht trin no sn c, v d hp ng, bin dch C, C+, m phng .. ? Khng gian a ch m CPU h tr l bao nhiu ? KB, MB, vi MB n GB ? (Lu l HTN s dng hai loi b nh chnh: b nh chng trnh ng dng, h iu hnh l flash, ROM, UVPROM, EEPROM. Loi th hai cho d liu l RAM (Ram tnh, hay RAM ng). CPU Clock, gi/hiu nng ca CPU ? l mt s tiu ch khi chn CPU cho thit k mt h thng nhng. Nhng CPU khng phi l tt c, cn c cc thit b, ghp ni cng cn xem xt v tnh tng thch, c sn trn th trng c gii php hp l. 4.2.2 Pht trin HTN C nhiu gii php la chn pht trin HTN, c th nu ra nh sau: 1) Dng bo mch thng mi, my tnh nhng chun, kiu PC gi l PC/104 (embedded computer standard kim sot bi PC/104 Consortium) vi mt s CPU a nng (dng low-cost x86 processor). Loi ny thuc kiu controller, c h iu hnh, c IO nh my tnh thng thng, lp theo kiu xp chng ln nhau, hnh khi: motherboard, analog-to-digital converter, digital I/O (data acquisition) module, ghp ni vi cc ngoi vi khc c trn th trng, BUS ISA, PCI, k c thit b thu tn hiu GPS, mng khng dy IEEE 802.11, v USB ( cp chng 1). H iu hnh: DOS 6.4, Linux, RTOS.
213

Vi gii php ny, cng vic tip theo phn ln l pht trin cc phn mm ng dng, cc trnh iu khin thit b, th nghim v a vo ng dng. Nu lp ng dng nhng nh, dng gii php ny s lng ph. Tham kho thm: http://www.controlled.com/pc104faq/ http://www.pc104.org/pdfs/PC104_trade_show.pdf 2) Thit k theo yu cu (customize) Gii php ny c th s dng xy dng cc HTN vi cc qui m rng, t n gin n phc tp. Qui trnh v k thut thit k nh trnh by cc phn trn. Chng loi CPU cho gii php c ph rt rng. Hin nc ta ph bin cc cng ngh sau y: dng chip PIC ((Programmable Interface Controller ca Microchip Technology), hay PSoC (Programmable System-on-Chip ca Cypress Semiconductor) xy dng cc microcontroller. Cc sn phm loi ny dng Kit hay linh kin ri c cng c pht trin bn km. V d thit k bo mch t linh kin: Xem v d Hnh 2.18- Cu hnh ti thiu bo mch CPU 8085, RAM/ROM/Ports vi CPU 8085, ROM 8755, port 6165 4.2.3 H pht trin, cng c xy dng phn mm v np vo HTN ch H pht trin:
Mi trng pht trin cho: h pht trin cng c - HTN ch
214

Phn mm ch trong mt h thng nhng, s gi tt l code image:
H thng nhng : cc phn mm v phn cng Xy dng, pht trin phn mm bao gm: Lp trnh, g ri, m phng (cng/mm), hiu chnh,
Hnh 4.8 H pht trin HTN 215
Qui trnh pht trin phn mm ch np vo HTN ch. Np vo bo mch ch Th nghim, nh gi Hon chnh.
216

H pht trin: PC + phn mm pht trin
App C sources
C compiler C header files (*.h) Preprocessing Compiling *.obj
Locator
Linker
*.exec
Asembler
ROM image
libs ROM burner RTOS Kernel

0
Np soft vo HTN
0 a1 a2 a3 a4 GND 0 Vcc1 b1 b2 b3 b4 5 1 6 2 7 3 8 4 0 a1 a2 a3 a4 GND 0 Vcc1 b1 b2 b3 b4
4 a4GNDb4 8
3 7
2 6
0 1 a1Vcc1b1 2 a2 b2 3 a3 b3 4 1 a4 b4 a1 b1 8 5 7 6 5
a3 b3
a2 b2
1 2 3 4
5 6 7 8
a4 GND b4
a3
a2
a1
a4
a3
a2
a1 Vcc1 b1
init
b3
b2
b1
b4
b3
b2
RAM
ROM
HTN
Hnh 4.9 Qui trnh pht trin phn mm cho HTN Cng c lin kt (linker) v nh v (locator) to ra tp thc thi kiu ELF (executable and linking format) dng nh phn (kiu image, hay code image) c th nh x hay np vo ROM.
Hnh 4.10 S n gin h thng v nh x b nh vo EEPROM hay FLASH ca HTN ch. 217

4.2.4 Khi ng h thng Sau khi phn mm pht trin t c cc chc nng c bn, n lc np vo HTN ang xy dng chy th. Trong mi trng hp, d HTN c hay khng c h iu hnh, u cn c mt qui trnh, gi l khi ng h thng. Khi ng h thng (hay boot) nm trong qu trnh thit k, kt hp mt vi yu t nh sau: To cng c: S dng chng trnh np (loader) vi chc nng s np tp nh (code image) t h pht trin (my PC) vo HTN:
Loader c vit ring v s c ghi vo boot ROM. Mt phn a ch ca boot ROM s cha boot image (l phn code do k s phn cng vit) s thc hin cc m cn thit theo qui trnh bt my ngui (Power ON System Test-Cold Boot): khi ng phn cng, a cc vi mch, phn vng b nh, khng gian a ch vo trng thi ban u. Sau ht boot loader nhy ti a ch RESTART hay START ca phn mm h thng chuyn iu khin cho n. T lc h thng bt u hot ng. Trong qu trnh pht trin, cc phn mm cn c bao gm: - Boot h thng np vo EEPROM/ROM; Boot ROM cn c tin ch c kh nng kt ni vi h pht trin, v d nh giao thc TFTP, dung ti phn mm vo FLASH; - Phn mm h thng (Monitor hay RTOS); - Phn mm ng dng nhng; - Ti phn mm h thng v cc ng dng nhng vo FLASH. Nu np vo EEPROM ri th khng cn bc ny).
218

Nguyn l khi ng h thng: Nhc li nh dng tp thc thi ELF (Executable and Linkable Format)
Phn program header table ch ra cc phn on c s dng lc chy chng trnh (run time) v phn header lit k tp cc phn nh phn : .text: m chng trnh, .rodata: d liu ch c, .data: d liu c/ghi c. Phn cng lin quan ti RESET ca loi CPU s dng. Khi ng c hai cch: khi ng ngui l khi bt ngun my, v khi ng nng, tc RESET nng khi my bt ngun, hay chnh xc l khi ng li nng. Khi thit k phn cng phi c mch in t to ra xung RESET v ni vo chn RESET ca CPU. rng ca xung ny bng my CPU-Clock ph thuc vo tng loi CPU s dng v cn thc hin chnh xc. u vo ny thc t l t hp ca mt s tn hiu quan trng, c tc ng khi ng li my. V d tn hiu t watchdogs, cc s kin s c h thng, cn thot khi vng lp qun v c th c mt vi tn hiu khc, ph thuc vo thit k. Phn mm thc hin c tn ph bin l: boot, bootstrap, hay bootloader (vi h c h iu hnh). Phn m thc thi gi l boot code. Thng thng m ny nm trong ROM nh l mt phn ca BIOS. Mt s CPU c kin trc vi mt b m chng trnh (Program Counter PC) t ng cu hnh cha a ch ca ROM m ti a ch l lnh u tin s c thc hin, hay phc tp hn l lnh nhy ti mt bng chn ch my s khi ng (v d khi khi ng h thng c h iu hnh, vi Intel X86, ban u chy ch thc (real mode), sau np nhn h iu hnh v chuyn sang ch chy bo v (protected mode) vi h iu hnh).
219
Hnh 4.11 nh x thc thi chuyn vo b nh ca h thng .rodata: Cc thng s khi ng h thng, thng khng i, do d ROM; _loader hay _wflash : start code hay loader, code ny RAM hay FLASH; _monitor: m ca chng trnh monitor. .sbss (block started by symbol) hay ni cha cc bin tnh c hay cha khi ng vi gi tr bng 0 trong ngn ng C), v, .sdata: HTN dng monitor hay OS c ti nh v vo RAM; .text: m chng trnh h thng v m ng dng nhng. Khi hiu c phc tho b tr b nh ca CPU s dng, s d dng hn khi np m thc thi vo h thng. Hy theo di nh trn hnh 4. 11: - Sau khi kch hot RESET CPU thc hin khi ng cng, y CPU bt u thc hin mt chng trnh, hay mt m nhy ti mt on m khc tip tc qu trnh khi ng, gi l khi ng mm. - Khi ng mm (start code, hay loader OS) thc hin mt lot cc thao tc to ra s phn chia b nh thnh cc vng chc nng (STACK, DATA cho h iu hnh, nhn h iu hnh, ), khi ng cc vi mch vi cc thng s c trong BIOS DATA ROM, v np h iu hnh v chuyn ti lnh u tin ca nhn h iu hnh. Nhn tip tc khi ng cc c s d liu ca nhn, khi ng cc dch v nhn v chuyn sang ch bo v. Vi cc bo mch thng mi, start code cho HTN cn kh nng ty bin p dng cho cc bo CPU khc nhau. c chc nng ny, b dch C t ng sinh code c cha tp hp ng tch ring cha m ca start code. Cc tp ny c tn crt0 hay crt1 (crt=C Run Time). Ty bin cc tp ny c start code ph hp vi bo mch. 220

i vi cc sn phm bo mch trn th trng, cc bo mch u c gi phn mm h tr i cng (board support package (BSP)) vi m chng trnh cho h iu hnh la chn chy trn bo mch. Thng thng l mt loi bootloader kt vi thit b cha h iu hnh v cc TKTB (device drivers) iu khin tt c cc thit b trn bo. V d v mt phn mm h tr : Monitor Mt gii php tch hp loader v boot image l s dng mt phn mm monitor nhng. l mt loi ng dng nhng m cc nh sn xut cc HTN cung cp s dng trong qu trnh ngi dng pht trin bo mch nhng ca h. moni t giuap ngi pht trin phn mm cho HTN kim tra, g ri h thng ch ngay khi cho h hot ng (run time). Ging nh boot image, monitor c thc hin khi bt ngun v n s khi ng h thng: Khi dng cc thit b, nh cc cng cc kt ni (ni tip, song song, mng). khi ng cc b nh thi, Khi ng a ch ca b nh ti phn mm h thng, Khi ng vi mch iu khin ngt, np cc vector ngt, cc ISP Monitor ng ngha giao din ngi dng qua thit b u cui (l PC) qua ng kt ni, thng l kt ni ni tip, vi ch dng lnh (Command Line Interface-CLI), qua ngi pht trin c th thc hin: Ti image code xung h ch; c/ghi vo b nh ca h thng ch; c/ghi cc thanh ghi ca CPU ca h thng ch; Lp v xa cc im dng khi chy g ri; Thc hin chy tng lnh; Reset h thng qua lnh. Monitor thng do k s phn cng vit ra dng cho c hai chc nng: chun on phn cng (diagnostics) v m g ri cp thp. phn mm monitor c th c dng m ngun, nn vic ty bin cho h c th l rt kh d. Kch bn boot h ch Phn ny gii thiu qu trnh khi ng h ch, t a mnh vo hot ng. Cc CPU ca HTN sau khi bt ngun, hay RESET (mm do nh thi, hay cng n cng tc) s tm v thc hin cc lnh u tin m a ch do CPU c thit k. m ti a ch ny cn gi l reset vector. Thng thng reset vector n gin l mt lnh nhy (JMP addr) ti mt a ch khc, m m khi ng chnh s c thc hin (xem v d PC chun pha sau). S d nh vy l v cc CPU c mt khng gian ia ch rt nh dnh rin cho cc mc ch c bit, do vy nu on m khi ng qu di s khng ch cho n. Hn na reset vector cung nh m boot khi ng phi nm v tr nh c nh (trn ROM h thng, hay FLASH trn bo mch, hay trn RAM khng b mt ni dung NVRAM). Khi m t loader y s qui chiu ti m thc thi 221

by boot h thng (system-bootstrap), ti phn mm h thng (boot image code) v cc bc khi ng. Tt c s c gii thiu thng qua v d, l d dng nht. Gi nh HTN c pht trin v lp trnh vi b nh FLASH trn bo mch ch. Phn mm ch (boot image) l tp cc phn on chng trnh khc nhau. Mi phn on c v tr xc nh trong b nh. Reset vector cha trong mt ROM nh c nh x vo a ch 0x0h. ROM cha mt s gi tr (hng) thng thng m CPU cn c khi reset. Cc gi tr l reset vector, con tr thanh ghi ngn xp (stack pionter), mt s a ch ca RAM V d c minh ha nh hnh sau:
V d tng quan v boostrap h thng
222

Reset vector nh v ti 0x0000h ca ROM, t c lnh JMP 0x00040h: nhy ti a ch 0x00040h FLASH. iu khin (hay startup initialization) bt u thc hin a ch ny. M y gm chng trnh ti boot image code, cc ngt ngoi l ca h thng (tr ti cc ISP ti FLASH) v cc chng trnh khc. Trn hnh l on code comes from FLASH. Phn u tin ca qu trnh bootstrap l a h vo trng thi u tin (known state): cc thanh ghi ca CPU c khi ng vi cc gi tr mc nh ph hp, stack pionter np gi tr xc nh (hng) trong ROM. Loader s cm ngt giao on ny v cha c cc ISP trong b nh; khi ng a ch ca RAM, a ch ca cache (nu c). Loader thc hin kim th cc thit b vi vi ch c bn. Phn mm chy RAM thng nhanh hn FLASH, do loader s copy mt phn m ti FLASH vo RAM. Ti y phn loader s c hai a ch: a ch np vo RAM v a ch chy ca chng trnh copy v RAM. y s dng debuger s gip gim st tnh hung outof-RAM khi copy v chy. M thc thi c phn d liu (DATA segment) c khi ng v phn cha c khi ng. Phn d liu ny cn copy vo RAM v do c / ghi c. Cc m lp trnh nh .data hay .sdata cha cc gi tr khi ng cho cc bin tng th v cc bin cc b. Phn m xc nh .bss v .sbss khng khi ng lc ny. Tip theo l khi ng cc thit b. Ch cc thit b m loader cn l c khi ng vo thi im ny. Cc thit b ny ch l mt phn ca I/O v s c khi ng tt c sau khi imagr code c ti hon taastvaf thc hin khu startup. n y loader cc iu kin ti cc phn mm h thng, RTOS, ng dng cc phn mm ny xut pht t hai ngun: 1. T h pht trin; 2. T thit b nh ch c no bn ngoi trn h pht trin. Cc kch bn chy phn mm h thng c th nh sau: 1. Ch y t ROM, c n RAM dnh cho d liu Mt s HTN c gii hn b nh, do h s khi ng trc tip t ROM. Trong trng hp ny s khng c qu trnh copy m lnh vo RAM chy. Tuy nhin khng gian cho d liu vn phi xc inh RAM (nh khi lp trnh). C 2 thanh ghi c bn l IP (Instruction register)-thanh ghi lnh, tr vo lnh tip theo s thc hin (.text) v SP (Stack Pointer), tr vo a ch tip theo trong ngn xp. ngn ng C s dng ngn xp truyn cc thng s khi kch hot mt hm. Vng ngn xp phi RAM v SP phi tr vo khi khi ng CPU. Qui trnh khi ng nh sau: 1) Thanh ghi IP c thit k cng thc hin lnh u tin trong b nh, l reset vector. 223

2) Reset vector nhy ti lnh u tin ca phn .text ca m boot (tc boot boot image), .text thng tr trong ROM; CPU dng IP thc hin .text, khi ng b nh, k c RAM. 3) Phn .data ca boot image c copy vo RAM c th c/ghi. 4) Xc lp .bss trong RAM. 5) Xc lp ngn xp .stack trong RAM, khi ng SP tr vo a ch u ca stack. 6) Hon tt khu khi ng, CPU tip tc thc hin cc lnh trong .text cho ti khi h thng hoc shutdown hay RESET. Lu y l cc lnh u bc 1) khng nh dng chun ELF m n gin l m my nh phn sn sng chy. Nhng boot image nh dng ELF (vit ra t cng c pht trin) nhng khng c program header v header table, do lu vit m thc thi sao cho c th khi to cc phn .datta, .bss, .stack trong RAM. ( v d nu dng hp ng th gn nhn, ).
Trnh t boot boot image chy t ROM Ch y R M sau hi m copy t ROM vo RAM kch bn ny, boot loader s chuyn mt chng trnh nh t ROM vo RAM v kch hot n chy. Thng m chng trnh h thng trong ROM rt ln m c ghi kiu nn np va ROM, nn boot loader phi gai nn trc khi khi ng phn m ny v n cn khng gian nh RAM thc hin. 1) --- n 6) ging nh trn. Mi trng lm vic cho loader c khi ng RAM (3, 4, 5). 224 2.

7) Loader copy phn m nn ca image vo RAM. 8) > 10) Copy cc phn m gii nn vo cc vng lm vic tm trong RAM (8, 9, 10) . Hon tt gii nn image. Image trong RAM hnh l on Final Boot image. 10) 11) Loader chuyn iu khin cho image bng mt lnh JMP vo .text (np cho IP a ch ny trc khi JMP ti ). 12) Vng RAM m loader chim khi c copy t ROM l ti s dng, SP c ti khi ng tr vo v c dng nh ngn xp cho mt chng trnh mi no . Vung RAM gii nn gii phng s dng khc. H thng i vo hot ng.
Trnh t boot thc hin RAM sau khi image c copy t ROM vo RAM 3. Ch y t R M sau hi ti xung t h pht trin (ang pht trin h thng) L kch bn trong qu trnh pht trin. Mi trng pht trin c mt PC h tr. S dng pht trin cc phn mm ng dng cho h thng nhng. Phaaffn mm pht trin nm trn PC v s ti xung h ch chy th hay np vo h ch pha cui cng. Trong RON c mt chng trnh gi l Debug Agent ng vai tr kp nh mt loader nh cc kch bn trn. 225

1) 6 ) ging nh trc 7) Ti ng dng t PC vo h ch. 8) Kim tra s hp nht ca phn mm ti xung. 9) Gii nn ng dng nu cn. 10) 12 ) chng trnh debug ti nh v ng dng vo v tr trong RAM (10, 11, 12). 13 ) Debug chuyn uu khirn cho image ti xung. H chy.
Chy image sau khi ti xung h ch t h pht trin (PC) Trnh t khi ng phn mm ca h ch Cho d h s chy theo kiu no th sau khi loader trao quyn iu khin cho code image, th phn mm ny s thc hin cc bc khi ng h thng. Cc bc khi nh h thng bao gm: - Khi ng phn cng, - Khi ng RTOS, - Kch hot ng dng nhng. 226
Khi ng phn cng Sau khi thc hin reset vector, cc thao tc c bn l cn phi khi ng cc phn cng ti thiu, bao gm: - Bt u thc hin reset vector (JMP ti a ch ca boot loader). - t CPU vo trng thi cc ng ban u, cc thanh ghi c khi ng vi cc gi tr thch hp, ly s hiu ca CPU, lp tn s CPUClock. - Cm cc ngt v cm cache nu h c cache. - Khi ng cc Chip iu khin b nh (MMU), iu khin cache (MCU). - Lp a ch u cho RAM (thng s c ROM), ly ton b kch thc ca RAM trn h, thc hin kim tra RAM (ghi/c, v d vi gi tr AAhex/55hex).
Tin trnh khi ng phn mm HTN Sau khi khi ng CPU v RAM, boot loader s copy v gii nn code imafe vo RAM, nh ni trn. 227

Hu ht phn m ca boot loader v cc bc khi ng vit bng hp ng v hng c th ti loi CPU s dng trn bo mch ch. Phn code cn li vit bng C/C++. Tip theo l m khi ng cc phn cng khc ca code image, bao gm: khi ng cc vi mch iu khn, np cc chu trnh thao tc, nh ISR, khi ng cc vector ngt (cng/mm), khi ng giao thc BUS. Khi ng cc thit b ngoi vi (cng truyn thng ni tip/song song, mng, ). Cc k s pht trin HTN coi bc 1) v 2) hnh trn l bc khi u, cn t 1) n 3) gi l cc bc c s BSP hay cn gi l khi ng phn cng. viest m cho BSP, cn nm chc phn cng ca h ch. C th dng BSP ca phn mm pht trin, nh gi bn km bo mch. Kt thc thnh cng BSP phn cng sn sng v ngi pht trin c cc hm chc nng kch hot phn mm h thng, nh RTOS chng hn. Khi ng RTOS Bc 4) n bc 6) hnh trn bt u cho khi ng phn mm h thng, RTOS. Bao gm: - Khi ng RTOS. - Khi ng cc dch v ca RTOS (cc i tng ca tc v, cc i tng c tranh chp-semaphore), cc hng i thng ip, cc dch v nh thi, cc dch v ngt ISR, cc dch v qun tr b nh. - To cc stack cho RTOS. - Khi ng mng (TCP/IP stack ). - Khi ng h thng tp FS (file system). - Kch hot RTOS vi cc tp khi ng h thng ca RTOS (/initd). Khi ng phn mm ng dng nhng Sau khi RTOS chy, phn tip l kch hot cc ng dng. Cch kch hot ph thuc vo ngi pht trin ng dng, thng l RTOS s gi mt chc nng xc nh trc trong chui cc lnh init hay cron vit theo shell h thng. G ri bng cng c bn m (On Chip Debugging OCD) Cc nh cung cp phn cng thng mi thng c OCD i cng, trong phn mm BDM (Background Debug mode) v JTAG (In the 1980s, the Joint Test Action Group (JTAG) developed a specification for JTAG testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement containing a description of the Boundary-Scan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world. Applications are 228

found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. In fact, due to its economic advantages, some smaller companies that cannot afford expensive in-circuit testers are using JTAG.) http://www.corelis.com/education/JTAG_Tutorial.htm Cc v d
V d Intel CPU 8085: RESET => IP=0x0000 l a ch ca EPROM: Khi ng ch ni vi Console (Keyboard), sau nhy v chng trnh khi ng h: JMP CLDST (Khi ng ngui) a ch 0x01F1
on CLDST:
Trong khi Intel CPU x86 trn PC hot ng nh sau: Sau khi thc hin bt ngun (khi ng ngui), hay n t hp phm CTRL+DEL (khi ng nng = RESET), hai thanh ghi phn on m (code segment CS) v con tr lnh (Instruction pointer IP), vit chung l CS:IP c np gi tr 0xFFFF:0000 (a ch vt l 0xFFFF0). Lnh u tin phi thc hin a ch ny, ti y thc hin mt lnh nhy ti on lnh khi ng gi l Kim tra h thng sau bt ngun (POST Power On System Test) ti nhn START. on m ny thc hin cc cng vic nh sau: cm ngt, khi ng cc c ca CPU, c/ghi th cc thanh ghi, kim tra li (CRC) ca EPROM, khi ng cc vi mch iu khin ca bo mch chnh v.v. Tip theo khi ng li v cho php cc ngt khng che hot ng, thc hin INT 19 chy chng trnh mi (bootstrap loader) np m khi ng h iu hnh (boot-record) t a cng xung b nh, sau nhy ti a ch ca boot-record. Chng trnh bootrecord tip tc np h iu hnh xung phn b nh h thng. Lc ny ch hot ng l ch thc (real mode) ca CPU. Sau khi HH np hon tt, ch thc chuyn sang ch o hay cn gi l ch c bo v (protected mode), do HH kim sot. Lc ny HH cho php ngi dng s dng my tnh. 229
(V d ca Intel 80286: A23 - A0: Cho cho 16 MB a ch vt l, 1 GB a ch o. Initialization and Processor Reset Processor initialization or start up is accomplished by driving the RESET input pin HIGH. RESET forces the M80C286 to terminate all execution and local bus activity. No instruction or bus activity will occur as long as RESET is active. After RESET becomes inactive and an internal processing interval elapses, the M80C286 begins execution in real address mode with the instruction at physical location FFFFF0(H). RESET also sets some registers to predefined values as shown in Table 6. HOLD must not be active during the time from the leading edge of RESET to 34 CLKs after the trailing edge of RESET.
M8086 REAL ADDRESS MODE The M80C286 executes a fully upward-compatible superset of the M8086 instruction set in real address mode. In real address mode the M80C286 is object code compatible with M8086 and M8088 software. The real address mode architecture (registers and addressing modes) is exactly as described in the M80C286 Base Architecture section of this Functional Description. Memory Size Physical memory is a contiguous array of up to 1,048,576 bytes (one megabyte) addressed by pins A0 through A19 and BHE. A20 through A23 should be ignored. Memory Addressing In real address mode physical memory is a contiguous array of up to 1,048,576 bytes (one megabyte) addressed by pins A0 through A19 and BHE. Address bits A20A23 may not always be zero in real mode. A20A23 should not be used by the system while the M80C286 is operating in Real Mode. The selector portion of a pointer is interpreted as the upper 16 bits of a 20-bit segment address. The lower four bits of the 20-bit segment address are always zero. Segment addresses, therefore, begin on multiples of 16 bytes. See Figure 7 for a graphic representation of address information. 230

All segments in real address mode are 64K bytes in size and may be read, written, or executed. An exception or interrupt can occur if data operands or instructions attempt to wrap around the end of a segment (e.g. a word with its low order byte at offset FFFF(H) and its high order byte at offset 0000(H). If, in real address mode, the information contained in a segment does not use the full 64K bytes, the unused end of the segment may be overlayed by another segment to reduce physical memory requirements. Cc segment: 1st: 2nd 3th 4th . . . 16th 00000-0FFFF => 0000:0000-0000:0FFF 10000-1FFFF => 1000:0000-1000:1FFF 20000-2FFFF => 2000:0000-2000:2FFF 30000-3FFFF
F0000-FFFF =>F000:0000-F000:FFFF
Hin tng chng cho trong m hnh ny: V d: Cho a ch 1256A, tm cc a ch trng vi n cc segment sau y: 1256 v 1240: i ch vt l = (segment * 16) + offset T : Segnent * 16 = a ch vt l offset 1256A=12560 + X, v 1256A=1240 + Y Vy: X=1256A-12560=A, v Y=1256A-1240=16A Cho nn ta c: 1256A=1256:000A = 1240:016A !!! Mt a ch vt l tn ti 2 segnent !!! Khi c a ch vt l v c offset, c th tnh ra s ca segment. V d: cho a ch vt l l 80FD2, vi offset=BFD2. Tm segment ? Segment*16=80FD2-BFD2=75000=> ch ti:7500:BFD2
231
Reserved Memory Locations The M80C286 reserves two fixed areas of memory in real address mode (see Figure 8); system initialization initialization area and interrupt table area. Locations from addresses FFFF0(H) through FFFFF(H) are reserved for system initialization. Initial execution begins at location FFFF0(H). Locations 00000(H) through 003FF(H) are reserved for interrupt vectors.
232
Real address Mode Initially Reserved Locations Sau RESET CS:IP=F000:FFF0 Do a ch tht s l (CS*16) + IP = F0000 + FFF0 = FFFF0
on m hp ng sau m t qui trnh trn: ************************************* *IBM PC AT System ROM BIOS Resident * ************************************* CODE SEGMENT AT 0F000H DB 57344 ; fill lonest DB . . . 233
56K
Award ..IBM COMPATIBLE 486 BIOS COPYRIGHT Award Software Inc

. STGTST PROC NEAR MOV CX,4000H . . . STGTST ENDP
F000:E010 F000:E010
;SETUP CNT TO TESTT 16K BLK
*************************************************** * NOW CPU TEST: FLAGS, REGS, CONDITIONALJMPS* *************************************************** ASSUME CS:CODE,DS: NOTHING ,ES: NOTHING ,SS: NOTHING ORG 0E05BH ; System start: F000:E05B RESET LABEL FAR F000:E05B START: F000:E05B FA CLI ;DISABLE INTERRUPTS F000:E05C B4D5 MOV AH, 0D5H ;SET flags SF, CF, ZF,F on .. .. (Tip tc m khi ng) CODE ENDS ; Bt ngun khi ng bt u y: ;---------------------------------------; POWER ON RESET VECTOR ;---------------------------------------VECTOR SEGMENT AT 0FFFFH FFFF:0000 EA5BE000F0 JMP RESET ; Nhy ti nhn RESET FFFF:0005 30342F32392F3035 DB VECTOR ENDS C th quan st cc a ch bng lnh debug: 04/29/05 ;RELEASE MARKER
234
Thng thng start code thc hin mt s thao tc nh kim tra CRC ca ROM, test RAM, ti nh v m ROM vo FLASH hay RAM (shadown mode) thc thi lnh nhanh hn, thc hin khi ng cc thanh ghi, khi ng cc vi mch iu khin tch hp trn bo vi cc gi tr lp trnh cho vi mch ROM . Sau thc hin np h iu hnh (trn a cng) hay chuyn iu khin ti h iu hnh FLASH. H thng i vo hot ng. V d star code: main() { //Check hardware (ROM, RAM); //Khi ng cc device drivers: cc Chip on board; //Khi ng cc bin mi trng; . //khi ng cc CSDL h thng; .. //Relocate RAM address, define memory map, load OS. ; //JMP to 1st instruction of OS JMP . //system run 235

}
4.2.5 V d pht trin HTN Mc ny a ra mt s u bi thc hnh pht trin HTN, s c ti liu ring cho mi bi tp. Cc HTN bao gm: 1) Thit k bo mch vi cc la chn: CPU Intel 8085/8086, ROM, RAM Cc vi mch ngoi vi : 74257, 74 244, 74245, 7474, 8253, 8255, 8237, UART 8250/16450/16550 2) http://www.beyondlogic.org/serial/serial2.htm 3) Pht trin HTN vi micro controller Intel 8051 vi phn mm KEIL Soft. 4) HTN vi PIC: http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2123&p aram=en022497 Hin nay trn th trng c bn bo mch vi PIC 16F877 vi phn mm H pht trin vi gi 900.000,00 VN, ph hp cho thc hnh vit chng trnh ng dng. Sau khi thnh tho, c th thit k phn cng vi cc vi mch ri v pht trin ng dng c th t n gin n phc tp. 5) HTN vi Linux, bo Tri-M MZ104 (H PC 104): http://www.tri-m.com/products/engineering/mz104.html 6) Mt s h iu hnh trn HTN: QNX 4 RTOS, Windows CE and embedded Linux. Palm OS Windows CE MS-DOS or DOS Clones Linux, including RTLinux and MontaVista Linux and Unison OS QNX . 4.3 KT CHNG Chng 4 nu ra cc bc khi thit k mt HTN ni chung, v s lin kt vi th trng ng dng, v cc qui tc v nn tr thc cn c. Thit k HTN l mt bi tp rt tng hp vi bt k ai khi ni n thit k my tnh, bi khi lng kin thc rt rng, t k thut in t, khoa hc my tnh, cng ngh bn dn, ng dng my tnh trong cng nghip, trong gia nh Thit k 236

HTN khng ch l thit k phn cng m cn sng to cc gii php phn mm ph hp gii quyt cho loi ng dng nhng. Do vy rt quan trng l cn phn hoch chi tit v phi hp kho lo khi thit k. Sau khi phn mm pht trin v chy ng nh thit k, cng on tip theo l np phn mm vo bo mch. Qui trnh ny i hi phi hiu bit cch mt CPU khi ng v chin lc qui hoch s dng b nh ca HTN thit k. Cc cng c thit k v pht trin phn mm l khng th thiu c, trong bao gm h pht trin, cng c m phng (IDE, ICE), phn mm h tr cho bo mch (board support package - BSP). Thng thng cc cng c ny c phn tng qut chung, nhng c phn c th cho CPU ng dng c th v do nh phn phi sn phm bn km. thc hnh, c th chn bt k loi HTN no t bo mch controller trn th trng hay bt u t A n Z vi CPU ri, vi PIC hay PSoC. 4.4 CU HI CUI CHNG 1) Pht tho v gii trnh cc pha thit k khi thit k HTN, pha no c cho l kh v quan trng nht, v sao ? 2) Nu cc bc c bn khi thit k kin trc mt HTN ? 3) M hnh 4+1 l g ? Ti sao m hnh ny laj c ch cho thit k HTN ? Cc cu trc no c trong m hnh 4+1 ? 4) Nu k thut np phn mm vo bo mch HTN ang thit k ? 5) tng v th cho qua v th gy s c khi pht trin v th nghim HTN l th no ? 6) Boot code l g ? v lm chc nng g ? 7) Khi HTN thit k a vo dy chuyn sn xut, cng vic ca i thit k v pht trin xong ?
237

TI LIU THAM KHO Arnold S. Berger: Embedded Systems Design: An Introduction to Processes, Tools, and Techniques, ISBN: 1578200733 PETER MARWEDEL : Embedded System Design Stephen Edwards, Luciano Lavagno, Edward A. Lee, and Alberto SangiovanniVincentelli: Design of Embedded Systems: Formal Models, Validation, and Synthesis Steave Heath: Embedded Systems Design Tammy Noergaard: Embedded System Architecture A Comprehenvive Guide for Engneers and Programmers, 2005 G. R. Wilson: Embedded Systems and Computer Architecture Jean J. Labrosse: Embedded_Systems_Building_Blocks (Soft blocks in C) Miles J. Murdocca: PRINCIPLES OF COMPUTER ARCHITECTURE Qing Li with Caroline Yao: Real-Time Concepts for Embedded Systems PHILIP KOOPMAN, HOWIE CHOSET, RAJEEV GANDHI, BRUCE KROGH, DIANA MARCULESCU, PRIYA NARASIMHAN, JOANN M. PAUL, RAGUNATHAN RAJKUMAR, DANIEL SIEWIOREK, ASIM SMAILAGIC, PETER STEENKISTE, DONALD E. THOMAS, and CHENXI WANG Carnegie Mellon University: Undergraduate Embedded SystemEducation at Carnegie Mellon Wayne H. Wolf: Hardware-Software Co-Design of Embedded Systems Rajesh K. Gupta Information and Computer Science University of California, Irvine: Introduction to Embedded Systems Lu Hng Vit: H thng iu khin nhng (Embedded Control Systems) Hunh Thc Cc: Bn trong H iu hnh Unix/Linux, HDL Thng Long Trn Quang Vinh: Nguyn l phn cng v K thut ghp ni my vi tnh Hunh Thc Cc: Hp ng cho my vi tnh, Phng K thut s, Vin Tin hc, VKHVN, 1983 Hunh Thc Cc , Nguyn vn Tam: Ghp ni thng minh a cng 29 MB vo my vi tnh VT 83, Phng K thut s, Vin Tin hc, VKHVN, 1983 Nguyn Trung ng: K thut vi x l IBM Coporation: The IBM Personal Computer Technical Reference manual, 1983 Falk Salewski, Stefan Kowalewski, Embedded Software Laboratory RWTH Aachen University, Germany: Hardware Platform Design Decisions in Embedded ng Thnh Phu, VCNTT: NGN NG ASSEMBLY V CCH LP TRNH
[ 1] [2] [3] [4] [5] [6] [7] [8] [10] [11]
[12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22]
238
PH LC
p n bi tp thit k: Chng 2: Bi 1: 5. 6. 7. 8. EPROM - 4 KB (Address lines required is 12 A0 to A11 ) RAM-I - 8 KB (Address lines required is 13 A0 to A12 ) RAM-II - 8 KB (Address lines required is 13 A0 to A12 ) nh x a ch vo cc Chip nh nh sau:
Hnh 2.77 Bi tp thit k ROM Bi 2: Bi gii: 239

Tm hiu nguyn tc hot ng ca cng my in ca PC, cch s dng cng my in dc d liu vo PC: dng cc chn c thng tin giao tip c d liu vo, mi ln 4 bit. Nguyn l lm vic ca ADC 0809, cch ghp ni. T ln thit k nguyn l.
74125 . . . . . E- Switch In0 MUX (74157) ADC (0809)
LPT Port ACK
BUSY PE
In7
START SELECT EOC START
7404
Q(o)
Q0
CLK CLR . . . . . D Q(o) Q7 CLK CLR LS74 Status EOC
4 bit
DECORDER (LS 154)
. . . . .
Hnh 2.79 Bi tp thit k ghp ni AD vi BUS h thng my tnh PC Pht tho lu phn mm diu khin gp ni: 2. Chn knh o 3. khi ng chu k o ca ADC 4. c trng thi sau mi bin i (STATUS do EOC pht ra) 5. c v lu d liu.
Bi 3:
240

Vcc 16 Vcc GND Vcc 26 20 [DataBUS A2] SD7 [DataBUS A3] SD6 [DataBUS A4] SD5 [DataBUS A3] SD4 2 3 4 5 10 18 17 16 D7 D6 D5 D4 D3 D2 D1 D0 27 28 29 30 31 32 33 34 4 PA0 3 PA1 2 PA2 3 1 PA3 40 PA4 39 PA5 38 PA6 37 PA7 18 PB0 D 6 B 1 C 2 A 7 13 a 12 b 11 c 7 6 4 2 1 9 10 4 5 Vcc Vcc Vcc GND GND 7 A 7 B 1 C 2 D 6 GND 8 13 a 12 b 11 c 7 6 4 2 1 9 10 3 8 Vcc
74 LS 47
10 d 9 e 15 f 14 9
seg.
DSP
15 14 13 12 11 19 /CS 1 DIR
[DataBUS A6] SD3 6 [DataBUS A7] SD2 7 [DataBUS A8] SD1 8 [DataBUS A9] SD0 9
74 LS 245 U1 DATA BUS
74 LS 47
10 d 9 e 15 f 14 9
seg.
DSP
PIO 8255 A
19 PB1 20 PB2 21 PB3 3 4 5
Vcc 14 dien tro R= 470 OHM, 7 SEGMENT chung ANODE
Vcc 20 [BUS B2] RESET [BUS A23] A8 [BUS A22] A9 [BUS B14] /IOR/ [BUS B13] /IOW/ MR/] [MW/] [BUS A11] AEN GND Vcc 2 3 4 5 6 7 8 9 G 19 1 DIR
GND 10 18 RESET 17 A8 RESET 35 /RD /WR 5 36
22 PB4 23 PB5 24 PB6 25 PB7 14 PC0 15 PC1 16 PC2 17 PC3
16 A9 15 IOR/ 14 IOW/ 13 MR/ 12 MW/ 11 AEN 13 12 1 2 3 4 5 6 11 12
A1 8 A0 9 /CS 6
74 LS 245 U2 CONTROL BUS
10 11 12 PC10 PC6 PC5
13 PC4
Vcc 20 [BUS A24]A7 [BUS A25]A6 [BUS A26]A5 [BUS A27]A4 [BUS A28]A3 [BUS A29]A2 [BUS A30] A1 [BUS A31]A0 G GND Vcc 2 3 4 5 6 7 8 9 19 1
GND 10 18 A7 17 A6 16 A5 5 9 11 1 3 4 6 10 8 2
15 A4 14 A3 13 A2 12 A1 11 A0
74 LS 245 U3 ADDRESS BUS

DIR
PC ISA BUS B: mat han mach in A: mat linh kien
Bi gii : -M t nguyn l lm vic 241

-Chng trnh iu khin ghp ni: /* ** 8255.c ** ** Minh hoa PIO 8255 voi mode 0 (tat ca out_ports on 8255 Ports): ** A, B and C. ** ** 8255 is first setup with control word 0x80 ** Mode set flag active - bit 7 = 1 ** Mode selection 0 - bits 6 5 = 0 0 ** Port A output - bit 4 = 0 ** Port C (upper) output - bit 3 = 0 ** Mode selection 0 - bit 2 = 0 ** Port B output - bit 1 = 0 ** Port C (lower) output - bit 0 = 0 ** ** D liu ra s dng gi hm out_data (port, data) trong : ** Port A - 0 ** Port B - 1 ** Port C - 2 ** */ #include <stdio.h> #include <dos.h> /* nh ngha cc bin*/ #define DATA 0x0300 /* Cho ghp ni lp bin DATA=base addr*/ #define STATUS DATA+1 #define CONTROL DATA+3 /*CONTROL=DATA+3*/ void reset(void); void write_clock(int a1a0); void set_control_word(void); void out_data(int port, int data);
void main(void) { int port; 242

int data; /*bat dau chuong trinh*/ reset(); set_control_word(); /* Bay gio da co the cho 8255 chay */ /* Thu dua ra cac so Hex tren 3 cong A,B,C */ printf("An <ENTER> DE KIEM TRA CAC GIA TRI TU a den f \n"); /* for(port=0;port<3;port++)*/ /*{*/ getchar(); port=0; /*Tam thoi voi port A*/ printf("Dua ra aa\n"); out_data(port, 0xaa); getchar(); printf("Dua ra bb\n"); out_data(port, 0xbb); getchar(); printf("Dua ra cc\n"); out_data(port, 0xcc); getchar(); printf("Dua ra dd\n"); out_data(port, 0xdd); getchar(); printf("Dua ra ee\n"); out_data(port, 0xee); getchar(); printf("Dua ra ff\n"); out_data(port, 0xff); /* }*/ /*Nhan bat ki so nao tu 00-99*/ printf("\n Go vao bat ki so nao tu 00 den 99 va ENTER \n"); while(1) { scanf("%x",&data); /*nhan luon so kieu hexa de dua ra cong*/ for (port=0;port<3 ;port++ ) { out_data(port, data); } }/*while*/ 243

} /*Cac ham ho tro*/ void set_control_word(void) { /*int a1a0 = 0x03;*/ outportb(CONTROL, 0x80); /* out control word = 0x80 */ /* bring a1 a0 to 1 1, WR to 1 */ /*outportb(CONTROL, */ /* ( ((0x00) | (a1a0 << 1) | 0x01) ^ 0x0b) & 0x0f); */ /* now wink WR low and high */ /*write_clock(a1a0); */ } void out_data(int port, int data) { /*int a1a0 = port;*/ outportb(DATA, data); /* put data on data leads */ /* set a1 and a0 to 0 0, 0 1 or 1 0, WR to 1 */ /*outportb(CONTROL,( ((0x00) | (a1a0 << 1) | 0x01) ^ 0x0b) & 0x0f);*/ /* now wink WR low and high */ /* write_clock(a1a0); */ } void write_clock(int a1a0) { /* bring WR low */ outportb(CONTROL, (((0x00) | (a1a0<<1) & (~0x01) ) ^ 0x0b) & 0x0f); /* bring WR back high */ outportb(CONTROL, (( (0x00) | (a1a0<<1) | (0x01)) ^ 0x0b) & 0x0f); } void reset(void) 244

{ /* bring reset high */ outportb(CONTROL, 0x08^0x0b); } ;
Making an LM35 temperature recorder with PIC 12F675.

http://www.best-microcontroller-projects.com/12F675-tutorial-mikroc-1-7-source.html
This page shows you how you can make an LM35 an temperature recorder by using the 12F675 PIC microcontroller as the controller and data store. It generates serial output so that you can view the results on a PC and it also calculates the temperature reading in Fahrenheit sending both to the serial port at half second intervals. The project uses the code from the previous tutorials to report the temperature to the PC using the serial port so the serial RS232 data format is generated in software. Jump Jump Jump Jump to to to to circuit. Solderless breadboard. Circuit Diagram. Software.
LM35DZ
The LM35 is a precision temperature sensor. It is guaranteed accurate to C at 25C (At different temperatures it is less accurate! but it is never more than 2C inaccurate and it probably is not this inaccurate anyway it's just the manufacturers maximum limits that may apply). Typically is stays accurate to within C over its temperature range so this is a good general purpose sensor and it's easy to use. It generates a linear output voltage using a centigrade scale - generating 10mV of output voltage for every degree centigrade change and there are several versions for operation over different temperature ranges: LM35 LM35C LM35D
-55C to 150C -40C to 110C 0C to 100C
Note: The project code calculates the temperature in Fahrenheit and generates both Centigrade and Fahrenheit outputs to the serial port.
245

Temperature recorder : LM35 pinout
Temperature recorder : pinout for the LM35DZ (from the top).
Temperature recorder Circuit

The LM35 is connected to analogue input AN0 which is also the data input line for programming the 12F675 using ICSP so you need a way of connecting the sensor and the programming input at the same time with the programming input overriding the sensor output (and not damaging the sensor!). This is done here by using 1k resistor that reduces the current flowing back into the sensor and at the same time is not too large (so that the ADC can easily convert the sensor output value - the impedance must be equal to or smaller than 10k Ohm from the sensor). The voltage reference for the circuit is taken from pin 6 using a resistor divider giving a 2.5V reference. This is simply done to increase the resolution of the ADC as for the LM35 only 01V is generated so you loose ADC range when using a 5V reference. You could use a lower reference value but this value gives reasonable results. Alternatively you could use an amplifier to scale the LM35 output up which would make the ADC less sensitive to noise but for this project it is simpler not to do so. Note: The large decoupling capacitor on the supply input of the 12F675. This reduces noise overall and gives a more consistent reading. However using a plug block and ADC is not a very good idea as there is no ground plane and no control over current paths which you would be able control in a pcb. In a commercial system the internal ADC is often not used at all as it is essential to separate the noise introduced to the ADC using separate grounds and shielding - some designs encase the ADC in a custom metal shield and along with a ground plane connecting to the shield gives the best possible result. To overcome noise problems on the ADC the software averages the input readings so you get a better result.
Solderless breadboard
Add the components (at top right to) the temperature recorder - wires and R3,R4,R5 and the LM35 temperature sensor (U4) and the decoupling capacitor C4.
246
Learn about the tool used for creating this diagram.
LM35 Temperature Recorder Circuit diagram
247
248

Learn about the tool used for creating this diagram.
Temperature recorder measurement accuracy

The analogue reference for the ADC is taken from the power supply via a resistive divider to the 12F675 input pin 6 and for the 7805 its accuracy is specified as 5% so the accuracy of the ADC is only 5% due to the reference -the divider also introduces a 1% error giving a 6% error overall. Note: Since the 7805 is only accurate to 5% the accuracy of the temperature reading will be accurate to 5% (plus errors in the ADC and temperature sensor itself and any noise introduced the the analogue input and the reference). However the reference source gives you the biggest error - the overriding accuracy - if you used a more accurate voltage supply then the ADC accuracy would become more important as well as the temperature sensor accuracy etc.
Temperature recorder Software

Buy all the 12F675 Tutorial source code ...with the MikroC project files and compiled hex files Click here for more information. The software uses the Soft USART (transmit only) described in the previous tutorial and uses the built in MikroC routines to get the data from analogue input pin AN0. // Temperature recorder analogue input val = ADC_Read(0); // more code adds up 10 readings of ADC val = ((val/MAX_AVG)*122)/50; val = ((val*18)/10)+320;
Software operation
The most interesting parts of the software are shown above. The variable val is an unsigned int so the maximum value it can store is 65535 The reference in use is 2.5V so for the 10bit ADC each ADC bit is worth 2.5/1023 = 2.44mV If you work out values generated for a maximum temperature of 100C using the scale
249

factor 2.44mV (or 244/100) 100 * 10mV = 1.0V 1.0V/2.44mV = 410 410 * 244 = 100,040 which will not fit into an unsigned int. So this scale factor does not work for all input values By using a little maths it can be made to fit -you need to reduce the top number to fit. e.g. 410 * 122 = 50,020 which does fit. Dividing by 50 gets back to the correct scale factor of 244. So the scale 122/50 works for all input values. This is an example of avoiding the use of floating point variables which take up too much resources. You can still make the system work but you have to be careful when using fixed types and you have to check all input values and outputs to make sure they fit.
Averaging
Averaging would be better done in the PC as it has more resources - the same goes for calculating and displaying the temperature in Fahrenheit but this gives a demonstration of what you can do. Note: The RAM is used up since a bug in MikroC 5.0.0.3 puts strings int RAM - in future versions this will be corrected.
Typical output from the temperature recorder

96 RAW 234 C 741 F
The left most value is the RAW ADC value, the next is the temperature sensor output in degrees centigrade and the next is the temperature sensor output in degrees Fahrenheit. Note: You have to put in the decimal point so the above readings are: 234 C 741 F 23.4C 74.1F
250

c thm: E380: Design of Embedded Systems Exercises Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology The questions and exercise included in this material represent typical questions which can be asked to the contents of the lectures given through the course Design of Embedded Systems (E380). The structure of chapters follows directly the structure of the lectures. Most of the questions are typical for the course and can be asked during the examinations, however, it is not the intention to supply the examination questions. The purpose is to give the guidance for students for preparation to examinations.
Introduction 1. Give a short definition of embedded systems and discuss main features of such systems. Illustrate your discussion with examples of embedded systems. 2. Discuss differences and similarities between embedded systems and general purpose workstations, desktop computers and portable computers. 3. What are basic characteristics of embedded systems? Discuss both inherent features of such systems as well as specific design process challenges. 4. Discuss and give a motivation why implementation of embedded systems using a single processor running a software implementation is not usually possible. What are advantages and disadvantages of such a solution? 5. Explain the term ``design space exploration''. What does it mean for embedded system design? What are typical design parameters which are included in a design space. 6. Design process is often controlled by the time-to-market requirement. Explain this requirement and possible consequences on the design methodology. Design Methodology 1. Input to a system design is usually defined as system specifications and a set of functional and non-functional requirements. Discuss system specification methods as well as different types of requirements. 2. What are basic features of good requirements? Discuss them briefly. 251

3. Discuss how design requirements can be created. 4. What is design flow? Give an example of design flow paradigm used for embedded system design. 5. Discuss different design flow approaches. Compare them and point out similarities and differences between them. 6. Explain the ideas behind the following design flow models: o waterfall model, o spiral model, o stepwise refinement model, o top-down model, o bottom-up model. 7. Hardware/Software co-design methodology becomes popular for embedded systems. Discuss basic ideas behind this methodology and compare it to a traditional design methodologies. 8. What are basic design steps in hardware/software co-design? Why this methodology can improve design process and design quality? 9. Discuss a typical design methodology for embedded systems. Where different design activities, such as design specification, design partitioning, component allocation, and communication synthesis are performed? 10. What are main design activities in communication synthesis? 11. What are IP-components. Discuss briefly hard and soft IP-components and their role in a design process. 12. Discuss different design verification methods and their advantages and disadvantages. 13. Design automation tools are used in many design methodologies to help designer in solving tedious design activities. Discuss theoretical limitations of design automation tools. 14. Many design automation problems belong to the class of NP-complete or NP-hard problems. Discuss briefly how this inherent complexity problem is solved in design automation tools. What kind of algorithm are used? Specification Languages 1. Discuss briefly what languages can be used for specification and implementation of embedded systems. What are their related advantages and disadvantages. 2. VHDL is a hardware description language which is often used to specify, simulate and synthesis hardware for embedded systems. Discuss basic VHDL constructs. 252

3. Hardware is inherently parallel and this need to be modeled in specification and design languages. How VHDL supports parallelism for hardware specification. 4. VHDL simulator is implemented as an event-driven simulator. Describe briefly the main idea of event-driven simulation. How time is handled in this simulation paradigm. 5. Discuss how different modeling styles, such as structural, behavioral, and data-flow can be mixed in a single VHDL model. 6. Present briefly VHDL simulation mechanism. Point out when VHDL code is executed and when time and signals are updated? 7. What is a signal driver in VHDL simulator. How is it used during simulation? How signals are updated by the simulator? 8. What is delta delay in VHDL? How is it used during simulation? 9. Give the values assigned to signals and variables by the part of the process code included below. 10. P1: process 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. variable a, b : integer; begin : -- initial values of s1 = 0, s2 = 0, a = 0, b = 0 s1 <= 10; a := s1; b := 3; s2 <= b + s1; -- give values of s1, s2, a, b here (1) wait for 10 ns; -- give values of s1, s2, a, b here (2) : end process;
24. VHDL is used both for hardware simulation and synthesis. Discuss briefly the language features which create problems for synthesis. What are possible solutions to this problem. 25. Discuss briefly commonly accepted restrictions for VHDL used for high-level synthesis.
253

Data-flow computational models 1. Discuss basic characteristics of data-flow and control-flow models. What are main application areas for both models of computation. 2. A filter is represented by a data-flow graph depicted in Figure 1. Additions have their usual meaning and multiplications are always by a constant. Using this data-flow graph determine filter equations, i.e., a function which defines y(n).
Figure 1: An example of data-flow graph
3. The theory of data-flow models is based on Khan process networks. In this theory it is proved that a network process is monotonous if X X' F(X) F(X'). What does this property means in practice? Which computations can be implemented using data-flow models? 4. Describe informally what are execution rules for data-flow network built of actors. Explain a notion of actors, tokens and firing rules. 5. What is a sufficient condition for a data-flow network to be deterministic. 6. Discuss briefly subclasses of data-flow networks called synchronous data-flow and boolean data-flow. Give examples of actors for these networks and their firing rules. 7. What is a firing rule for a data-flow network? Give examples of firing rule. 8. What does it mean that a set of firing rules for an actor of data-flow network is sequential? Give an algorithm for checking this property.
254

Control-flow computational models 1. Explain the main idea of StateCharts. How they handle concurrency and hierarchy? 2. Explain the main idea of AND and OR states in StateChart model. Why a notion of AND and OR states is defined? 3. Describe a general idea of Petri nets? How they can be used to model parallel activities. 4. Draw simple Petri nets which model sequential execution, parallel execution and nondeterministic choice. 5. How firing of a transition in a Petri net is defined? What does it mean that a transition is enabled and it may fire? 6. Define the following properties of Petri nets: o reachability, o liveness, o boundness, o safeness, o conservation. Try to relate this formal properties to practical properties of embedded system, i.e., system properties which can be analyzed using Petri nets notions. 7. Explain the reachability tree for Petri nets. What kind of problems can be analyzed using this technique? What is a reason for limitation of this method? 8. Describe Petri nets analysis method based on matrix equations. What are limitations of this method? Why the method has these limitations? Partitioning 1. What is embedded system partitioning? What is decided during partitioning? 2. What is difference between structural and functional partitioning? Which one is more suitable for system partitioning? 3. What does it mean partitioning granularity? Give examples of possible granularity. 4. How are defined objective or closeness functions for partitioning? Give examples. 255

5. How design constraints, such as number of pins in a package or maximal permitted are, are handled during partitioning? Give two alternatives. 6. Describe an algorithm for hierarchical partitioning. 7. What is a basic method for transformation based (iterative) partitioning? What is a main problem with this approach? 8. Describe briefly Kernighan-Lin algorithm for bi-partitioning. 9. What is a basic approach to neighborhood search based partitioning. Give an example. 10. Describe briefly simulated annealing partitioning approach. 11. What is hardware/software partitioning? What is a goal of this partitioning? 12. Assume that the weighted graph depicted in Figure 2 represents tasks and their intercommunications. The weight of a node represents a size of the task while the weight of an edge represents the communication ``cost''. Using hierarchical clustering and appropriate closeness function find a partitioning which minimizes communication cost.
Figure 2: An example system represented as a graph.
256

Scheduling 1. Discuss static and dynamic scheduling approaches. Point out their application areas as well as advantages and disadvantages. 2. Explain difference between time-constrained and resource-constrained scheduling methods. 3. Explain the following scheduling approaches ASAP, ALAP and list scheduling. What is an advantage of list scheduling? 4. Explain forced-directed scheduling. 5. Explain a role of chaining and pipelining during scheduling. 6. What does it mean resource sharing and conditional resource sharing during scheduling? 7. What is speculative execution during scheduling? 8. How static scheduling influences register allocation? 9. How static scheduling influences power consumption? 10. Make static scheduling of a filter depicted in Figure 1. Assume that a delay defines new input/output pair. 11. Discuss briefly different real-time scheduling policies. Divide them into off-line and online. Furthermore, discuss different priority assignment strategies. 12. Explain Rate Monotonic Scheduling (RMS). What is a limitation of this method. 13. What is priority inversion problem for Rate Monotonic Scheduling (RMS)? What are methods for solving this problem? 14. Describe briefly priority ceiling protocol for solving priority inversion problem. 15. Describe briefly Earliest Deadline First (EDF) dynamic priority scheduling. 16. Use the RMS schedulability analysis to check if each of the following task sets is schedulable with RMS. If not, identify which tasks will miss their deadlines.
257

Task set 1 Task Period Worst execution time 1 2 3 5 3 8 Task set 2 Task Period Worst execution time 1 2 2 3 Task set 3 Task Period Worst execution time 1 2 3 5 7 9 1 2 4 Table 1: Three task sets 1 1 1 2 4
Interface Synthesis 1. Describe briefly basic steps in communication synthesis. 2. What are main objectives of channel binding, communication refinement, interface generation? 3. Describe briefly strobe and handshake protocols for processor communication with other devices. 4. Why interrupts are used for processor communication with external devices? 5. What is a role of an interrupt service routine? 6. Describe briefly functionality of a typical interrupt service routine. 7. What is DMA controller and what is its role in communication between different devices? 8. Describe briefly functionality of a DMA controller. 258

9. Why there is a need for bus arbitration? What are bus arbitration methods? 10. Present briefly daisy-chain arbitration method for a bus. 11. The handshaking protocol discussed on the course is represented in Figure 3. Formalize this specifications using, for example, Petri nets and prove that the master after sending a request will get data. Extend the example with two slaves and ensure that the protocol is fair, i.e., non of two slaves will wait for the possibility to send data forever. How can you include timing analysis in the model?
Figure 3: An example handshaking protocol.
Low Power Design 259

1. What are main sources of power consumption in CMOS technology? How power consumption can be minimized? 2. What is a relation between power consumption and energy consumption? Explain importance of power and energy consumption for embedded systems? 3. What are basic ways of reducing power consumption? Testability 1. Explain the concept of production faults and their models. 2. Explain stuck-at fault model. 3. Describe briefly test generation method based on fault sensitization and fault propagation. 4. What are reconvergent fan-out points? Why do they create problems for test generation? 5. Discuss basic testability improvement methods. 6. What is the main goal of all testability improvement methods? 7. Discuss briefly main idea of SCAN path testability improvement method. 8. Discuss briefly main idea of BIST testability improvement method. 9. Explain briefly testability improvement by circuit partitioning and enhancement with specific testability improvement methods.
V d khc: (Trng i hc Bch khoa H Ni B mn iu khin t ng H THNG IU KHIN NHNG (Embedded Control Systems) TS. Lu Hng Vit) M hnh thc thi b iu khin nhng
260
Hnh 6 9: H thng iu khin s thc thi mt b iu khin s trn thit b vt l thc phi i hi xt xem b iu khin vi m hnh hm truyn cho c th hin thc ha c khng. iu kin phi xt thc ra l m bo rng khng c u ra no ca h thng li xut hin trc khi c tn hiu vo. Hay ni cch khc h thng xy dng phi tun th tnh nhn qu. Nu khai trin hm truyn ca b iu khin s c m t dng tng qut
thnh chui ly tha theo z th n phi khng c php cha bt k phn t no cha ly tha dng ca z. Hay ni cch khc l b iu khin c m t nh (1.5) phi c bc 0 tc l bc ca t s phi nh hn hoc bng bc ca mu s Sau khi thit k c b iu khin s th vic cn li l lp trnh v np vo cc b iu khin vt l kh trnh. Thc cht qu trnh ny l thc thi hm truyn ca b iu khin s bng lp trnh s trn cc b iu khin vt l c. y chng ta s ch yu quan tm n vic trin khai chun b cho bc lp trnh cc hm truyn ca b iu khin s. Xut pht t m t hm truyn dng tng qut ca b iu khin s
trong , l cc s nguyn dng. C th trin khai thc thi mt hm truyn ca b iu khin s theo 3 cch nh sau: 261

Trin khai lp trnh s trc tip trin khai lp theo phng php lp trnh trc tip th hm truyn b iu khin cho biu din trong min z phi c chuyn i v dng hm truyn ri rc
T ng thc (1.7) d dng tnh ra c gi tr ca u ra *( ) u t ca b iu khin s cho theo cc gi tr hin ti v qu kh ca u vo *( ) e t cng nh cc gi tr qu kh ca chnh n
thc hin b iu khin ny yu cu phi lu tr cc gi tr qu kh ca u vo v u ra ca b iu khin. Vi b iu khin cho yu cu phi c n m + gi tr cn phi lu tr hay ni cch khc cn phi c n m + phn t lu tr. Mt phng php khc trin khai lp trnh trc tip l s dng c ch tch trc tip u vo v u ra ca b iu khin theo mt bin trung gian X(z). Khng mt tnh tng qut nu chng ta nhn c t v mu ca hm truyn b iu khin s cho vi mt bin X(z). T rt ra c hm truyn ca u vo E(z) theo X(z) v hm truyn ca u ra U(z) theo X(z). Phng php ny thc hin nh sau:
Theo phng php ny yu cu s phn t lu tr chnh bng gi tr n, bng bc ca a thc mu s trong hm truyn b iu khin s cho. T cc ng thc (1.9) v (1.10) ta cng d dng xy dng c gin trng thi m t hm truyn ca b iu khin s (gi thit m=n=3).
262
Hnh 6 10: Gin trng thi ca h thng s Trin khi lp trnh s ghp tng Cch trin khai ny yu cu chuyn i b iu khin v dng tch ca cc hm truyn n gin c th d dng thc hin bng cc chng trnh n gin. Hay ni cch khc b iu khin s cho l kt qu ghp tng ca nhiu b iu khin nh. Trin khai lp trnh s song song B iu khin cho s c tch ra thnh tng ca cc b iu khin n gin v c th thc hin lp trnh song song cho cc b iu khin . 6.4.2 V d trin khai b iu khin PID s Xp x ho thnh phn vi tch phn C 3 phng php xp x gin on ph bin p dng cho cc thnh phn tch phn: vt trc (forward), vt sau (backward), v trapezoidal. Xp x sai phn vt trc
p dng chuyn i z cho (1.11) ta thu c
D xp x ho tch phn s l:
263
Hnh 6 11: Xp x sai phn vt trc Xp x sai phn vt sau Tng t nh sai phn vt trc ta c xp x tch phn nh sau:
Hnh 6 12: Xp x sai phn vt sau Xp x Trapezoidal Php xp x tch phn thu c s l:
264
ng thc l tng m t b iu khin PID
trong , K l h s khuch i, TI l hng s thi gian tch phn, TD l hng s thi gian vi phn. Trong trng hp chu k trch mu nh, ng thc (1.16) c th c chuyn sang dng ng thc sai phn bng phng php ri rc ho. Trong , thnh phn vi phn c th c xp x nh php tnh sai phn bc nht v thnh phn tch phn c xp x dng vt trc. Bng php ri rc ny ta thu c ng thc m t b iu khin PID s nh sau:
T ng thc (1.17) ta d dng nhn thy rng thc thi b iu khin PID cn thng tin ca tt c cc sai lch e trong qu kh. thun tin cho vic thc hin lp trnh, dng qui s ph hp hn v c th rt ra t (1.17) nh sau:
T (1.17) v (1.18) ta rt ra c algorithm iu khin ca PID s:
265

Trong :
M hnh b iu khin dng hm truyn ta c:
trong , thnh phn tch phn c th xp x theo mt trong ba cch nh m t trong phn 6.1, thnh phn vi phn c th c xp x nh sau:
108 t (1.21) c th xp x hm truyn thnh phn vi phn
Nh vy hm truyn ca b iu khin PID s c th c xp x theo mt trong 3 dng nh sau:
Xp x vt trc:
Xp x vt sau:
Xp x Trapezoidal:
266

Xay Dung Cac He Thong Nhung V4-8.2011-BCVT

Uploaded by

Copyright:

Available Formats

You might also like

Xay Dung Cac He Thong Nhung V4-8.2011-BCVT

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Xay Dung Cac He Thong Nhung V4-8.2011-BCVT

Uploaded by

Copyright:

Available Formats

HC VIN CNG NGH BU CHNH VIN THNG

Khoa Cng ngh thng Tin B mn Khoa hc my Tnh

XY DNG CC H THNG NHNG

H Ni, thng 7 nm 2010

Xy dng cc h thng nhng: M u v Mc lc

Xy dng cc h thng nhng: M u v Mc lc

Xy dng cc h thng nhng: M u v Mc lc

Xy dng cc h thng nhng: M u v Mc lc

Xy dng cc h thng nhng: M u v Mc lc

OS RTOS ES HTN OS hay HH TKTB PLC

Programmable Intelligent Computer

My tnh kh trnh thng minh

Programmable System - on Chip Application-Specific Integrated Circuit

Xy dng cc h thng nhng: M u v Mc lc

Universal Serial Aynchronous Receiver/Transmitter Interrupt Service Routine

Media Access Control

L loi thit b phn cng dng g ri khi pht trin 7

Xy dng cc h thng nhng: M u v Mc lc

Danh sch cc hnh v

Xy dng cc h thng nhng: M u v Mc lc

Xy dng cc h thng nhng: M u v Mc lc

Xy dng cc h thng nhng: M u v Mc lc

Xy dng cc h thng nhng: M u v Mc lc

3.11 3.12 3.13 3.14 3.15

156 157 158 159 160

4.1 4.2 4.3 4.4 4.5 4.6

164 165 166 167 168

171 172 176 177 177 178

4.7 4.8 4.9 4.10 4.11

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Lnh vc ng dng t in t tiu dng

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

B vi x l trung tm (CENTRAL PROCESSING UNIT)

H thng ng dy iu khin (CONTROL BUS)

dy d liu (DATA BUS)

Ghp ni ra (O) Ngun nui mt chiu

Hnh 1.1- M hnh tng qut bo mch ch

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

HTN xy dng t xy dng t vi x l(Microprocessor-based) v vi iu khin (microcontroller based) 20

Chng 1: Gii thiu chung v h thng nhng

Microcontroller v cc thnh phn c bn, BUS kt ni bn trong.

Kin trc ca CPU

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Hnh 1.4-Hai kiu HTN vi 2 loi kin trc CPU

Harvard, Modified Harvard, or von Neumann?

Chng 1: Gii thiu chung v h thng nhng

Modern uses of the Modified Harvard architecture

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng

Chng 1: Gii thiu chung v h thng nhng