P-58 / H. N.

Nguyen

P-58: A Differential Multi-bit/Conversion Cyclic DAC for TFT-LCD Column Drivers

Hoai-Nam Nguyen, Yeong-Shin Jang, Jeong-Yeol Bae, Huy-Binh Le, and Sang-Gug Lee
Department of Information and Communications Engineering, Korea Advanced Institute of Science and Technology, Daejeon, Korea

Abstract
A differential cyclic 10-bit DAC with multi-bit conversion per cycle architecture is presented. Passive conversion is done within 1s and the output is driven during the rest of 1-H time. Designed in differential scheme, the switched-capacitor circuit is robust to charge injection, clock feedthrough and capacitive noise coupling. The DAC has been designed for a high voltage 0.18-m CMOS technology.

voltages should be clean at the end of sampling period. In addition, inevitable charge injection and clock feedthrough effects are critical issue in this design. An alternative to CDAC, integration-type serial DAC has been implemented with significant size efficiency [5]. Weighting reference voltages generated from a global resistor string are sampled onto the sampling capacitor and redistributed into the integration capacitor. The bottom plate sampling, active switched-capacitor integrator shows accurate but slow conversion because of limitation in opamp current consumption. Therefore, this approach is not suitable for large panel, high resolution displays. This paper presents a differential multi-bit/conversion cyclic DAC architecture for 10-bit LCD column drivers. This architecture takes advantages of the CDAC in simple structure, small chip area and low power while guaranteeing fast conversion. The differential scheme helps the design overcome reference bounce, charge injection and clock feedthrough problems. The double in the number of capacitors is not burden when we keep the same total capacitor as [2].

1.

Introduction

Nowadays, TFT-LCDs are widely used from the portable devices to very large size televisions. The technology trend towards high resolution, high color depth, and high frame rate keep generating challenges to driver IC design [1]. Large screen displays have hundreds of channels; hence column drivers should be low power designs. Besides, the color uniformity between channel-tochannel and chip-to-chip leads to design consideration in offset regulation. Conventional 6 or 8-bit column drivers have been successfully designed with resistor-string digital-to-analog converter (RDAC). However, as DACs resolution increases for high quality display applications, full RDAC design has reached its size limitation because the circuit complexity increases exponentially as the resolution increases. In order to reduce the chip size of high resolution DACs, various interpolating DACs have been proposed as summarized in [1]. In those designs, the RDAC has been used for coarse analog range decision with MSB bits, and fine output is determined by the following LSB interpolation stage. Due to the size of decoders and routing from the global resistor-string to decoder in every channel, the chip area is still problematic. A promising architecture for compact LCD driver design is charge redistribution DAC using cyclic DAC (CDAC) [2-3]. The serial conversion CDAC has a simple structure with two identical capacitors and several switches. For accuracy up to 12-bit DAC, the active conversion is preference owing to parasitic insensitivity operation. However, active close-loop operation consumes more power to finish as many as number-of-bit conversion cycles in a given time. To avoid this issue, [2] introduces a new driving method for full line time driving with two DACs per channel; and [3] is a modification with just three swappable capacitors for two passive DACs and one driving opamp for each channel. The use of two DACs for one channel [2,3] may affect not only the channel-to-channel uniformity but also the in-channel uniformity. Speed improvement architecture with one multi-bit/cycle CDAC per channel [4] allows analog-to-digital conversion and driving process within one horizontal time (1H). Designed in single-ended topology, the switched-capacitor CDAC [4] is hard to achieve sub-microsecond conversion time because the bouncing reference

2.

Proposed Cyclic DAC Architecture

Figure 1 shows an embodiment of the multi-bit/conversion 10bit CDAC with two bits per cycle in differential configuration. It is proved that the most effective design to eliminate the effects of charge injection and clock feedthrough is to use differential scheme accompanied with dummy switches. In this architecture, the negative part can be considered as the mirror of the positive part. The operation principle of the proposed CDAC is similar to that of a conventional CDAC [6]; but Mbit/conversion CDAC can convert M bits at once making M times speed improvement. Resolution of multi-bit/conversion CDAC can be increased without changing the core hardware. The 10-bit input data b9b8b7b6b5b4b3b2b1b0 is organized into groups of two bits (b1b0), (b3b2),, and (b9b8) successively fed to CDAC. Firstly, the storing capacitors (CH) are reset. In sampling phase (SP), sampling capacitors (C) are pre-charged to reference voltages depending on the code (b2n+1b2n) with n = 0-4. Bits b2n are used to sampling weighted-0 capacitors (1C), while b2n+1 are used to sampling weighted-1 capacitors (2C) which are separated into two identical capacitors (C) for better DNL. After sampling phases, the charges on sampling capacitors and storing capacitors are redistributed in charge sharing (CS) phases to perform an algorithmic digital-toanalog conversion. With 10-bit conversion in five clock cycles, the DAC has been doubled in speed compared to conventional one.

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(a)

(b) (a)

(c) (b) Figure 1. Simplified schematic of a differential 10-bit CDAC with 2-bit/conversion (a) and clock diagram (b) The output voltages of 10-bit CDAC in Figure 1 through five conversion cycles can be expressed as Figure 2. RMS INL simulation of M-bit/conversion 10-bit CDACs, M=1, 2 and 5 (a) 1-b/c capacitor mismatch 0.12%, (b) 2-b/c capacitor mismatch 0.15% and (c) 5-b/c capacitor mismatch 0.43% Increasing M -bit/conversion leads to reduction of matching requirement and conversion time. However, the holding capacitor CH is getting smaller; while the number of CS switches increased makes the charge injection and clock feedthrough more serious. Therefore, in this work, the architecture of 10-bit CDAC with two bits per cycle is used. Double speed operation is achieved with reduction in matching requirement in contrast to [7] which require more capacitor matching. The 10-bit CDAC design with driving buffer is shown in Fig.3. In order to get better charge injection and clock feedthrough cancellation, the CDAC core is designed to operate in a scale down voltage. By doing that, the positive and negative part experience similar charge injection, clock feedthrough error, captive coupling noise and supply bounce, thus the differential output will suffer from those problems. During conversion time (CONV), the switched capacitor network performs passive conversion in differential mode as presented above. After a conversion process has been done, we can consider the capacitor banks are sampled with the desired voltage of DAC output. In driving phase (DRIV), by connecting bottom plates of the capacitor banks to common voltage (Vcm), the charge in sampling capacitor banks is redistributed onto buffer capacitors (CB) for driving to the load line with a class AB output stage opamp.

Vout =

Vref Vref Vref (2b9 + b8 ) + (2b9 + b8 ) + (2b9 + b8 ) + 4 16 64

Vref Vref Vref (2b9 + b8 ) + (2b9 + b8 ) = 10 4 16 2

2 b ;
i i =0 i

where Vref = VH VL = 2(VH Vcm ) = 2(Vcm VL ) In the design, sampling (SP) and reset (RST) switches are implemented with dummies at the capacitor side to cancel charge injection effect when the switches turn off. The charge sharing (CS) switches use dummies in both sides to cancel charge injection error in both turn on and turn off transitions. The 10-bit CDAC can be designed with 1-bit, 2-bit or 5-bit conversion per cycle. We have estimated matching requirement for each topology. In TFT-LCD column driver application, INL error is more important than DNL one because INL determines output voltage derivation of the driver ICs. For the target of RMS INL <= 0.4 LSB (expect less than 1 LSB in silicon implementation), the capacitor matching requirement for 1-bit, 2bit and 5-bit/conversion topology are 0.12%, 0.15% and 0.43 %, respectively. The results presented in Figure 2 were done with behavioral simulation in MATLAB for 10,000 samples.

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(a)

Figure 4. Simulated DNL and INL of positive polarity CDAC

(b) Figure 3. Differential 10-bit CDAC with 2-bit/conversion for LCD column drivers (a) and clock diagram (b) The switched capacitor amplifier with gain x4 is implemented with the architecture present in [6]. The piecewise DAC can be achieved with swapping references or connections between the CDAC core and buffer. To avoid the error from using small capacitor CB, the whole capacitors in the CDAC core are used as the sampling capacitors in amplification mode; therefore, ten capacitors are identical with the typical value of 100fF. The designed MIM capacitance units of 100fF with matching accuracy better than 0.1% can be satisfied 10-bit linearity requirement.

3.

Simulation Results
Figure 5. Simulated DNL and INL of negative polarity CDAC Figure 4 and 5 show the DNL and INL simulations of the proposed DAC using Cadence Spectra. The maximum DNL and INL are 0.5 LSB and 0.6 LSB, respectively, for 0.1% capacitor mismatch. The DNLs increase at (k*256) codes because of error accumulation with 11111111 LSB bits.

The 10-bit cyclic DAC shown in Figure 3 for a large size panel column driver is designed using a 0.18 m, 13.5V CMOS technology. The digital ramp signal for the column driver simulation has been built to simulate driver operation with full codes from 0000000000 to 11111111111. The class AB opamp with rail-to-rail output stage [8] has been designed for the DAC. It draws 6 A static current and no slew enhancement technique is needed. The setting time for 0.5 LSB error (2mV) at the lineend node is about 5 s including 1s conversion time at 150 pF and 10K load.

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P-58 / H. N. Nguyen 4. Conclusion 6. References

format, IEEE Transactions on Consumer Electronics, Vol. 51, No. 4, pp 1042- 1050, Nov. 2005.

A speed and power efficient 10-bit CDAC with 2-bit conversion per cycle scheme has been proposed for column drivers. Charge injection, clock feedthrough errors and substrate coupling are minimized with differential scheme. The circuit can be suffered from reference and supply bounces, thus reduces conversion time. The simple structure CDAC with total capacitor of 1 pF shows the capability of low cost source driver ICs for high resolution and large size LCDs. Table 1 Performance summary Parameter Gray level Voltage supply Settling time DNL/INL Power consumption Display application Technology Performance (simulation) 10-bit linear 13.5 V Analog 5 us (10K+150pF RC) 0.5/0.6 LSB 6 uA/channel Medium, large size monitors, TVs 0.18 um CMOS

[1] J.H. Kim, et al., 1-bilion-color TFT-LCD TV with full HD [2] M.J. Bell, An LCD column driver using a switch capacitor
DAC, IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, pp 2756- 2765, Dec. 2005.

[3] Y.K. Choi, et al., A compact low-power CDAC architecture

for mobile TFT-LCD driver ICs, ISSCC 2008 Digest of Technical Papers, pp 176-177.

[4] H.N. Nguyen, et al., A Multi-bit/Cycle 12-bit Cyclic DAC

for TFT-LCD Column Drivers", IDW Proceeding 2008, pp 263-266.

[5] K.D. Kim, et al., A 10-bit serial integration-type DAC

architecture for AMLCD column drivers, SID 2009 Digest of Technical Papers, pp 379-382.

[6] S.K. Kim, Design of analog circuits for column driver ICs
and backlight inverters of LCD TVs, Dissertation KAIST 2006.

5.

Acknowledgements

[7] H.B. Le, et al., Double Speed Cyclic Digital-to Analog

Converter ", IEEE HUT-ICCE Conference 2008.

This research was financially supported by the Ministry of Education, Science Technology (MEST) and Korea Institute for Advancement of Technology (KIAT) through the Human Resource Training Project for Regional Innovation.

[8] J.H. Huijsing, Operational Amplifiers: Theory and Design,

Kluwer Academic Publishers, 2001.

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