P.

NARASIMHA MURTHY
Application Engineer Mobile: +91-9849693071, 8985418976 Email: pandrapragada.nm@gmail.com Objective
To obtain a challenging fulltime position where I can use my electronics and communication engineering and VLSI System Design skills for the design and development of products and technology

Industrial Experience
Total Experience: Around 2.5 Years

Presently Working as Application Engineer from March 2011 in Core-EL

Technologies (I) Pvt. Ltd., Hyderabad, Andhra Pradesh, INDIA.

Worked as Design Engineer from October 2009 to April 2011 in VISION KREST
Embedded Technologies Pvt. Ltd., Hyderabad, Andhra Pradesh, INDIA

Present Work Summary Provides post-sales technical expertise during the installation, implementation, and
maintenance of Mentor Graphics Products and Xilinx Products with Defence Accounts and Private Accounts.

Provides pre-sales support to company sales staff and customer personnel. Handeled EDA tool products in the areas of Synthesis, Simulation, Verification, Place
and Route.

Handled different Technical Issues at Tool level, Design level and system level. Attended GDC Boot camp AE training given by Mentor Graphics at China. Get trained on Basic level UVM Methology for verification with Questa product from
Mentor Graphics.

Get Trained on C/C++ for AutoESL product from Xilinx, and catapult-C from Mentor
Graphics.

Professional Summary
Strong in Digital Design concepts

Good hands on RTL coding (VHDL and Verilog HDL) and Xilinx FPGA Flow

 Worked on RTL Synthesis

Worked on Programming FPGA Boards using ChipScope-Pro

Good Knowledge on System Verilog Basics

Good Knowledge on ASIC Front end & Backend Good Knowledge on VCS, Design Compiler, and Astro tools from synopsis (These tools
are used during my masters)

EDA Tools Simulations : ModelSim, Questa-Sim Synthesis : Xilinx-ISE, Precision Synthesis Design Entry: HDL Designer ESL Tools: AutoESL, Catapult-C Education Profile 2007-2009 Master of Science [Engineering] in VLSI System Design from Coventry
University, UK, (Off-Campus Collaborative programme with M.S. Ramaiah School of Advanced Studies), Bangalore, India.

2006-2007 Post Graduate Diploma in VLSI System Design and Embedded Systems in
CITD (Central Institute of Tool Design), Certified jointly by ECIL (Electronics Corporation of India limited), Hyderabad, India.

2002-2006 Bachelor of Technology (B.Tech.) in Electronics and communications

engineering from JNT University, Hyderabad, India.

Projects Involved
Project Title : Design & FPGA Implementation of Lossless DWT and IDWT for Medical Images Tools : ModelSim, Xilnx-ISE and ChipScope-Pro
Description : The basic idea of this work is Image Transformation and DeTransformation in which both DWT and IDWT blocks were designed using Lifting based scheme which has lower computational complexity. The DWT and IDWT are modeled using Verilog HDL and design is validated using suitable test vectors. Modeled design has been synthesized and implemented on FPGA family of Spartan 3E (XC3S500E) using Xilinx ISE and ChipScope Pro tool.

Project Title : Design of Viterbi Decoder for Wireless Applications Tools : ModelSim and Xilnx-ISE and ChipScope-Pro
Description : The work presents the design of Viterbi Decoder that acts as a powerful method for Forward Error Correction. It checks every node for path metric value and eliminates the path that is found and any path passing the state with greater metric will affect the probability of error decoding. This architecture modeled with Verilog HDL and functional verification was done for an appropriate test cases. The modeled design was taken to the Synthesis process in Xilinx-ISE Tool.

Project Title : Design & ASIC Implementation of 10/100 Mbps Ethernet Switch for Networking Application (Academic Project) Tools : ModelSim, Xilinx, VCS, Design Compiler, Astro and Primetime
Description : This work presents a switch which conforms to the IEEE 802.3 Ethernet specifications. All nodes are capable of full duplex operation. All the sub modules of Ethernet switch and top level block are modeled in verilog HDL. The designed switch is a modified-cut-through type with dedicated memory for each input port and a common memory for the output ports. The look-up table for MAC addresses is designed on a linear search algorithm for optimum speed. The same design was synthesized using TSMC 0.18m technology with optimal constraints in Design Compiler (DC) and P&R was carried out using Astro tool.

Strengths
Team player Target and achievement oriented with an ability to take up challenges and perform in challenging work environments Unique blend of technical and interpersonal skills combined with proficiency in MsOffice Suite Quick Learner and Adjustable to the desired Environment

Personal Details
Date of Birth : 10th November, 1984

Marital Status Languages Known Nationality PAN Card Number Passport Number

: Single : English, Hindi, Telugu, Tamil and Kannada : Indian : BDMPP7469L : Provided up on Request

I hereby declare that the above-furnished information is true and genuine to the best of my knowledge.

Place: Hyderabad

P. Narasimha Murthy