Wafer Level Package and Technology

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Enabling a Microelectronic World

Wafer Level Packaging

Fab-like WLP, Hybrid packaging: Fab and Assy

Most or all of processing related to packaging the die is done at

wafer level, using redistribution and bumping

WLP, bumping and WLCSP are closely related and sometimes,

used interchangeably 70% of WLP business is directly related to cell phone application
2008 global cell phone production: 1.3B unit 3.5M cell phones manufactured per day; every day!!

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Why Consider Wafer Level Packages?

Cost
Packaging cost Test cost Batch Processing
High Parallelism Improved test concepts

Dimensions
Smallest package heights Minimum lateral area

Package height ( ) Lateral dimensions (

I/O Density
Pitches ( ) No standards Small chips / high no. of I/Os

Min pitches

Wafer Level Packages

Min line length Multilayer RDL Reduced no. of interconnects

Electrical Performance
Interconnect line length ( ) Operating frequencies ( ) Package Speed ( Parasitics

Integrated passives in RDL SiP / 3D capability

Improved chip to board coupling

Functionality (Integration)
Integrated Passives (R, L, C) System in Package 3D

Thermal Performance
Power consumption ( Package Density ( ) )

= Increase = Decrease
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Wafer Level PKG Classification

Wafer Bumping
- Solder bump - Cu Pillar bump

WLCSP

Next Generation:
IPD, TSV, MEMS

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Fine Pitch Trend in Bump/WLP

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Whats Different in WLP?

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Multilevel Wiring/Inductor/Cu Bar

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WLCSP Defined
Wafer Level Chip Scale Package is defined by Amkor as
follows:
Die size package Mounted directly onto final substrate (typically PCB) No underfill required Assembled using standard SMT pitch & assembly equipment

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Whats Different about Wafer Level Package? Traditional Package Flow

Assy Assy

Test Test Test Test

Mark Mark
PACK

Wafer Fab

Test

Dice
Assy Assy Mark Mark

SHIP

Flip Chip

Wafer Level Package Flow

Wafer Fab

Bump

Test Sort

Mark

Dice

SHIP

Pick
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Whats driving adoption of WLP?

Footprint (die = package; more functions same space) Performance (bumps < Inductance than wire-bond) Legacy die converted to WLP through use of RDL (<< $ and
time than silicon redesign)

Thin package profile (Z max <= 1.0 mm) SiP (fine pitch: 85 m/40 m bump) Improved reliability in non-underfilled parts (temp cycle >
1,500 cycles -40 to +125 C)

Cost (now competitive with other package types) Application Expansion & Substitution

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Future WLCSP Developments

Thinner Package Height (<0.5 mm) Finer Bump Pitch (~ 0.3 mm) Increased I/O count (144-196 I/Os and beyond) Ultra low-k materials Increased drop test and temp cycle ranges Increased Thermal and Power requirements Through-Wafer Via Technologies Embedded Silicon Technologies

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WLFO(Wafer Level Fan Out)

Increased I/O, Reduced pkg thickness, electrical/thermal
performance

Potential cost reduction compared to conventional packages

(fcCSP, wbCSP, MLF)

Potential for very thin POP configuration as technology is

extended beyond single die package

New infrastructure, higher cost Yield and manufacturing cost will be a challenge

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Standard WLCSP vs. WLFO

Both use fab level processes to build redistribution layer WLCSP created within device footprint WLFO created within and beyond device footprint

Standard Wafer
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AMKOR WLFO Molded Wafer

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WLCSP vs. WLFO X-Sections

Device Silicon Area Device Silicon Area
Fan Out (Molded
Area)

Solder ball
Dielectric 1 Dielectric 2 Dielectric 1 Dielectric 2

Redistribution Layer

Redistribution Layer

Standard WLCSP (RDL on a Silicon Wafer)

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WLFO (RDL on Reconstituted Wafer)

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Effect of Die Shrink on WLCSP

As die shrinks with each successive Silicon node, cannot fit
Ball Grid Array on die without reduction in BGA pitch

End users do not like BGA pitch reduction due to increase

motherboard and SMT process cost => Need to Fan Out Interconnections

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Process Flow
Film lamination

Die placement

Compression molding

Debonding from carrier

RDL Process

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Amkor WLFO
Fan out Area Si chip RDL(Redistribution)

Solder ball

Dielectric

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