Contents

S.No. No. 1. 2. 3. 4. 5. 6. 7. 8. 8 Title Introduction.. Page 3

Functional Test Generation with RTPG. 3 Synthesis. 4

Coverage Metrics.. 7 Results.. Error Injection.. 7 8

Coverage Summary for the modules simulated. Coverage Report.. 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.8. 8.9. 8.10. 18 8.11. 19 8.12. 20 Or1200_ctrl.. Or1200_alu Or1200_dc_fsm Or1200_freeze. Or1200_sb_fifo. Fpu_adder.. Fpu_divider Fpu_except Fpu_fpu 9 9 10 11 12 13 14 15 16 17

Fpu_multiplier. Fpu_post_norm Fpu_pre_norm_fmul..

8.13. 21 9. 10.

Fpu_pre_norm.. 22

Conclusion..

References 22
LIST of Figures

Introduction: With an ever increasing trend in chip complexity, it has become increasingly difficult and expensive to verify the design extensively. Several methodologies have been proposed to cut down the verification expense and time. One such methodology is verification through random test program generation (RTPG). Functional test generation with RTPG methodology: In the RTPG methodology, the inputs are excited with random vectors and the output is checked for correctness. To generate such a vast set of vectors is a cumbersome effort and hence it is automated. This reduces the cost of verification. Simulations can be run till the required coverage targets are reached. However, it is difficult to achieve 100% coverage in all the designs. Sometimes the vast set of random vectors is constrained to a search space. This increases the probability of hitting valid states and hence reduces the time taken for verification.

Figure Verification Environment

In this project, the gate level netlist is verified against the RTL design. The synthesis is performed using Design Compiler from Synopsis. The RTL belongs to Open RISC processor. There are several modules out of which 13 modules are taken for Gate synthesis. A testbench is developed for each of them and a miter is designed. RTPG simulation is performed and the coverage metrics are made sure to meet the expected coverage. The following are the modules that were selected for synthesis and verification.

1. Or1200_ctrl 2. Or1200_alu 3. Or1200_freeze 4. Or1200_sb_fifo 5. Or1200_dc_fsm 6. Fpu_adder 7. Fpu_divider 8. Fpu_exception 9. Fpu_fpu 10.Fpu_multiplier 11.Fpu_post_norm_gate 12.Fpu_pre_norm_fmul 13.Fpu_pre_norm Synthesis: Design Compiler was used to synthesize the RTL. The synthesis was performed without timing constraints, since only a translated gate level netlist for verification. The following are the different process performed in the Design Compiler. 1. Reading the Libraries The libraries are setup as a part of the .setup file that is placed in the project directory form where the dc_shell is invoked. This points to the GTECH library from which the design compiler uses the primitives and uses the same for synthesis. 2. Reading the Design The first task in synthesis is to read the design into Design Compiler memory. Reading in an HDL design description consist of two tasks: analyzing and elaborating the description. The analysis command (analyze) performs the following tasks: Reads the HDL source and checks it for syntactical errors Creates HDL library objects in an HDL-independent intermediate format and saves these intermediate files in a specified location. 5

If the analysis reports errors, they must be fixed, and the design reanalyzed before continuing. The elaboration command (elaborate) does e.g. the following: Translates the design into a technology-independent design (GTECH) from the intermediate files produced during analysis Allows changing of parameter values (generics) defined in the source code Replaces the HDL arithmetic operators in the code with DesignWare components Automatically executes the link command, which resolves design references At this point, if the elaboration completed successfully, the design is represented in GTECH format, which is an internal, equation-based, technology-independent design format. 3. Constraining the Design The Constraints are usually placed in the design compiler while getting the gate level netlist. Constraints are the instructions that the designer gives to Design Compiler. They define what the synthesis tool can or cannot do with the design or how the tool behaves. Usually this information can be derived from the various design specifications There are basically two types of design constraints: Design Rule Constraints: Design rules constraints are implicit constraints which mean that they are defined by the ASIC vendor in technology library. By specifying the technology library that Design Compiler should use, you also specify all design rules in that library. You cannot discard or override these rules. Optimization Constraints: Optimization constraints are explicit constraints (set by the designer). They describe the design goals (area, timing, and so on) the designer has set for the design and work as instructions for the Design Compiler how to perform synthesis. Design rule constraints comprise: a. Maximum transition time: 6

Longest time allowed for a driving pin of a net to change its logic value Maximum fanout Maximum fanout for a driving pin Maximum (and minimum) capacitance The maximum (and minimum) total capacitive load that an output pin can drive. The total capacitance comprises of load pin capacitance and interconnect capacitances. b. Cell degradation: Some technology libraries contain cell degradation tables. The cell degradation tables list the maximum capacitance that can be driven by a cell as a function of the transition times at the inputs of the cell. The optimization constraints comprise timing and maximum area constraints. The most common timing constraints include:

a. System clock definition and clock delays: Clock constraints are the most important constraints in your ASIC design. The clock signal is the synchronization signal that controls the operation of the system. The clock signal also defines the timing requirements for all paths in the design. Most of the other timing constraints are related to the clock signal. b. Multicycle paths: A multicycle path is an exception to the default single cycle timing requirement of paths. That is, on a multicycle path the signal requires more than a single clock cycle to propagate from the path startpoint to the path endpoint. Input and output delays Input and output delays constrain external path delays at the boundaries of a design. Input delay is used to model the path delay from external inputs to the first registers in the design. Output delay constrains the path from the last register to the outputs of the design. c. Minimum and maximum path delays: Minimum and maximum path delays allow constraining paths individually and setting specific timing constraints on those paths. 7

Input transition and output load capacitance These constraints can be used to constrain the input slew rate and output capacitance on input and output pins. d. False paths: A false path is a path that cannot propagate a signal. For example, a path that is not activated by any combination of inputs is a false path. In this project, the constraints are not given because of the fact that only gate level netlist is required sans optimization. 4. Optimization Optimization can take place in several perspectives. a. Architectural Optimzation b. Logic-level Optimizations c. Gate-level Optimizations 5. Saving the Design After optimization the design is saved into gate-level netlist format. The generic design compiler flow is illustrated below. script can be found in Appendix I. The design compiler

Figure Design Compiler Synthesis flow

Coverage metrics:

Coverage metrics quantify the efficacy of the test. There are several coverage metrics, the most important of them are: 1. Statement Coverage: This measures the percentage of lines in the RTL coverage during simulation. 2. Toggle Coverage: Toggle coverage gives the percentage of nets in the design that toggle in a simulation. 3. Branch Coverage: This measures if all the conditional branches in a design have been taken during simulation. 4. FSM Coverage: This measures if all the paths to all the states in a Finite State machine have been excited during simulation. The Testbenches of all the modules and the script files to automate the simulation are given in Appendix II. Below are the results for each of the blocks. Results: The testbench results of the miter and the coverage statistics are populated below for all the modules considered.

Error Injection: For each of the module, errors are injected manually in the gate level netlist and made sure they are captured by the miter. The below figure represents the miter design.

Figure Miter Design

Coverage summary for the modules simulated. S.No. Module RTL Coverage Statemen t 1 2 3 4 5 6 7 8 9 10 11 Or1200_ctrl Or1200_alu Or1200_dc_fsm Or1200_freeze Or1200_sb_fifo Fpu_adder Fpu_divider Fpu_except Fpu_fpu Fpu_multiplier Fpu_post_norm 98.5% 100% 97.2% 100% 100% 100% 100% 100% 100% 100% 82.8% Branc h 99% 86.4% 91.8% 100% 100% 100% 100% 100% 94.4% 94.4% 85.5% 10 Toggl e 94.6% 99.2% 94.9% 100% 99% 100% 77% 86.1% 97.5% 100% 97.8% Gate level netlist Coverage Statemen t 100% 100% 100% 100% 100% 95.2% 100% 100% 100% 100% 100% Branc h N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Toggle 97.6% 93.5% 93.6% 100% 99.8% 100% 98.1% 93.4% 90.4% 90.4% 92.2%

12 13

Fpu_pre_norm_fmul Fpu_pre_norm

100% 100%

100% 97.2%

98.3% 97.9%

100% 96.4%

N/A N/A

96.6% 96.8%

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Coverage Reports: 1. Or1200_ctrl It is an Instruction Decoding control unit.

Figure Coverage Report for or1200_ctrl

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is less because few states were not reachable. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. FD2 \ex_simm_reg[7] ( .D(), .CP(clk), .CD(n879), .Q(ex_simm[7]), .QN(n375) ); FD2 \id_insn_reg[6] ( .D(n538), .CP(clk), .CD(), .Q(id_simm[6]), .QN(n875) );

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2. Or1200_alu This is the Arithmetic Logic Unit of the Processor.

Figure Coverage Report for or1200_alu

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is less because few states were not reachable. Branch coverage is 50% because there are no mismatches when no errors are injected. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. ND4 U757 ( .A(n793), .B(n794), .C(), .D(n796), .Z(result[27]) );

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AO1 U758 ( .A(n724), .B(), .C(n798), .D(n799), .Z(n796) );

3. Or1200_dc_fsm This is the data cache of the Finite State Machine.

Figure Coverage Report for or1200_dc_fsm

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is less because few states were not reachable. Branch coverage is 50% because there are no mismatches when no errors are injected. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. NR3 U441 ( .A(n498), .B(dirty), .C(), .Z(n515) ); 14

IV U442 ( .A(dcqmem_we_i), .Z() );

4. Or1200_freeze: This module is the freeze signal generation module. It generates signals like stall, flush etc.

Figure Coverage Report for or1200_freeze

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is also 100% as there are less internal wires. Branch coverage is 50% because there are no mismatches when no errors are injected. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. 15

OR2 U48 ( .A(), .B(id_freeze), .Z(if_freeze) ); OR2 U49 ( .A(force_dslot_fetch), .B(), .Z(id_freeze) );

5. Or1200_sb_fifo: This module is the store buffer FIFO.

Figure Coverage Report for or1200_sb_fifo

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is less because few states were not reachable. Branch coverage is 100% because there were mismatches when no errors are injected. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. 16

MUX21L U646 ( .A(n1078), .B(n1079), .S(N20), .Z() ); MUX21L U647 ( .A(), .B(n1081), .S(N20), .Z(N29) );

6. Fpu_adder: This is the adder module of the FPU.

Figure Coverage Report for fpu_adder

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is little less because few states were not reachable. Branch coverage is 50% because there were no mismatches. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. 17

EO U94 ( .A(n86), .B(), .Z(n89) ); EON1 U95 ( .A(n90), .B(n91), .C(n92), .D(A[11]), .Z() );

7. Fpu_divider: This is the divider module of the fpu.

Figure Coverage Report for fpu_divider

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is less because few divider exponents like not a number (nan), underflow, overflow were not reachable. Branch coverage is 50% because there were no mismatches. Random Error Injection:

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Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. AO7 U88 ( .A(n79), .B(n39), .C(), .Z(DIFF[37]) ); NR2 U89 ( .A(n12), .B(A[37]), .Z() );

8. Fpu_except: This is the fpu exception handling unit.

Figure Coverage Report for fpu_except

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is less because few exceptions were not generaed. Branch coverage is 50% because there were no. Random Error Injection: 19

Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. FD1 opa_inf_reg ( .D(n27), .CP(clk), .Q() ); FD1 snan_r_a_reg ( .D(), .CP(clk), .Q(snan_r_a), .QN(n84) );

9. Fpu_fpu: This is the top fpu module that includes all the other modules.

Figure Coverage Report for fpu_fpu

Coverage Results: The simulation takes a long time to get the above coverage. 100% Statement Coverage is obtained in all of the sub-modules. Toggle coverage is less because were not reachable. Branch coverage is 50% because there were no mismatches when no errors are injected. 20

Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. AN2 U32 ( .A(\ML_int[4][10] ), .B(), .Z(\ML_int[5][10] ) ); NR2 U33 ( .A(SH[4]), .B(n23), .Z() );

10.Fpu_multiplier: This is the multiplier module of fpu.

Figure Coverage Report for fpu_multiplier

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is little less because few states were not reachable. Branch coverage is 50% because there were no mismatches. 21

Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. EN U43 ( .A(n41), .B(), .Z(SUM[41]) ); AO6 U44 ( .A(n6), .B(n42), .C(n43), .Z() );

11.Fpu_post_norm: This module does the normalization after the fpu operations are completed.

Figure Coverage Report for fpu_post_norm

Coverage Results: 100% Statement Coverage is not obtained due to out of range numbers might not be generated. Even after running for several hours, the . Toggle coverage is little

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less because few states were not reachable. Branch coverage is 50% because there were no mismatches. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. AO2 U46 ( .A(n32), .B(n80), .C(), .D(n81), .Z(n79) ); ND2 U47 ( .A(n82), .B(n83), .Z() );

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12.Fpu_pre_norm_fmul: This module performs the normalization of floating point multiplier before operation.

Figure Coverage Report for fpu_pre_norm_fmul

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is little less because few states were not reachable. Branch coverage is 50% because there were no mismatches. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. EN U27 ( .A(A[4]), .B(), .Z(n24) ); AO5 U28 ( .A(ADD_SUB), .B(n3), .C(n25), .Z() );

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13.Fpu_pre_norm: This module performs the normalization of the operands for addition and subtraction.

Figure

Coverage Report for fpu_pre_norm

Coverage Results: 100% Statement Coverage is obtained. Toggle coverage is little less because few states were not reachable. Branch coverage is 50% because there were no mismatches. Random Error Injection: Errors were injected in random manner by removing connections etc. These were captured by the testbench by popping out Mismatch by the miter. AO4 U52 ( .A(n76), .B(n77), .C(A[2]), .D(), .Z(n75) ); EON1 U53 ( .A(B[1]), .B(n78), .C(n79), .D(A[1]), .Z() ); 25

Conclusion: Through this project, a complete gate level synthesis is performed for 13 modules of Open RISC processor and thorough design verification is done. The different coverage reports are analyzed and simulations are performed to meet the coverage target. Manual errors were injected and they are captured by the miter. The Appendix includes the RTL, Gate Level Netlist, Synthesis scripts and Simulation scripts used.

References: 1. http://classes.soe.ucsc.edu/cmpe125/Spring07/dc_tutorial/dc_tutorial.html 2. http://www.tkt.cs.tut.fi/tools/public/tutorials/synopsys/design_compiler/gsdc.ht ml 3. http://csg.csail.mit.edu/6.375/6_375_2008_www/handouts/tutorials/tut4-dc.pdf

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APPENDIX I Synthesis Scripts:

analyze -library WORK -format verilog {./SRC/or1200_alu.v} elaborate or1200_alu -library WORK check_design -multiple_designs current_design or1200_alu link compile write -format verilog -output {./SYN/NETLIST/or1200_alu_gate_gate.v} reset_design analyze -library WORK -format verilog {./SRC/or1200_freeze.v} elaborate or1200_freeze -library WORK check_design -multiple_designs current_design or1200_freeze link compile write -format verilog -output {./SYN/NETLIST/or1200_freeze_gate_gate.v} reset_design analyze -library WORK -format verilog {./SRC/or1200_sb_fifo.v} elaborate or1200_sb_fifo -library WORK check_design -multiple_designs current_design or1200_sb_fifo link compile write -format verilog -output {./SYN/NETLIST/or1200_sb_fifo_gate_gate.v} reset_design analyze -library WORK -format verilog {./SRC/or1200_ctrl.v} elaborate or1200_ctrl -library WORK check_design -multiple_designs current_design or1200_ctrl link compile write -format verilog -output {./SYN/NETLIST/or1200_ctrl_gate.v} 27

reset_design analyze -library WORK -format verilog {./SRC/or1200_dc_fsm.v} elaborate or1200_dc_fsm -library WORK check_design -multiple_designs current_design or1200_dc_fsm link compile write -format verilog -output {./SYN/NETLIST/or1200_dc_fsm_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_adder.v} elaborate add_sub27 -library WORK check_design -multiple_designs current_design add_sub27 link compile write -format verilog -output {./SYN/NETLIST/fpu_adder_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_divider.v} elaborate div_r2 -library WORK check_design -multiple_designs current_design div_r2 link compile write -format verilog -output {./SYN/NETLIST/fpu_divider_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_exception.v} elaborate except -library WORK check_design -multiple_designs current_design except link compile write -format verilog -output {./SYN/NETLIST/fpu_exception_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_final.v} elaborate fpu -library WORK check_design -multiple_designs current_design fpu link compile write -format verilog -output {./SYN/NETLIST/fpu_final_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_multiplier.v} elaborate mul_r2 -library WORK check_design -multiple_designs 28

current_design mul_r2 link compile write -format verilog -output {./SYN/NETLIST/fpu_multiplier_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_post_norm.v} elaborate post_norm -library WORK check_design -multiple_designs current_design post_norm link compile write -format verilog -output {./SYN/NETLIST/fpu_post_norm_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_pre_norm.v} elaborate pre_norm -library WORK check_design -multiple_designs current_design pre_norm link compile write -format verilog -output {./SYN/NETLIST/fpu_pre_norm_gate.v} reset_design analyze -library WORK -format verilog {./SRC/fpu_pre_norm_fmul.v} elaborate pre_norm_fmul -library WORK check_design -multiple_designs current_design pre_norm_fmul link compile write -format verilog -output {./SYN/NETLIST/fpu_pre_norm_fmul_gate.v} reset_design

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APPENDIX II Simulation Scripts: vopt work.tb_ctrl +acc -o tb_ctrl_coverage -cover sbceft2 -covercells vsim -coverage work.tb_ctrl_coverage add wave -r /* vopt work.tb_alu +acc -o tb_alu_coverage -cover sbceft2 -covercells vsim -coverage work.tb_alu_coverage add wave -r /* vopt work.tb_dc_fsm +acc -o tb_dc_fsm_coverage -cover sbceft2 -covercells vsim -coverage work.tb_dc_fsm_coverage add wave -r /* vopt work.tb_freeze +acc -o tb_freeze_coverage -cover sbceft2 -covercells vsim -coverage work.tb_freeze_coverage add wave -r /* vopt work.tb_sb_fifo +acc -o tb_sb_fifo_coverage -cover sbceft2 -covercells vsim -coverage work.tb_sb_fifo_coverage add wave -r /* vopt work.tb_fpu_adder +acc -o tb_fpu_adder_coverage -cover sbceft2 -covercells vsim -coverage work.tb_fpu_adder_coverage add wave -r /* vopt work.tb_fpu_divider +acc -o tb_fpu_divider_coverage -cover sbceft2 -covercells vsim -coverage work.tb_fpu_divider_coverage add wave -r /* vopt work.tb_fpu_exception +acc -o tb_fpu_exception_coverage -cover sbceft2 -covercells vsim -coverage work.tb_fpu_exception_coverage add wave -r /* vopt work.tb_fpu_final +acc -o tb_fpu_final_coverage -cover sbceft2 -covercells vsim -coverage work.tb_fpu_final_coverage add wave -r /* vopt work.tb_fpu_multiplier +acc -o tb_fpu_multiplier_coverage -cover sbceft2 -covercells 30

vsim -coverage work.tb_fpu_multiplier_coverage add wave -r /* vopt work.tb_fpu_post_norm +acc -o tb_fpu_post_norm_coverage -cover sbceft2 -covercells vsim -coverage work.tb_fpu_post_norm_coverage add wave -r /* vopt work.tb_fpu_pre_norm +acc -o tb_fpu_pre_norm_coverage -cover sbceft2 -covercells vsim -coverage work.tb_fpu_pre_norm_coverage add wave -r /* vopt work.tb_fpu_pre_norm_fmul +acc -o tb_fpu_pre_norm_fmul_coverage -cover sbceft2 -covercells vsim -coverage work.tb_fpu_pre_norm_fmul_coverage add wave -r /*

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