EE101B, Spring 2011 Department of Electrical Engineering Stanford University

Handout 19 Profs M. Hershenson, D. Colleran, S. Mohan

Homework 6
Due: Wednesday, May 25, 5:00 pm in box outside 203 CISX

Problem 1 : Open-circuit time-constants

Three-stage CMOS voltage amplifier

(a) Assuming that VBIAS is set so that all the transistors are saturated, find the numerical value of the small-signal voltage gain vout/vs, with the load resistor RL connected. Note that the current sources are not ideal. Replace each current source in the small-signal model with the parallel combination of roc,i and Coc,i. (b) Find the numerical value of the open-circuit time constant 1 associated with the capacitance from node 1, the input node at the gate of M1, and small-signal ground.*
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(c) Find the numerical value of the open-circuit time constant 2 associated with the capacitance from node 2 and small-signal ground.* (d) Find the numerical value of the open-circuit time constant 3 associated with the capacitance from node 3 and small-signal ground.* (e) Find the numerical value of the open-circuit time constant 4 associated with the capacitance from node 4 and small-signal ground.* * If necessary, transform any capacitances between the given node and another node using the Miller theorem to find the total effective capacitance between to small-signal ground. What is the gain-bandwidth product of this amplifier?

Problem 2 : Input capacitance

Effective input capacitance at the gate of a source-degenrated common-source amp In Lab 6, we stated without proof that the input capacitance at the second stage of the microphone pre-amplifier was effectively (if we ignore the parasitic package capacitances), Cin2 = Cgs2/(1+gm2REQ2) + Cgd2*(1+Av2). (a) Using the small-signal model in Figure 1, show that this is the case. Ignore the parasitic package capacitances, the transistors output resistance, and the capacitance at the source of transistor M2. (b) Give an intuitive explanation for the transformation of the Cgs and Cgd capacitances. (c) Also derive the input capacitance of the common-drain stage, Cin3 = Cgs3/(1+gm3REQ3) + Cgd3 (Hint: the you should be able to re-use your derivation from part a). For reference, the complete schematic is shown in Figure 2.

Figure 1: High-frequency small-signal model of microphone pre-amplifier from the lab

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Figure 2: Microphone pre-amplifier schematic from the lab

Problem 3: Folded cascode CMOS OTA

Goal: Understand and appreciate the operation of the popular folded cascode amplifier.
We analyzed an idealized folded cascode operational transconductance amplifier (OTA) in homework 5. This week, we replace the ideal current sources with transistors in the saturation region as shown in figure 3.

Figure 3: folded cascode operational transconductance amplifier Assumptions (to simplify analysis): all transistors are in saturation and all transistors have the same channel length L; all the pmos and nmos transistors have the same current, I, except transistors Mt, M3 and M4; which have twice the current of the other transistors; all the pmos signal path transistors have the same channel width Wp, except M3 and M4 which have twice the width of the other pmos transistors; all the nmos signal path transistors have the same channel width Wn, except transistor Mt which has twice the width of the other nmos transistors; all transistors have the same overdrive voltage Vgov; fully differential configuration and perfect matching in the fully-differential signal-path section so that all the bias voltages at nodes g3, g5, g7 and g9 can be assumed to be virtual ground nodes for differential small-signal considerations; fully differential small-signal excitation at the inputs (Vinp, Vinn) and assume we are interested in the differential transfer function (Voutp-Voutn)/(Vinp-Vinn).
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Assume the following numerical values:

M3, M4 and Mt have a gm of 2 mS, while all the others have a gm of 1 mS; M3, M4 and Mt have a gds of 0.062 mS, while all the others have a gm of 0.031 mS; ignore gmb5, gmb6, gmb7 and gmb8; total capacitance of 1pF at each of the nodes connected to the drains of M1 and M2; total capacitance of 10pF at each of the nodes Voutn and Voutp; ignore any capacitance at the nodes connected to the drains of M9 and M10 in order to simplify the calculations; all transistors have an overdrive voltage (Vgov) of 0.2V.
3.1. DC biasing (ignore channel length modulation and the body effect throughout this section): 3.1.a. What is current, I, needed to achieve a transconductance, gm, of 1mS with an overdrive voltage of 0.2V ? 3.2. Small signal transfer function Leverage the analysis done in question 3 of the previous homework. Do not draw any new small-signal models nor do any node equation analysis. Rather, adopt the results from the previous homework for the output impedance, short circuit current and the transfer function. Some useful results have been reproduced below for the small signal model.

Figure 3b: small signal half-circuit for question 3 from the previous homework.

Output impedance : g m 5 rds 5 rds1 + rds1 + rds 5 + jrds1rds 5C1 g m 5 rds 5 rds1 zout = 2 1 + jrds1C1 + jC L ( g m 5 rds 5 rds1 + rds1 + rds 5 ) rds1rds 5C1C L 1 + jC L g m 5 rds 5 rds1

Short circuit current : g m1rds1 (g m 5 rds5 + 1)vin g m1vin isc = (g m5rds 5 rds1 + rds1 + rds 5 + jrds 5 rds1C1 ) jC1 1 + g m5 Transfer function : vout isc zout g m1rds1 ( g m 5 rds 5 + 1) = = vin vin 1 + jrds1C1 + jC L ( g m 5 rds 5 rds1 + rds1 + rds 5 ) 2 rds1rds 5C1C L
vout vin g m1rds1 g m 5 rds 5 ADC (1 + jC L g m5 rds 5rds1 )1 + jC1 1 + j 1 + j g m5 pout pcas

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3.2.a. What is the differential output resistance of the circuit looking up into the drains of M5 and M6 (hint: Use the DC differential output expression format that you derived in the last week after determining which other resistances need to be added in parallel with the output resistance of M1 in order to capture the output resistance of the M1-M6 differential transistor circuit)? 3.2.b. What is the differential output resistance looking down into the drains of M7 and M8 (hint: Use the DC differential output expression format that you derived last week after determining which transistor gm and gds values are needed to capture the output resistance of the M7-M10 differential transistor circuit)? 3.2.c. What is the differential output resistance (hint: use the results from 3.2.a and 3.2.b above)? 3.2.d. What is the differential output impedance ? For this section, ignore capacitances at all nodes except the output nodes. 3.2.e. What is the output differential short circuit current (hint: use the result from the previous homework)? 3.2.f. Express the output transfer function in phasor form (hint: use the results from 3.2.d and 3.2.e above).

3.3. DC gain, 3dB bandwidth and the gain-bandwidth product 3.3.a. What is the magnitude of the transfer function? 3.3.b. What is the DC gain? 3.3.c. What is the 3dB bandwidth? 3.3.d. What is the gain-bandwidth product? 3.3.e. How do the DC gain, 3dB bandwidth and the gain-bandwidth product compare to that of a single-transistor common source amplifier (also with a gm of 1 mS and a gds of 0.031 mS) with an ideal current source load and with a total capacitance of 10pF at the drain node (output) of the transistor ?

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