DESIGN OF DIFFERENT TECHNIQUES TO REDUCE SUBTHRESHOLD LEAKAGE IN LOW POWER DIGITAL CIRCUITS Abstract

Low power circuit operation is becoming an increasingly important metric for future integrated circuits. As portable battery powered devices such as cell phones, pagers, PDAs and portable computers become more complex and prevalent, the demand for increasing battery life will require designers to seek out new technology and circuit technologies to maintain high performance and long operational lifetimes. In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. Therefore scaling and power reduction trends in future technologies will cause sub threshold leakage currents to become an increasingly large component of total power dissipation. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This project focuses on circuit optimization and design automation techniques to accomplish this goal. This dissertation develops new circuit techniques that exploit dual threshold voltages and body biasing in order to reduce subthreshold leakage currents in both standby and active modes. To address standby leakage currents, a novel sleep transistor sizing methodology for MTCMOS circuits was developed and new imbedded dual Vt techniques were described that could provide better performance and less area overhead by exploiting different logic styles. Work was also done to develop new MTCMOS sequential circuits, which include a completely novel way to hold state during standby modes. Body biasing circuit techniques were also explored to provide dynamic tuning of device threshold voltages to tune out parameter and temperature variations during the active state. This not only helps reduce active leakage currents but also improves process yields as well. A final research direction explored optimal VCC/Vt tuning during the active modes as a function of varying workloads and temperatures so that a chip can automatically be configured to operate at the lowest energy level that balances subthreshold leakage power and dynamic switching power. Through novel circuit techniques and methodologies, this work illustrates how subthreshold leakage currents can be controlled from a circuit perspective, thereby helping to enable continued aggressive scaling of semiconductor technologies.

MURALI KRISHNA

K.SOWJANYA

DESIGN OF DIFFERENT TECHNIQUES TO REDUCE SUBTHRESHOLD LEAKAGE IN LOW POWER DIGITAL CIRCUITS Abstract
In this paper, three different techniques to reduce subthreshold leakage current are implemented in CADENCE 90nm technology. Dual threshold method, leakage current can be reduced by assigning higher Vth to devices in non-critical path, while maintaining performance with low Vth in the critical paths. The Stacking effect is the reduction in subthreshold current when multiple transistors connected in series (stack) are turned off. Sleepy keeper uses traditional sleep transistors plus two additional transistors driven by a gates already calculated output to save state during sleep mode. 1. DUAL