CHAPTER 3

FINITE STATE MACHINE

Learning outcomes
Upon completion of this chapter, students should be able to identify the difference between Moore and Mealy model. explain the concept of finite state machine (FSM) and its relationship with Moore and Mealy model. design a finite state machine (FSM) circuit

Introduction
Counter is known as simple FSM because it has a regular numeric count sequence and less function. Definition of FSM: a sequential logic with a fixed number of possible states and has multiple functions. Synchronous sequential circuits can be drawn in the forms shown in Figure 1. These forms are called finite state machine (FSM).

Figure 1: Finite state machine: (a) Moore machine (b) Mealy machine

Introduction (continue)
In a digital circuit, an FSM may be built using a programmable logic device (PLD), a programmable logic controller (PLC), logic gates and flip flops or relays.
Models for representing FSM Moore model (Edward F. Moore) Mealy model (George H. Mealy)

Application of FSM
FSM is actually a concept that are used for:
designing Visual Basic programs logic circuits firmware for a microcontroller Many computers and microprocessor chips have, at their hearts, an FSM.

Other applications of FSM:

Vending machine Elevator Car Airplane Robot

Structure of FSM
A finite state machine is an abstract description of digital hardware. In general, a finite state machine can be split into three parts: The State Memory block State Transition Logic block. Output Logic block
(Mealy only)
Input Signals Present state State Transition Logic Next state State Memory Output Logic Output Signals

i) ii) iii)

Clock

Figure 2: Structure of a finite state machine

Structure of FSM (continue)

Basic truth table for FSM
Present state Input Q2 Q1 Q0 I Next state Q2 Q1 Q0 Output Y FF inputs D2 D1 D0

Moore machine
For Moore machine, the output depends on a function of the present state only, therefore the output can change only on a clock edge.
Input Signals State Transition Logic Next state State Memory Present state Output Logic Output Signals

Clock

A [1]
Output

B [0]

A B

Present state Input Q0 I 0 0 0 1 1 0 1 1

Next state Q0 0 1 1 x

Output Y 1 1 0 x

FF inputs D0 0 1 1 x

A = S0 = 0, B = S1 = 1

Moore model (Continue)

PS

A
Inputs

D Q Q

out
Output logic

B clock

D Q Q

Figure: Example of Moore circuit

Example: Moore model

Output is only function of state
specify in state bubble in state diagram example: sequence detector for 01 or 10
0 B/0 0 reset 0 A/0 1 C/0 1 1 0 E/1 1 0 1 D/1 reset 1 0 0 0 0 0 0 0 0 0 0 present state A A B B C C D D E E next input state A 0 B 1 C 0 B 1 D 0 E 1 C 0 E 1 C 0 B 1 D output 0 0 0 0 0 0 1 1 1 1

Exercise 1(Moore)
By referring to Figure 1, fill in the truth table below.
0 S0 [0] 1 S1 0 [0] 1 S2 [1] 1 0

Present state Q1 Q0

Input I

Next state Q1 Q0

Output Y

Flip-flop inputs D1 D0

Figure 1

Answer Exercise 1
Present state Input Q1 Q0 I 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Next state Q1 Q0 0 0 0 1 0 0 1 0 0 0 1 0 x x x x Output Y 0 0 0 0 1 1 x x FF inputs D1 D0 0 0 0 1 0 0 1 0 0 0 1 0 x x x x

S0

S1

S2

Exercise 2 (Moore)
Draw a truth table for Figure 2 below. This design should use D flip-flops.

Figure 2

Answer Exercise 2
1.

Step by step solution Analyze the figure and transfer into a truth table
Present state S0 S0 S1 S1 S2 S2 S3 S3 Input I 0 1 0 1 0 1 0 1 Next state S2 S1 S2 S1 S3 S2 S2 S0 Output Y 0 0 0 0 1 1 1 1

2.

Identify the number of bits 2n = number of states , n = number of bits 2n = 4 n = 2 bits Q1, Q0 (From here, we can conclude that the possible states are 00, 01, 10 and 11.

Answer Exercise 2 (continue)

3.

State encoding S0 = 00 S1 = 01 S2 = 10 S3 = 11 Convert into real truth table

Present state Q1 Q0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Input I 0 1 0 1 0 1 0 1 Next state Q1 Q0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 Output Y 0 0 0 0 1 1 1 1 FF inputs D1 D0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0

4.

S0 S1 S2 S3

Exercise 3 (Moore)
Draw a logic circuit from the truth table you obtain from Exercise 2.

Answer Exercise 3
Truth table from exercise 2.
Present state Q1 Q0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Input I 0 1 0 1 0 1 0 1 Next state Q1 Q0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 Output Y 0 0 0 0 1 1 1 1 FF inputs D1 D0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0

3 inputs Step 1: Draw a k-map for these columns: Output (Y) and each bit for flip-flop inputs (D1 and D0)

Answer Exercise 3 (continue)

Step 2: Draw the logic circuit

Exercise 4 (Moore)
Draw the truth table and logic circuit for the diagram below. Use D ff.
0

S0 [0] 1 0 0 S1 [0] S4 [1]

1 1 S2 [0] 0 0

S3 [0]

Answer exercise 4
Total number of state = 5, Truth table
Present state Q2 Q1 Q0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Input I 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next state Q2 Q1 Q0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 1 X X X X X X X X X X X X X X X X X X
Q1 Q0' Q1 I' Q1' Q0 I D0 Q1' Q0 I' Q0' CLK Q1' Q2' Q0 D1 Q1

3 bit = Q2, Q1, Q0

Output Flip-flop inputs Y D2 D1 D0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X

Q2 I' Q1 Q0 I

Y = Q2
D2 = Q2.I' +Q1.Q0.I

D1 = Q1Q0' +Q1.I' +Q1'.Q0.I

D0 = Q0'.I' +Q1'.Q0.I'

Q0' I

D2

Q2

Mealy machine
Mealy machines: the output depends on the function of the present state and current inputs, therefore the output can change when any input changes. The outputs can change immediately after a change at the inputs, independent of the clock. A Mealy machine constructed in this fashion has asynchronous outputs.

Input Signals

State Transition Logic

Next state

State Memory

Present state

Output Logic

Output Signals

Clock

input 0/1 A Output while in state A, if input is 1 1/0

output 0/1 B

A B

Present state Q0 0 0 1 1

Input I 0 1 0 1

Next state Q0 0 1 1 X

Output Y 1 0 1 X

FF inputs D0 0 1 1 X

Mealy model (Continue)

Figure: Examples of Mealy circuit

Example: Mealy model

Output is function of state and inputs
specify output on transition arc between states example: sequence detector for 01 or 10
0/0 B 0/0 reset/0 A 1/0 C 1/0 0/1 1/1 reset 1 0 0 0 0 0 0 current state input A 0 A 1 B 0 B 1 C 0 C 1 next state A B C B C B C output 0 0 0 0 1 1 0

Comparison between Moore and Mealy FSM

Exercise 1 (Mealy)
Draw a truth table and logic circuit for Figure 4 below. This design should use D ff.

Figure 4

Answer Exercise 1 (Mealy)

1.

Step by step solution Analyze the figure and transfer into a truth table
Present state Q1 Q0 S0 S0 S1 S1 S2 S2 S3 S3 Input I 0 1 0 1 0 1 0 1 Next state Q1 Q0 S2 S1 S2 S1 S3 S2 S2 S0 Output Y 0 0 0 1 0 0 0 1 FF inputs D1 D0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0

2.

Identify the number of bits 2n = number of states , n = number of bits 2n = 4 n = 2 bits Q1, Q0 (From here, we can conclude that the possible states are 00, 01, 10 and 11.

Answer Exercise 1 (Mealy)

3.

State encoding S0 = 00 S1 = 01 S2 = 10 S3 = 11 Convert into real truth table

Present state Q1 Q0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Input I 0 1 0 1 0 1 0 1 Next state Q1 Q0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 Output Y 0 0 0 1 0 0 0 1 FF inputs D1 D0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0

4.

Answer Exercise 1 (Mealy)

5.

Draw the k-map

5.

Draw the logic circuit

Exercise 2 (Mealy)
Draw a truth table and logic circuit for the figure below. This design should use T ff.
0/0 1/0 1/0
SO S1

1/1

0/0
S2 S3

1/1 0/1 0/0 1/1

S5 S4

0/0

0/1

Answer Exercise 2 (Mealy)

Present state Q2 Q1 Q0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Input I 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next state Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 0 1 1 0 1 X X X X X X X X X X X X X X X Output Flip-flop inputs Y T2 T1 T0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 X X X X X X X X X X X X X X X X X X X X

Answer Exercise 2 (Mealy)

Q1 I Y Q1 Q0 Q2 Q0' I' Q1 Q0 I' T2 Q2 Q1 I' Q2 Q0' I' Q2' Q0 I'

Q2 Q0' Q0' I T1 Q1 Q2' Q0 I' T0 Q0

Q2' CLK

Q1'

Q0'

Moore to Mealy conversion

A Moore machine can be converted into Mealy machine and vice versa. However conversion from Mealy to Moore machine is rarely be done.

Output from next state of Moore machine Moore machine Mealy machine

Example: Moore to Mealy conversion

input 0
0/0

Output for next state

0 0

1 1

Moore machine

Mealy machine

State minimization
Advantage of Mealy: often leads to a reduction of the number of states. # To be apply in Question 1 page 154. The number of states can be reduced by using the concept of equivalent states. Two states are equivalent if both states provide the same outputs for identical inputs. One of the states can be eliminated if two states are equivalent. Thus, the number of states can be reduced.

Example: State minimization

Minimize the state below
1/1 0/0 0/0 1/1 V 1/0 1/0 1/0 0/0 W X 0/0 Y 0/0 Z

Example: State minimization (Answer)

Step 1: Draw a truth table based on the state diagram. From the state, identify the same outputs for identical inputs.
Present state V V W W X X Y Y Z Z Input 0 1 0 1 0 1 0 1 0 1 Next state V W Y V Y V Z V V W Output 0 1 0 0 0 0 0 0 0 1

State V is identical with state Z and state W is identical with state X (Input, Next state and output are identical)

Example: State minimization (Answer)

Step 2: Because V and Z are equivalent, one of the states can be removed; Z is removed. Also, W and X are equivalent, so one of the states can be removed; X is thus eliminated in the state table.
Present state V V W W X X Y Y Z Z Input 0 1 0 1 0 1 0 1 0 1 Next state V W Y V Y V Z V V W Output 0 1 0 0 0 0 0 0 0 1

Example: State minimization (Answer)

Step 3: The row with present states X and Z is eliminated. If they appear in the next state columns, they must be replaced by their equivalent states. In this case, the row for state Y contains Z in the next column. This is replaced by its equivalent state V.
Present state V V W W X X Y Y Z Z Input 0 1 0 1 0 1 0 1 0 1 Next state V W Y V Y V Z V V V W Output 0 1 0 0 0 0 0 0 0 1

Example: State minimization (Answer)

Step 4: Draw the new truth table
Present state V V W W Y Y Input 0 1 0 1 0 1 Next state V W Y V V V Output 0 1 0 0 0 0

Step 5: Draw the new state diagram

0/0 1/1 V 1/0 0/0 1/0 W 0/0 Y

Application: A simple vending machine

The vending machine delivers a package of gums after it has received 15 cents in coins. The machine has a single coin slot that accepts nickels (5 cents) and dimes (10 cents), one coin at a time. A mechanical sensor indicates to the control whether a dime or nickel has been inserted into the coin slot. The controllers output causes a single package of gum to be released down a chute to the customer. One further specification: we will design our machine so it does not give change. A customer who pays with two dimes is out 5 cents!

Procedure:
1.

Understanding the problem Draw a block diagram to understand the inputs and outputs. The machine asserts Open for one clock period when 15 cents (or more) has been deposited since the last reset. Assume that the coin sensor returns any coins it does not recognize, leaving N and D unasserted. Assume that external logic resets the machine after the gum is delivered.
N Coin Sensor D Reset Clk Vending Open Gum Machine Release FSM Mechanism

Figure: Vending machine block diagram

Procedure (Continue)
2.

Abstract representations Once you understand the behavior reasonably well, it is time to map the specification into a more suitable abstract representation. A good way to begin this is by enumerating the possible unique sequences of inputs. These will help define the states of the FSM. Possible input sequence: Three nickels in sequence: N, N, N Two nickels followed by a dime: N, N, D A nickel followed by a dime: N, D A dime followed by a nickel: D, N Two dimes in sequence: D, D

Procedure (Continue)
State diagram representation:

Figure: Unminimized state diagram

Procedure (Continue)
3. State minimization. Since states S4, S5, S6, S7 and S8 have identical behavior, they can be combined into a single state.

present state 0

10

15

inputs D N 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

next state 0 5 10 5 10 15 10 15 15 15

output open 0 0 0 0 0 0 0 0 0 1

symbolic state table

Procedure (Continue)
Moore machine
outputs associated with state
Reset N D + Reset

0 [0] N D 5 [0] N D 10 [0] N+D 15 [1]

N D

N D

N D

Reset

Procedure (Continue)
4. State encoding. A natural state assignment would encode the states in 2-bits: state 0 as 00, state 5 as 01, state 10 as 10 and state 15 as 11. Implementation using D flip-flop.
Present state Q1 Q0 Inputs D N Next state Q1+ Q0+ Ouput Open Flip-flop inputs D1 D0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X

0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X

0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X

0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X

0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X

Moore implementation for D flip-flop

Q1Q0 DN 00 01 11 10 00 01 11 10 Q1Q0 DN 00 01 11 10 D1 00 01 11 10 Q1Q0 DN 00 01 11 10 D0 00 01 11 10

0 0 X 1

0 1 X 1

1 1 X 1

1 1 X 1

0 1 X 0

1 0 X 1

1 1 X 1

0 1 X 1

0 0 X 0

0 0 X 0

1 1 1 X 1

0 0 X 0
Open

D1 = Q1 + D + Q0 N

D0 = N Q0 + Q0 N + Q1 N + Q1 D
Q1 D D1 CLK
CLR

Open = Q1Q 0

SET

Q1

Q0 N N \Q0 Q0 \N Q1 N Q1 D

Reset Open

D0 CLK

SET

Q0

CLR

Reset

Vending machine FSM implementation based on D flip-flops(Moore).

Moore implementation for JK flip-flop

Encoded vending machine state transition table (using JK flipflop)

Figure: Encoded vending machine state transition table using JK flip-flop

Moore implementation for JK flip-flop

Vending machine FSM implementation based on JK flip-flops(Moore).

Example: Mealy implementation

Reset/0 Reset/0 0 N/0 D/0 N/0 D/1 N+D/1 15 Reset/1 10 N D/0 5 N D/0 N D/0

present state inputs Q1 Q0 D N 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1

next state D1 D0 0 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 1 1

output open 0 0 0 0 0 1 0 1 1 1

Example: Mealy implementation

Table: State transition table for Mealy implementation
Present state Q1 Q0 0 0 Inputs D N 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next state Q1+ Q0+ 0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X Ouput Open 0 0 0 X 0 0 1 X 0 1 1 X 1 1 1 X Flip-flop inputs D1 D0 0 0 1 X 0 1 1 X 1 1 1 X 1 1 1 X 0 1 0 X 1 0 1 X 0 1 1 X 1 1 1 X

Example: Mealy implementation

Q1Q0 DN 00 01 11 10 00 01 11 10 Q1Q0 DN 00 01 11 10 D1 00 01 11 10 Q1Q0 DN 00 01 11 10 D0 00 01 11 10

0 0 X 1

0 1 X 1

1 1 X 1

1 1 X 1

0 1 X 0

1 0 X 1

1 1 X 1

0 1 X 1

0 0 X 0

0 0 X 1 0

0 1 X 1

0 1 0 1 X 1 0
Open

D1 = Q1 + D + Q0 N

D0 = N Q0 + Q0 N + Q1 N + Q1 D

Open = Q1Q 0 + Q1 N + Q 0 D

Vending machine FSM implementation based on D flip-flops(Mealy).

Summary
The Moore machine offers a simpler implementation when the output values depend only on the state and not on the transition. A Moore machine requires less hardware to produce the output values than does a Mealy machine, since its outputs depend only on its state. The outputs of a Mealy machine is well suited for representing the control units of microprocessors and central processing units. The use of a Mealy FSM often leads to a reduction of the number of states.