Appl. Phys. A 74, 541543 (2002) / Digital Object Identier (DOI) 10.

1007/s003390100927

Applied Physics A
Materials Science & Processing

Nanocrystalline silicon thin-lm transistors with 50-nm-thick deposited channel layer, 10 cm2V1s1 electron mobility and 108 on/off current ratio
R.B. Min , S. Wagner
Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA Received: 28 May 2001/Accepted: 30 May 2001/Published online: 30 August 2001 Springer-Verlag 2001

Abstract. Thin-lm transistors were made using 50-nm-thick directly deposited nanocrystalline silicon channel layers. The transistors have a coplanar top gate structure. The nanocrystalline silicon was deposited from discharges in silane, hydrogen and silicon tetrauoride. The transistors combine a high electron eld effect mobility of 10 cm2 V1 s1 with a low off current of 1014 A per m of channel length and an on/off current ratio of 108. This result shows that transistors made from directly deposited silicon can combine high mobility with low off currents. PACS: 81.05.Gc; 81.15.Gh; 85.30.-z Integrated backplane circuits are the key to the widespread application of large-area electronics, which today comprises liquid crystal displays and X-ray detector arrays, but eventually will extend to sensor skin, mechatronic materials and electrotextiles. These large-area backplane circuits will be based on unit cells, or pixels, which contain the basic function and its control, for example a light emitter switched and powered by a sample-and-hold circuit. Each cell may contain some intelligence used for local signal processing in amplication, addressing and multiplexing. A neighborhood of cells will be controlled by a higher-performance circuit, and the entire backplane will be addressed by driver circuits. Pervasive circuit integration will be needed to make such backplanes affordable. Such integration requires that a single transistor material and process be used for all hierarchical functions, ranging from switching to high-speed signal reception and multiplexing. In other words, the backplane transistor technology should perform similarly to complementary metaloxide-semiconductor (CMOS) circuits made in single-crystal silicon. For this reason we have been pursuing thin-lm transistor technology based on nanocrystalline silicon, nc-Si:H. This semiconductor can provide sufcient electron mobility [14] and hole mobility to host CMOS circuits [1, 2],
Corresponding

and it can be made at temperatures that are compatible with the plastic substrates envisaged for roll-to-roll production [4]. However, nc-Si:H is a complex material whose deposition and device processing are not yet mature [5]. The highmobility material develops only over a certain lm thickness and then often is coupled with a high transistor leakage current in the off state. It is this specic problem that we addressed by fabricating nc-Si:H thin-lm transistors (TFTs) with very thin i-layers. Figure 1 shows the transfer characteristic of an earlier ncSi:H n-channel thin-lm transistor [1]. Its on current is at least one order of magnitude higher than that of amorphous silicon TFTs of comparable channel width/length ratios. This is a manifestation of high electron mobility. Also note that the off current is 109 A, a value that lies three orders of magnitude above the value needed for an active-matrix pixel switch. The origin of this high off current is shown in Fig. 2. As the thickness of the nc-Si:H lm grows from 50 to 350 nm,

author. (Fax: +1-609/258-1840, E-mail: bobmin@princeton.edu)

Fig. 1. Transfer characteristics of an early n-channel thin-lm transistor made from nc-Si:H (from [1]). Note the off current of 109 A

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the thickness-averaged lm conductivity is seen to rise by about ve orders of magnitude. This rise in conductivity is composed of a rise in carrier mobility by nearly two orders of magnitude and a rise in carrier density that can vary greatly in magnitude between deposition runs. The in-plane electron eld effect mobilities n measured to date in a-Si:H (which is the rst-to-grow layer at the bottom of the nc-Si:H lm) and the nc-Si:H at the top of the lm are 1 cm2 V1 s1 and 40 cm2 V1 s1 respectively. The conductivity rises with lm thickness up to typically a few hundred nm and then levels off at a saturation thickness. The highest TFT on currents are then obtained with channel lms of saturation thickness. This rise of n with lm thickness is the principal reason for making nc-Si:H TFTs in the top gate conguration, to take advantage of the mobility that is highest at the very top of the lm. (No comparable information exists about the hole eld effect mobility p .) Because of the low built-in electrostatic barrier between source/drain and the channel, the TFT off current is simply the conduction current of the channel lm in the at-band condition. This observation makes reducing the free electron density in the neutral channel lm essential. The off current must be as low as possible if the TFT is to be used as a switch (for voltage stability in the cell) and for CMOS circuits (to minimize power consumption). The electron density can be made low by gettering oxygen and water from the source gases [6], by compensation doping [7] or by depositing in the presence of chlorine [4, 8]. The lowest conductivity obtained in nc-Si:H at room temperature is 107 S/cm, which is equal to the conductivity of intrinsic crystalline silicon. Growing from SiH4 + H2 with the addition of SiF4 promotes crystallization [9], and this is the approach we took to obtain our very thin channel lms. From glow discharges excited at 13.56 MHz, nc-Si:H grows at a rate of typically 0.1 nm/s1 . This low growth rate is interpreted as the consequence of the etching of amorphous tissue during growth, with the less etchable crystalline material remaining. The growth rate is too low for the industrialization of solar cells and even for TFT fabrication, for which process steps as brief as one minute are desired. The slow growth rate of nc-Si:H is a secondary motive for fabricating very thin channel layers.

Thus the ideal nc-Si:H lm would (I) grow fast, (II) grow to its highest carrier mobility in a small thickness and (III) have low electrical conductivity. In separate experiments we are pursuing the plasma-enhanced chemical vapor deposition (PECVD) growth of nc-Si:H for TFTs at 80-MHz excitation frequency (goal I), and the reduction of conductivity by chlorine doping (goal III) [4]. Here we report the results of experiments designed to develop a TFT-grade nc-Si:H structure in a very thin lm (goal II). 1 Experiments The nanocrystalline TFTs were made in the top gate coplanar source/drain conguration of Fig. 3. Source and drain layers are deposited and not self-aligned. Because we design and print our own photolithographic masks, our patterns are fairly large: the channels are 180-m wide and 45-m long. The nc-Si:H channel layer is deposited on Corning 1737 glass by plasma-enhanced chemical vapor deposition, in a process similar to the deposition of a-Si:H, from a mixture of 50 sccm of H2 , 2 sccm of SiH4 and 35 sccm of SiF4 at a pressure of 900 mTorr and an RF power density of 110 mW cm2. The deposition time of the i-layer was 15 min, realizing a thickness of 50 nm. Phenomenologically it is this slow growth at 0.05 nm s1 that produces nanocrystalline structure in the very thin lm. Next, the 80-nm n+ source/drain layer was grown on top of the i-layer in a separate chamber of the PECVD machine without breaking vacuum. The deposition temperatures were 350 C for both layers. The n+ microcrystalline silicon was then patterned by reactive ion etching (RIE) based on a mixture of SF6 and CCl2 F2 to form source and drain regions. The RIE power and pressure were 50 W and 200 mTorr respectively. This patterning etch is a demanding process step, because even a slight overetch may rupture the thin channel layer (see also [4]). The next step was to dene the TFT island before a 270-nm SiO2 gate dielectric was deposited also by PECVD but in a separate system and at a temperature of 250 C. Finally, contact holes were etched into the SiO2 using HFbased buffered oxide etch, and 300 nm of aluminum thermally evaporated and patterned for gate, source and drain contacts.

Fig. 2. Thickness-averaged electrical conductivity and thermal activation energy of nc-Si:H lms as a function of their thickness (from [1])

Fig. 3. Schematic cross section of the nanocrystalline silicon thin-lm transistor. The coplanar top gate structure uses deposited, non-self-aligned source and drain layers

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Fig. 4. a Transfer and b current voltage characteristics of the TFT of Fig. 3. Note the high on current that corresponds to an electron eld effect mobility of 10 cm2 V1 s1 , and the low off current

2 Results and discussion The TFTs were evaluated with an HP 4155A parameter analyzer. Figure 4 shows (a) the transfer and (b) the output characteristics of a TFT using the directly deposited 50-nmthick channel layer. We calculated the threshold voltage Vth and the electron eld effect mobility in the linear regime lin from the linear plot of drain current Ids vs gate voltage Vgs at a drain voltage Vds = 0.1 V, and the electron mobility in the saturated regime sat from the linear plot of (Ids )1/2 vs Vgs at Vds = 10 V. This transistor has Vth = 25 V, lin = cm2 V1 s1 and sat = 11 cm2 V1 s1 . The off current, dened as the lowest current in the transfer characteristics, is 1 1012 A at Vds = 10 V for this TFT with a gate width W of 180 m and a length L of 45 m. This value is comparable to the off currents of amorphous silicon TFTs made in our laboratory on glass substrates and provides an on/off current ratio of 108 . The sub-threshold slope S is extracted from the log plot of Id vs Vgs at the turn-on point in the transfer characteristics. All transistors have S of 2.5 V/decade. The high values of Vth , S and the crossover of the Vds = 10 V and 0.1 V curves suggest that the Si/SiO2 interface requires improvement. A regular experience in our work with new TFT materials has been that the introduction of a new channel material entrains the need for revising the entire device-fabrication process. The primary target for material improvement is the gate dielectric, which needs substantial improvement as the values of Vth and S show. Because the coplanar top gate structure poses considerable processing difculties, experimentation with alternative device structures that can be processed more easily will also be important [4].

3 Conclusions The goal of the study that we report here was to demonstrate a combination of high on current with low off current in TFTs made from directly deposited silicon. Combined with our ability to grow nanocrystalline silicon on a plastic substrate, and with more easily fabricated device structures [4], our present results make nc-Si:H a serious contender for both switching and driver circuits in high-performance large-area electronics.
Acknowledgements. Support of this work by DARPAs HDS Program and by the New Jersey Commission on Science and Technology is gratefully acknowledged.

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